2005-04-16 22:20:36 +00:00
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/*
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* x86 SMP booting functions
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*
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* (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
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* (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
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* Copyright 2001 Andi Kleen, SuSE Labs.
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*
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* Much of the core SMP work is based on previous work by Thomas Radke, to
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* whom a great many thanks are extended.
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*
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* Thanks to Intel for making available several different Pentium,
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* Pentium Pro and Pentium-II/Xeon MP machines.
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* Original development of Linux SMP code supported by Caldera.
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*
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2005-04-16 22:25:19 +00:00
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* This code is released under the GNU General Public License version 2
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2005-04-16 22:20:36 +00:00
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*
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* Fixes
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* Felix Koop : NR_CPUS used properly
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* Jose Renau : Handle single CPU case.
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* Alan Cox : By repeated request 8) - Total BogoMIP report.
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* Greg Wright : Fix for kernel stacks panic.
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* Erich Boleyn : MP v1.4 and additional changes.
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* Matthias Sattler : Changes for 2.1 kernel map.
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* Michel Lespinasse : Changes for 2.1 kernel map.
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* Michael Chastain : Change trampoline.S to gnu as.
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* Alan Cox : Dumb bug: 'B' step PPro's are fine
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* Ingo Molnar : Added APIC timers, based on code
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* from Jose Renau
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* Ingo Molnar : various cleanups and rewrites
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* Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
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* Maciej W. Rozycki : Bits for genuine 82489DX APICs
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* Andi Kleen : Changed for SMP boot into long mode.
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2005-04-16 22:25:19 +00:00
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* Rusty Russell : Hacked into shape for new "hotplug" boot process.
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* Andi Kleen : Converted to new state machine.
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* Various cleanups.
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* Probably mostly hotplug CPU ready now.
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2005-04-16 22:20:36 +00:00
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*/
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2005-04-16 22:25:19 +00:00
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2005-04-16 22:20:36 +00:00
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/kernel_stat.h>
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#include <linux/smp_lock.h>
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#include <linux/irq.h>
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#include <linux/bootmem.h>
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#include <linux/thread_info.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/mc146818rtc.h>
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#include <asm/mtrr.h>
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#include <asm/pgalloc.h>
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#include <asm/desc.h>
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#include <asm/kdebug.h>
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#include <asm/tlbflush.h>
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#include <asm/proto.h>
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2005-04-16 22:25:19 +00:00
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/* Change for real CPU hotplug. Note other files need to be fixed
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first too. */
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#define __cpuinit __init
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#define __cpuinitdata __initdata
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2005-04-16 22:20:36 +00:00
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/* Number of siblings per CPU package */
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int smp_num_siblings = 1;
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/* Package ID of each logical CPU */
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u8 phys_proc_id[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
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2005-04-16 22:25:15 +00:00
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u8 cpu_core_id[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
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2005-04-16 22:20:36 +00:00
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EXPORT_SYMBOL(phys_proc_id);
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2005-04-16 22:25:15 +00:00
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EXPORT_SYMBOL(cpu_core_id);
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2005-04-16 22:20:36 +00:00
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/* Bitmask of currently online CPUs */
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cpumask_t cpu_online_map;
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2005-04-16 22:25:19 +00:00
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EXPORT_SYMBOL(cpu_online_map);
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/*
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* Private maps to synchronize booting between AP and BP.
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* Probably not needed anymore, but it makes for easier debugging. -AK
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*/
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2005-04-16 22:20:36 +00:00
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cpumask_t cpu_callin_map;
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cpumask_t cpu_callout_map;
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2005-04-16 22:25:19 +00:00
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cpumask_t cpu_possible_map;
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EXPORT_SYMBOL(cpu_possible_map);
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2005-04-16 22:20:36 +00:00
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/* Per CPU bogomips and other parameters */
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struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
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2005-04-16 22:25:19 +00:00
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/* Set when the idlers are all forked */
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int smp_threads_ready;
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2005-04-16 22:20:36 +00:00
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cpumask_t cpu_sibling_map[NR_CPUS] __cacheline_aligned;
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2005-04-16 22:25:15 +00:00
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cpumask_t cpu_core_map[NR_CPUS] __cacheline_aligned;
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2005-04-16 22:20:36 +00:00
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/*
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* Trampoline 80x86 program as an array.
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*/
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2005-04-16 22:25:19 +00:00
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extern unsigned char trampoline_data[];
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extern unsigned char trampoline_end[];
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2005-04-16 22:20:36 +00:00
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/*
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* Currently trivial. Write the real->protected mode
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* bootstrap into the page concerned. The caller
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* has made sure it's suitably aligned.
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*/
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2005-04-16 22:25:19 +00:00
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static unsigned long __cpuinit setup_trampoline(void)
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2005-04-16 22:20:36 +00:00
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{
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void *tramp = __va(SMP_TRAMPOLINE_BASE);
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memcpy(tramp, trampoline_data, trampoline_end - trampoline_data);
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return virt_to_phys(tramp);
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}
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/*
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* The bootstrap kernel entry code has set these up. Save them for
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* a given CPU
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*/
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2005-04-16 22:25:19 +00:00
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static void __cpuinit smp_store_cpu_info(int id)
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2005-04-16 22:20:36 +00:00
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{
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struct cpuinfo_x86 *c = cpu_data + id;
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*c = boot_cpu_data;
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identify_cpu(c);
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}
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/*
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2005-04-16 22:25:19 +00:00
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* Synchronize TSCs of CPUs
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2005-04-16 22:20:36 +00:00
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*
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2005-04-16 22:25:19 +00:00
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* This new algorithm is less accurate than the old "zero TSCs"
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* one, but we cannot zero TSCs anymore in the new hotplug CPU
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* model.
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2005-04-16 22:20:36 +00:00
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*/
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2005-04-16 22:25:19 +00:00
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static atomic_t __cpuinitdata tsc_flag;
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static __cpuinitdata DEFINE_SPINLOCK(tsc_sync_lock);
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static unsigned long long __cpuinitdata bp_tsc, ap_tsc;
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2005-04-16 22:20:36 +00:00
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#define NR_LOOPS 5
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2005-04-16 22:25:19 +00:00
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static void __cpuinit sync_tsc_bp_init(int init)
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2005-04-16 22:20:36 +00:00
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{
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2005-04-16 22:25:19 +00:00
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if (init)
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_raw_spin_lock(&tsc_sync_lock);
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else
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_raw_spin_unlock(&tsc_sync_lock);
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atomic_set(&tsc_flag, 0);
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}
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2005-04-16 22:20:36 +00:00
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2005-04-16 22:25:19 +00:00
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/*
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* Synchronize TSC on AP with BP.
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*/
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static void __cpuinit __sync_tsc_ap(void)
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{
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if (!cpu_has_tsc)
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return;
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Dprintk("AP %d syncing TSC\n", smp_processor_id());
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while (atomic_read(&tsc_flag) != 0)
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cpu_relax();
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atomic_inc(&tsc_flag);
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mb();
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_raw_spin_lock(&tsc_sync_lock);
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wrmsrl(MSR_IA32_TSC, bp_tsc);
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_raw_spin_unlock(&tsc_sync_lock);
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rdtscll(ap_tsc);
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mb();
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atomic_inc(&tsc_flag);
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mb();
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2005-04-16 22:20:36 +00:00
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}
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2005-04-16 22:25:19 +00:00
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static void __cpuinit sync_tsc_ap(void)
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2005-04-16 22:20:36 +00:00
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{
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int i;
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2005-04-16 22:25:19 +00:00
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for (i = 0; i < NR_LOOPS; i++)
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__sync_tsc_ap();
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}
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2005-04-16 22:20:36 +00:00
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2005-04-16 22:25:19 +00:00
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/*
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* Synchronize TSC from BP to AP.
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*/
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static void __cpuinit __sync_tsc_bp(int cpu)
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{
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if (!cpu_has_tsc)
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return;
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2005-04-16 22:20:36 +00:00
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2005-04-16 22:25:19 +00:00
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/* Wait for AP */
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while (atomic_read(&tsc_flag) == 0)
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cpu_relax();
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/* Save BPs TSC */
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sync_core();
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rdtscll(bp_tsc);
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/* Don't do the sync core here to avoid too much latency. */
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mb();
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/* Start the AP */
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_raw_spin_unlock(&tsc_sync_lock);
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/* Wait for AP again */
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while (atomic_read(&tsc_flag) < 2)
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cpu_relax();
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rdtscl(bp_tsc);
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barrier();
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}
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2005-04-16 22:20:36 +00:00
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2005-04-16 22:25:19 +00:00
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static void __cpuinit sync_tsc_bp(int cpu)
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{
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int i;
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for (i = 0; i < NR_LOOPS - 1; i++) {
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__sync_tsc_bp(cpu);
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sync_tsc_bp_init(1);
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2005-04-16 22:20:36 +00:00
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}
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2005-04-16 22:25:19 +00:00
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__sync_tsc_bp(cpu);
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printk(KERN_INFO "Synced TSC of CPU %d difference %Ld\n",
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cpu, ap_tsc - bp_tsc);
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2005-04-16 22:20:36 +00:00
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}
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2005-04-16 22:25:19 +00:00
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static atomic_t init_deasserted __cpuinitdata;
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2005-04-16 22:20:36 +00:00
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2005-04-16 22:25:19 +00:00
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/*
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* Report back to the Boot Processor.
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* Running on AP.
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*/
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void __cpuinit smp_callin(void)
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2005-04-16 22:20:36 +00:00
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{
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int cpuid, phys_id;
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unsigned long timeout;
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/*
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* If waken up by an INIT in an 82489DX configuration
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* we may get here before an INIT-deassert IPI reaches
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* our local APIC. We have to wait for the IPI or we'll
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* lock up on an APIC access.
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*/
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2005-04-16 22:25:19 +00:00
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while (!atomic_read(&init_deasserted))
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cpu_relax();
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2005-04-16 22:20:36 +00:00
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/*
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* (This works even if the APIC is not enabled.)
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*/
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phys_id = GET_APIC_ID(apic_read(APIC_ID));
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cpuid = smp_processor_id();
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if (cpu_isset(cpuid, cpu_callin_map)) {
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panic("smp_callin: phys CPU#%d, CPU#%d already present??\n",
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phys_id, cpuid);
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}
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Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
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/*
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* STARTUP IPIs are fragile beasts as they might sometimes
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* trigger some glue motherboard logic. Complete APIC bus
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* silence for 1 second, this overestimates the time the
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* boot CPU is spending to send the up to 2 STARTUP IPIs
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* by a factor of two. This should be enough.
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*/
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/*
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* Waiting 2s total for startup (udelay is not yet working)
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*/
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timeout = jiffies + 2*HZ;
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while (time_before(jiffies, timeout)) {
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/*
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* Has the boot CPU finished it's STARTUP sequence?
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*/
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if (cpu_isset(cpuid, cpu_callout_map))
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break;
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2005-04-16 22:25:19 +00:00
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cpu_relax();
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2005-04-16 22:20:36 +00:00
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}
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if (!time_before(jiffies, timeout)) {
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panic("smp_callin: CPU%d started up but did not get a callout!\n",
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cpuid);
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}
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/*
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* the boot CPU has finished the init stage and is spinning
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* on callin_map until we finish. We are free to set up this
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* CPU, first the APIC. (this is probably redundant on most
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* boards)
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*/
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Dprintk("CALLIN, before setup_local_APIC().\n");
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setup_local_APIC();
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/*
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* Get our bogomips.
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*/
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calibrate_delay();
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Dprintk("Stack at about %p\n",&cpuid);
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disable_APIC_timer();
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/*
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* Save our processor parameters
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*/
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smp_store_cpu_info(cpuid);
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/*
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* Allow the master to continue.
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*/
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cpu_set(cpuid, cpu_callin_map);
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}
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/*
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2005-04-16 22:25:19 +00:00
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* Setup code on secondary processor (after comming out of the trampoline)
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2005-04-16 22:20:36 +00:00
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*/
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2005-04-16 22:25:19 +00:00
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void __cpuinit start_secondary(void)
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2005-04-16 22:20:36 +00:00
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{
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/*
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* Dont put anything before smp_callin(), SMP
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* booting is too fragile that we want to limit the
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* things done here to the most necessary things.
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*/
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cpu_init();
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smp_callin();
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2005-04-16 22:25:19 +00:00
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/*
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* Synchronize the TSC with the BP
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*/
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sync_tsc_ap();
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2005-04-16 22:20:36 +00:00
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/* otherwise gcc will move up the smp_processor_id before the cpu_init */
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barrier();
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Dprintk("cpu %d: setting up apic clock\n", smp_processor_id());
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setup_secondary_APIC_clock();
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2005-04-16 22:25:19 +00:00
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Dprintk("cpu %d: enabling apic timer\n", smp_processor_id());
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2005-04-16 22:20:36 +00:00
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if (nmi_watchdog == NMI_IO_APIC) {
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disable_8259A_irq(0);
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|
|
enable_NMI_through_LVT0(NULL);
|
|
|
|
enable_8259A_irq(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-04-16 22:25:19 +00:00
|
|
|
enable_APIC_timer();
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
/*
|
2005-04-16 22:25:19 +00:00
|
|
|
* Allow the master to continue.
|
2005-04-16 22:20:36 +00:00
|
|
|
*/
|
|
|
|
cpu_set(smp_processor_id(), cpu_online_map);
|
2005-04-16 22:25:19 +00:00
|
|
|
mb();
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
cpu_idle();
|
|
|
|
}
|
|
|
|
|
2005-04-16 22:25:19 +00:00
|
|
|
extern volatile unsigned long init_rsp;
|
2005-04-16 22:20:36 +00:00
|
|
|
extern void (*initial_code)(void);
|
|
|
|
|
|
|
|
#if APIC_DEBUG
|
2005-04-16 22:25:19 +00:00
|
|
|
static void inquire_remote_apic(int apicid)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
|
|
|
unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
|
|
|
|
char *names[] = { "ID", "VERSION", "SPIV" };
|
|
|
|
int timeout, status;
|
|
|
|
|
|
|
|
printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid);
|
|
|
|
|
|
|
|
for (i = 0; i < sizeof(regs) / sizeof(*regs); i++) {
|
|
|
|
printk("... APIC #%d %s: ", apicid, names[i]);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Wait for idle.
|
|
|
|
*/
|
|
|
|
apic_wait_icr_idle();
|
|
|
|
|
|
|
|
apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
|
|
|
|
apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]);
|
|
|
|
|
|
|
|
timeout = 0;
|
|
|
|
do {
|
|
|
|
udelay(100);
|
|
|
|
status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
|
|
|
|
} while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
|
|
|
|
|
|
|
|
switch (status) {
|
|
|
|
case APIC_ICR_RR_VALID:
|
|
|
|
status = apic_read(APIC_RRR);
|
|
|
|
printk("%08x\n", status);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
printk("failed\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2005-04-16 22:25:19 +00:00
|
|
|
/*
|
|
|
|
* Kick the secondary to wake up.
|
|
|
|
*/
|
|
|
|
static int __cpuinit wakeup_secondary_via_INIT(int phys_apicid, unsigned int start_rip)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
|
|
|
unsigned long send_status = 0, accept_status = 0;
|
|
|
|
int maxlvt, timeout, num_starts, j;
|
|
|
|
|
|
|
|
Dprintk("Asserting INIT.\n");
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Turn INIT on target chip
|
|
|
|
*/
|
|
|
|
apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Send IPI
|
|
|
|
*/
|
|
|
|
apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
|
|
|
|
| APIC_DM_INIT);
|
|
|
|
|
|
|
|
Dprintk("Waiting for send to finish...\n");
|
|
|
|
timeout = 0;
|
|
|
|
do {
|
|
|
|
Dprintk("+");
|
|
|
|
udelay(100);
|
|
|
|
send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
|
|
|
|
} while (send_status && (timeout++ < 1000));
|
|
|
|
|
|
|
|
mdelay(10);
|
|
|
|
|
|
|
|
Dprintk("Deasserting INIT.\n");
|
|
|
|
|
|
|
|
/* Target chip */
|
|
|
|
apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
|
|
|
|
|
|
|
|
/* Send IPI */
|
|
|
|
apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
|
|
|
|
|
|
|
|
Dprintk("Waiting for send to finish...\n");
|
|
|
|
timeout = 0;
|
|
|
|
do {
|
|
|
|
Dprintk("+");
|
|
|
|
udelay(100);
|
|
|
|
send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
|
|
|
|
} while (send_status && (timeout++ < 1000));
|
|
|
|
|
|
|
|
atomic_set(&init_deasserted, 1);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Should we send STARTUP IPIs ?
|
|
|
|
*
|
|
|
|
* Determine this based on the APIC version.
|
|
|
|
* If we don't have an integrated APIC, don't send the STARTUP IPIs.
|
|
|
|
*/
|
|
|
|
if (APIC_INTEGRATED(apic_version[phys_apicid]))
|
|
|
|
num_starts = 2;
|
|
|
|
else
|
|
|
|
num_starts = 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Run STARTUP IPI loop.
|
|
|
|
*/
|
|
|
|
Dprintk("#startup loops: %d.\n", num_starts);
|
|
|
|
|
|
|
|
maxlvt = get_maxlvt();
|
|
|
|
|
|
|
|
for (j = 1; j <= num_starts; j++) {
|
|
|
|
Dprintk("Sending STARTUP #%d.\n",j);
|
|
|
|
apic_read_around(APIC_SPIV);
|
|
|
|
apic_write(APIC_ESR, 0);
|
|
|
|
apic_read(APIC_ESR);
|
|
|
|
Dprintk("After apic_write.\n");
|
|
|
|
|
|
|
|
/*
|
|
|
|
* STARTUP IPI
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* Target chip */
|
|
|
|
apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
|
|
|
|
|
|
|
|
/* Boot on the stack */
|
|
|
|
/* Kick the second */
|
|
|
|
apic_write_around(APIC_ICR, APIC_DM_STARTUP
|
|
|
|
| (start_rip >> 12));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Give the other CPU some time to accept the IPI.
|
|
|
|
*/
|
|
|
|
udelay(300);
|
|
|
|
|
|
|
|
Dprintk("Startup point 1.\n");
|
|
|
|
|
|
|
|
Dprintk("Waiting for send to finish...\n");
|
|
|
|
timeout = 0;
|
|
|
|
do {
|
|
|
|
Dprintk("+");
|
|
|
|
udelay(100);
|
|
|
|
send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
|
|
|
|
} while (send_status && (timeout++ < 1000));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Give the other CPU some time to accept the IPI.
|
|
|
|
*/
|
|
|
|
udelay(200);
|
|
|
|
/*
|
|
|
|
* Due to the Pentium erratum 3AP.
|
|
|
|
*/
|
|
|
|
if (maxlvt > 3) {
|
|
|
|
apic_read_around(APIC_SPIV);
|
|
|
|
apic_write(APIC_ESR, 0);
|
|
|
|
}
|
|
|
|
accept_status = (apic_read(APIC_ESR) & 0xEF);
|
|
|
|
if (send_status || accept_status)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
Dprintk("After Startup.\n");
|
|
|
|
|
|
|
|
if (send_status)
|
|
|
|
printk(KERN_ERR "APIC never delivered???\n");
|
|
|
|
if (accept_status)
|
|
|
|
printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
|
|
|
|
|
|
|
|
return (send_status | accept_status);
|
|
|
|
}
|
|
|
|
|
2005-04-16 22:25:19 +00:00
|
|
|
/*
|
|
|
|
* Boot one CPU.
|
|
|
|
*/
|
|
|
|
static int __cpuinit do_boot_cpu(int cpu, int apicid)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
|
|
|
struct task_struct *idle;
|
|
|
|
unsigned long boot_error;
|
2005-04-16 22:25:19 +00:00
|
|
|
int timeout;
|
2005-04-16 22:20:36 +00:00
|
|
|
unsigned long start_rip;
|
|
|
|
/*
|
|
|
|
* We can't use kernel_thread since we must avoid to
|
|
|
|
* reschedule the child.
|
|
|
|
*/
|
|
|
|
idle = fork_idle(cpu);
|
2005-04-16 22:25:19 +00:00
|
|
|
if (IS_ERR(idle)) {
|
|
|
|
printk("failed fork for CPU %d\n", cpu);
|
|
|
|
return PTR_ERR(idle);
|
|
|
|
}
|
2005-04-16 22:20:36 +00:00
|
|
|
x86_cpu_to_apicid[cpu] = apicid;
|
|
|
|
|
|
|
|
cpu_pda[cpu].pcurrent = idle;
|
|
|
|
|
|
|
|
start_rip = setup_trampoline();
|
|
|
|
|
2005-04-16 22:25:19 +00:00
|
|
|
init_rsp = idle->thread.rsp;
|
2005-04-16 22:20:36 +00:00
|
|
|
per_cpu(init_tss,cpu).rsp0 = init_rsp;
|
|
|
|
initial_code = start_secondary;
|
|
|
|
clear_ti_thread_flag(idle->thread_info, TIF_FORK);
|
|
|
|
|
2005-04-16 22:25:19 +00:00
|
|
|
printk(KERN_INFO "Booting processor %d/%d rip %lx rsp %lx\n", cpu, apicid,
|
2005-04-16 22:20:36 +00:00
|
|
|
start_rip, init_rsp);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This grunge runs the startup process for
|
|
|
|
* the targeted processor.
|
|
|
|
*/
|
|
|
|
|
|
|
|
atomic_set(&init_deasserted, 0);
|
|
|
|
|
|
|
|
Dprintk("Setting warm reset code and vector.\n");
|
|
|
|
|
|
|
|
CMOS_WRITE(0xa, 0xf);
|
|
|
|
local_flush_tlb();
|
|
|
|
Dprintk("1.\n");
|
|
|
|
*((volatile unsigned short *) phys_to_virt(0x469)) = start_rip >> 4;
|
|
|
|
Dprintk("2.\n");
|
|
|
|
*((volatile unsigned short *) phys_to_virt(0x467)) = start_rip & 0xf;
|
|
|
|
Dprintk("3.\n");
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Be paranoid about clearing APIC errors.
|
|
|
|
*/
|
|
|
|
if (APIC_INTEGRATED(apic_version[apicid])) {
|
|
|
|
apic_read_around(APIC_SPIV);
|
|
|
|
apic_write(APIC_ESR, 0);
|
|
|
|
apic_read(APIC_ESR);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Status is now clean
|
|
|
|
*/
|
|
|
|
boot_error = 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Starting actual IPI sequence...
|
|
|
|
*/
|
2005-04-16 22:25:19 +00:00
|
|
|
boot_error = wakeup_secondary_via_INIT(apicid, start_rip);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
if (!boot_error) {
|
|
|
|
/*
|
|
|
|
* allow APs to start initializing.
|
|
|
|
*/
|
|
|
|
Dprintk("Before Callout %d.\n", cpu);
|
|
|
|
cpu_set(cpu, cpu_callout_map);
|
|
|
|
Dprintk("After Callout %d.\n", cpu);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Wait 5s total for a response
|
|
|
|
*/
|
|
|
|
for (timeout = 0; timeout < 50000; timeout++) {
|
|
|
|
if (cpu_isset(cpu, cpu_callin_map))
|
|
|
|
break; /* It has booted */
|
|
|
|
udelay(100);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cpu_isset(cpu, cpu_callin_map)) {
|
|
|
|
/* number CPUs logically, starting from 1 (BSP is 0) */
|
|
|
|
Dprintk("OK.\n");
|
|
|
|
print_cpu_info(&cpu_data[cpu]);
|
|
|
|
Dprintk("CPU has booted.\n");
|
|
|
|
} else {
|
|
|
|
boot_error = 1;
|
|
|
|
if (*((volatile unsigned char *)phys_to_virt(SMP_TRAMPOLINE_BASE))
|
|
|
|
== 0xA5)
|
|
|
|
/* trampoline started but...? */
|
|
|
|
printk("Stuck ??\n");
|
|
|
|
else
|
|
|
|
/* trampoline code not run */
|
|
|
|
printk("Not responding.\n");
|
|
|
|
#if APIC_DEBUG
|
|
|
|
inquire_remote_apic(apicid);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (boot_error) {
|
|
|
|
cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
|
|
|
|
clear_bit(cpu, &cpu_initialized); /* was set by cpu_init() */
|
2005-04-16 22:25:19 +00:00
|
|
|
cpu_clear(cpu, cpu_present_map);
|
|
|
|
cpu_clear(cpu, cpu_possible_map);
|
2005-04-16 22:20:36 +00:00
|
|
|
x86_cpu_to_apicid[cpu] = BAD_APICID;
|
|
|
|
x86_cpu_to_log_apicid[cpu] = BAD_APICID;
|
2005-04-16 22:25:19 +00:00
|
|
|
return -EIO;
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
2005-04-16 22:25:19 +00:00
|
|
|
|
|
|
|
return 0;
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
2005-04-16 22:25:19 +00:00
|
|
|
cycles_t cacheflush_time;
|
|
|
|
unsigned long cache_decay_ticks;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Construct cpu_sibling_map[], so that we can tell the sibling CPU
|
|
|
|
* on SMT systems efficiently.
|
|
|
|
*/
|
|
|
|
static __cpuinit void detect_siblings(void)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
2005-04-16 22:25:19 +00:00
|
|
|
int cpu;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2005-04-16 22:25:19 +00:00
|
|
|
for (cpu = 0; cpu < NR_CPUS; cpu++) {
|
|
|
|
cpus_clear(cpu_sibling_map[cpu]);
|
|
|
|
cpus_clear(cpu_core_map[cpu]);
|
|
|
|
}
|
|
|
|
|
|
|
|
for_each_online_cpu (cpu) {
|
|
|
|
struct cpuinfo_x86 *c = cpu_data + cpu;
|
|
|
|
int siblings = 0;
|
|
|
|
int i;
|
|
|
|
if (smp_num_siblings > 1) {
|
|
|
|
for_each_online_cpu (i) {
|
2005-04-16 22:25:20 +00:00
|
|
|
if (cpu_core_id[cpu] == cpu_core_id[i]) {
|
2005-04-16 22:25:19 +00:00
|
|
|
siblings++;
|
|
|
|
cpu_set(i, cpu_sibling_map[cpu]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
siblings++;
|
|
|
|
cpu_set(cpu, cpu_sibling_map[cpu]);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (siblings != smp_num_siblings) {
|
|
|
|
printk(KERN_WARNING
|
|
|
|
"WARNING: %d siblings found for CPU%d, should be %d\n",
|
|
|
|
siblings, cpu, smp_num_siblings);
|
|
|
|
smp_num_siblings = siblings;
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
2005-04-16 22:25:19 +00:00
|
|
|
if (c->x86_num_cores > 1) {
|
|
|
|
for_each_online_cpu(i) {
|
|
|
|
if (phys_proc_id[cpu] == phys_proc_id[i])
|
|
|
|
cpu_set(i, cpu_core_map[cpu]);
|
|
|
|
}
|
|
|
|
} else
|
|
|
|
cpu_core_map[cpu] = cpu_sibling_map[cpu];
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2005-04-16 22:25:19 +00:00
|
|
|
* Cleanup possible dangling ends...
|
2005-04-16 22:20:36 +00:00
|
|
|
*/
|
2005-04-16 22:25:19 +00:00
|
|
|
static __cpuinit void smp_cleanup_boot(void)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
2005-04-16 22:25:19 +00:00
|
|
|
/*
|
|
|
|
* Paranoid: Set warm reset code and vector here back
|
|
|
|
* to default values.
|
|
|
|
*/
|
|
|
|
CMOS_WRITE(0, 0xf);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2005-04-16 22:25:19 +00:00
|
|
|
/*
|
|
|
|
* Reset trampoline flag
|
|
|
|
*/
|
|
|
|
*((volatile int *) phys_to_virt(0x467)) = 0;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2005-04-16 22:25:19 +00:00
|
|
|
#ifndef CONFIG_HOTPLUG_CPU
|
2005-04-16 22:20:36 +00:00
|
|
|
/*
|
2005-04-16 22:25:19 +00:00
|
|
|
* Free pages reserved for SMP bootup.
|
|
|
|
* When you add hotplug CPU support later remove this
|
|
|
|
* Note there is more work to be done for later CPU bootup.
|
2005-04-16 22:20:36 +00:00
|
|
|
*/
|
|
|
|
|
2005-04-16 22:25:19 +00:00
|
|
|
free_page((unsigned long) __va(PAGE_SIZE));
|
|
|
|
free_page((unsigned long) __va(SMP_TRAMPOLINE_BASE));
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Fall back to non SMP mode after errors.
|
|
|
|
*
|
|
|
|
* RED-PEN audit/test this more. I bet there is more state messed up here.
|
|
|
|
*/
|
|
|
|
static __cpuinit void disable_smp(void)
|
|
|
|
{
|
|
|
|
cpu_present_map = cpumask_of_cpu(0);
|
|
|
|
cpu_possible_map = cpumask_of_cpu(0);
|
|
|
|
if (smp_found_config)
|
|
|
|
phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id);
|
|
|
|
else
|
|
|
|
phys_cpu_present_map = physid_mask_of_physid(0);
|
|
|
|
cpu_set(0, cpu_sibling_map[0]);
|
|
|
|
cpu_set(0, cpu_core_map[0]);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Handle user cpus=... parameter.
|
|
|
|
*/
|
|
|
|
static __cpuinit void enforce_max_cpus(unsigned max_cpus)
|
|
|
|
{
|
|
|
|
int i, k;
|
|
|
|
k = 0;
|
|
|
|
for (i = 0; i < NR_CPUS; i++) {
|
|
|
|
if (!cpu_possible(i))
|
|
|
|
continue;
|
|
|
|
if (++k > max_cpus) {
|
|
|
|
cpu_clear(i, cpu_possible_map);
|
|
|
|
cpu_clear(i, cpu_present_map);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2005-04-16 22:25:19 +00:00
|
|
|
/*
|
|
|
|
* Various sanity checks.
|
|
|
|
*/
|
|
|
|
static int __cpuinit smp_sanity_check(unsigned max_cpus)
|
|
|
|
{
|
2005-04-16 22:20:36 +00:00
|
|
|
if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
|
|
|
|
printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
|
|
|
|
hard_smp_processor_id());
|
|
|
|
physid_set(hard_smp_processor_id(), phys_cpu_present_map);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If we couldn't find an SMP configuration at boot time,
|
|
|
|
* get out of here now!
|
|
|
|
*/
|
|
|
|
if (!smp_found_config) {
|
|
|
|
printk(KERN_NOTICE "SMP motherboard not detected.\n");
|
2005-04-16 22:25:19 +00:00
|
|
|
disable_smp();
|
2005-04-16 22:20:36 +00:00
|
|
|
if (APIC_init_uniprocessor())
|
|
|
|
printk(KERN_NOTICE "Local APIC not detected."
|
|
|
|
" Using dummy APIC emulation.\n");
|
2005-04-16 22:25:19 +00:00
|
|
|
return -1;
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Should not be necessary because the MP table should list the boot
|
|
|
|
* CPU too, but we do it for the sake of robustness anyway.
|
|
|
|
*/
|
|
|
|
if (!physid_isset(boot_cpu_id, phys_cpu_present_map)) {
|
|
|
|
printk(KERN_NOTICE "weird, boot CPU (#%d) not listed by the BIOS.\n",
|
|
|
|
boot_cpu_id);
|
|
|
|
physid_set(hard_smp_processor_id(), phys_cpu_present_map);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If we couldn't find a local APIC, then get out of here now!
|
|
|
|
*/
|
|
|
|
if (APIC_INTEGRATED(apic_version[boot_cpu_id]) && !cpu_has_apic) {
|
|
|
|
printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
|
|
|
|
boot_cpu_id);
|
|
|
|
printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
|
2005-04-16 22:25:19 +00:00
|
|
|
nr_ioapics = 0;
|
|
|
|
return -1;
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If SMP should be disabled, then really disable it!
|
|
|
|
*/
|
|
|
|
if (!max_cpus) {
|
|
|
|
printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n");
|
2005-04-16 22:25:19 +00:00
|
|
|
nr_ioapics = 0;
|
|
|
|
return -1;
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
2005-04-16 22:25:19 +00:00
|
|
|
return 0;
|
|
|
|
}
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2005-04-16 22:25:19 +00:00
|
|
|
/*
|
|
|
|
* Prepare for SMP bootup. The MP table or ACPI has been read
|
|
|
|
* earlier. Just do some sanity checking here and enable APIC mode.
|
|
|
|
*/
|
|
|
|
void __cpuinit smp_prepare_cpus(unsigned int max_cpus)
|
|
|
|
{
|
|
|
|
int i;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2005-04-16 22:25:19 +00:00
|
|
|
nmi_watchdog_default();
|
|
|
|
current_cpu_data = boot_cpu_data;
|
|
|
|
current_thread_info()->cpu = 0; /* needed? */
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2005-04-16 22:25:19 +00:00
|
|
|
enforce_max_cpus(max_cpus);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
/*
|
2005-04-16 22:25:19 +00:00
|
|
|
* Fill in cpu_present_mask
|
2005-04-16 22:20:36 +00:00
|
|
|
*/
|
2005-04-16 22:25:19 +00:00
|
|
|
for (i = 0; i < NR_CPUS; i++) {
|
|
|
|
int apicid = cpu_present_to_apicid(i);
|
|
|
|
if (physid_isset(apicid, phys_cpu_present_map)) {
|
|
|
|
cpu_set(i, cpu_present_map);
|
|
|
|
/* possible map would be different if we supported real
|
|
|
|
CPU hotplug. */
|
|
|
|
cpu_set(i, cpu_possible_map);
|
|
|
|
}
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
2005-04-16 22:25:19 +00:00
|
|
|
if (smp_sanity_check(max_cpus) < 0) {
|
|
|
|
printk(KERN_INFO "SMP disabled\n");
|
|
|
|
disable_smp();
|
|
|
|
return;
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
2005-04-16 22:25:19 +00:00
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
/*
|
2005-04-16 22:25:19 +00:00
|
|
|
* Switch from PIC to APIC mode.
|
2005-04-16 22:20:36 +00:00
|
|
|
*/
|
2005-04-16 22:25:19 +00:00
|
|
|
connect_bsp_APIC();
|
|
|
|
setup_local_APIC();
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2005-04-16 22:25:19 +00:00
|
|
|
if (GET_APIC_ID(apic_read(APIC_ID)) != boot_cpu_id) {
|
|
|
|
panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
|
|
|
|
GET_APIC_ID(apic_read(APIC_ID)), boot_cpu_id);
|
|
|
|
/* Or can we switch back to PIC here? */
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
2005-04-16 22:25:19 +00:00
|
|
|
x86_cpu_to_apicid[0] = boot_cpu_id;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
/*
|
2005-04-16 22:25:19 +00:00
|
|
|
* Now start the IO-APICs
|
2005-04-16 22:20:36 +00:00
|
|
|
*/
|
|
|
|
if (!skip_ioapic_setup && nr_ioapics)
|
|
|
|
setup_IO_APIC();
|
|
|
|
else
|
|
|
|
nr_ioapics = 0;
|
|
|
|
|
|
|
|
/*
|
2005-04-16 22:25:19 +00:00
|
|
|
* Set up local APIC timer on boot CPU.
|
2005-04-16 22:20:36 +00:00
|
|
|
*/
|
|
|
|
|
2005-04-16 22:25:19 +00:00
|
|
|
setup_boot_APIC_clock();
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
2005-04-16 22:25:19 +00:00
|
|
|
/*
|
|
|
|
* Early setup to make printk work.
|
|
|
|
*/
|
|
|
|
void __init smp_prepare_boot_cpu(void)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
2005-04-16 22:25:19 +00:00
|
|
|
int me = smp_processor_id();
|
|
|
|
cpu_set(me, cpu_online_map);
|
|
|
|
cpu_set(me, cpu_callout_map);
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
2005-04-16 22:25:19 +00:00
|
|
|
/*
|
|
|
|
* Entry point to boot a CPU.
|
|
|
|
*
|
|
|
|
* This is all __cpuinit, not __devinit for now because we don't support
|
|
|
|
* CPU hotplug (yet).
|
|
|
|
*/
|
|
|
|
int __cpuinit __cpu_up(unsigned int cpu)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
2005-04-16 22:25:19 +00:00
|
|
|
int err;
|
|
|
|
int apicid = cpu_present_to_apicid(cpu);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2005-04-16 22:25:19 +00:00
|
|
|
WARN_ON(irqs_disabled());
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2005-04-16 22:25:19 +00:00
|
|
|
Dprintk("++++++++++++++++++++=_---CPU UP %u\n", cpu);
|
|
|
|
|
|
|
|
if (apicid == BAD_APICID || apicid == boot_cpu_id ||
|
|
|
|
!physid_isset(apicid, phys_cpu_present_map)) {
|
|
|
|
printk("__cpu_up: bad cpu %d\n", cpu);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
sync_tsc_bp_init(1);
|
|
|
|
|
|
|
|
/* Boot it! */
|
|
|
|
err = do_boot_cpu(cpu, apicid);
|
|
|
|
if (err < 0) {
|
|
|
|
sync_tsc_bp_init(0);
|
|
|
|
Dprintk("do_boot_cpu failed %d\n", err);
|
|
|
|
return err;
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
2005-04-16 22:25:19 +00:00
|
|
|
|
|
|
|
sync_tsc_bp(cpu);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
/* Unleash the CPU! */
|
|
|
|
Dprintk("waiting for cpu %d\n", cpu);
|
|
|
|
|
|
|
|
while (!cpu_isset(cpu, cpu_online_map))
|
2005-04-16 22:25:19 +00:00
|
|
|
cpu_relax();
|
2005-04-16 22:20:36 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2005-04-16 22:25:19 +00:00
|
|
|
/*
|
|
|
|
* Finish the SMP boot.
|
|
|
|
*/
|
|
|
|
void __cpuinit smp_cpus_done(unsigned int max_cpus)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
2005-04-16 22:25:19 +00:00
|
|
|
zap_low_mappings();
|
|
|
|
smp_cleanup_boot();
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
#ifdef CONFIG_X86_IO_APIC
|
|
|
|
setup_ioapic_dest();
|
|
|
|
#endif
|
|
|
|
|
2005-04-16 22:25:19 +00:00
|
|
|
detect_siblings();
|
|
|
|
time_init_gtod();
|
|
|
|
}
|