2009-04-28 02:52:28 +00:00
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/*
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* xHCI host controller driver
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*
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* Copyright (C) 2008 Intel Corp.
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*
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* Author: Sarah Sharp
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* Some code borrowed from the Linux EHCI driver.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/usb.h>
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2009-04-28 02:52:34 +00:00
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#include <linux/pci.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 08:04:11 +00:00
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#include <linux/slab.h>
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2009-04-30 02:06:56 +00:00
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#include <linux/dmapool.h>
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2009-04-28 02:52:28 +00:00
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#include "xhci.h"
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2009-04-28 02:52:34 +00:00
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/*
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* Allocates a generic ring segment from the ring pool, sets the dma address,
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* initializes the segment to zero, and sets the private next pointer to NULL.
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*
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* Section 4.11.1.1:
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* "All components of all Command and Transfer TRBs shall be initialized to '0'"
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*/
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static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, gfp_t flags)
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{
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struct xhci_segment *seg;
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dma_addr_t dma;
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seg = kzalloc(sizeof *seg, flags);
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if (!seg)
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return 0;
|
2009-04-30 02:14:08 +00:00
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xhci_dbg(xhci, "Allocating priv segment structure at %p\n", seg);
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2009-04-28 02:52:34 +00:00
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seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma);
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if (!seg->trbs) {
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kfree(seg);
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return 0;
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}
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2009-04-30 02:14:08 +00:00
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xhci_dbg(xhci, "// Allocating segment at %p (virtual) 0x%llx (DMA)\n",
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seg->trbs, (unsigned long long)dma);
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2009-04-28 02:52:34 +00:00
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memset(seg->trbs, 0, SEGMENT_SIZE);
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seg->dma = dma;
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seg->next = NULL;
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return seg;
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}
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static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
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{
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if (!seg)
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return;
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if (seg->trbs) {
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2009-04-30 02:14:08 +00:00
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xhci_dbg(xhci, "Freeing DMA segment at %p (virtual) 0x%llx (DMA)\n",
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seg->trbs, (unsigned long long)seg->dma);
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2009-04-28 02:52:34 +00:00
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dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
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seg->trbs = NULL;
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}
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2009-04-30 02:14:08 +00:00
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xhci_dbg(xhci, "Freeing priv segment structure at %p\n", seg);
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2009-04-28 02:52:34 +00:00
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kfree(seg);
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}
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/*
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* Make the prev segment point to the next segment.
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*
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* Change the last TRB in the prev segment to be a Link TRB which points to the
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* DMA address of the next segment. The caller needs to set any Link TRB
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* related flags, such as End TRB, Toggle Cycle, and no snoop.
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*/
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static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
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struct xhci_segment *next, bool link_trbs)
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{
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u32 val;
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if (!prev || !next)
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return;
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prev->next = next;
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if (link_trbs) {
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2009-07-27 19:03:31 +00:00
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prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr = next->dma;
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2009-04-28 02:52:34 +00:00
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/* Set the last TRB in the segment to have a TRB type ID of Link TRB */
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val = prev->trbs[TRBS_PER_SEGMENT-1].link.control;
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val &= ~TRB_TYPE_BITMASK;
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val |= TRB_TYPE(TRB_LINK);
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2009-08-07 21:04:36 +00:00
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/* Always set the chain bit with 0.95 hardware */
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if (xhci_link_trb_quirk(xhci))
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val |= TRB_CHAIN;
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2009-04-28 02:52:34 +00:00
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prev->trbs[TRBS_PER_SEGMENT-1].link.control = val;
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}
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2009-04-30 02:14:08 +00:00
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xhci_dbg(xhci, "Linking segment 0x%llx to segment 0x%llx (DMA)\n",
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(unsigned long long)prev->dma,
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(unsigned long long)next->dma);
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2009-04-28 02:52:34 +00:00
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}
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/* XXX: Do we need the hcd structure in all these functions? */
|
USB: xhci: Bandwidth allocation support
Since the xHCI host controller hardware (xHC) has an internal schedule, it
needs a better representation of what devices are consuming bandwidth on
the bus. Each device is represented by a device context, with data about
the device, endpoints, and pointers to each endpoint ring.
We need to update the endpoint information for a device context before a
new configuration or alternate interface setting is selected. We setup an
input device context with modified endpoint information and newly
allocated endpoint rings, and then submit a Configure Endpoint Command to
the hardware.
The host controller can reject the new configuration if it exceeds the bus
bandwidth, or the host controller doesn't have enough internal resources
for the configuration. If the command fails, we still have the older
device context with the previous configuration. If the command succeeds,
we free the old endpoint rings.
The root hub isn't a real device, so always say yes to any bandwidth
changes for it.
The USB core will enable, disable, and then enable endpoint 0 several
times during the initialization sequence. The device will always have an
endpoint ring for endpoint 0 and bandwidth allocated for that, unless the
device is disconnected or gets a SetAddress 0 request. So we don't pay
attention for when xhci_check_bandwidth() is called for a re-add of
endpoint 0.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2009-04-28 02:58:38 +00:00
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void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
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2009-04-28 02:52:34 +00:00
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{
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struct xhci_segment *seg;
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struct xhci_segment *first_seg;
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if (!ring || !ring->first_seg)
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return;
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first_seg = ring->first_seg;
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seg = first_seg->next;
|
2009-04-30 02:14:08 +00:00
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xhci_dbg(xhci, "Freeing ring at %p\n", ring);
|
2009-04-28 02:52:34 +00:00
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while (seg != first_seg) {
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struct xhci_segment *next = seg->next;
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xhci_segment_free(xhci, seg);
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seg = next;
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}
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xhci_segment_free(xhci, first_seg);
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ring->first_seg = NULL;
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kfree(ring);
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|
|
}
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|
2009-12-03 17:44:29 +00:00
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static void xhci_initialize_ring_info(struct xhci_ring *ring)
|
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|
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{
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|
|
|
/* The ring is empty, so the enqueue pointer == dequeue pointer */
|
|
|
|
ring->enqueue = ring->first_seg->trbs;
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|
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ring->enq_seg = ring->first_seg;
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ring->dequeue = ring->enqueue;
|
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|
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ring->deq_seg = ring->first_seg;
|
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|
|
/* The ring is initialized to 0. The producer must write 1 to the cycle
|
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|
|
* bit to handover ownership of the TRB, so PCS = 1. The consumer must
|
|
|
|
* compare CCS to the cycle bit to check ownership, so CCS = 1.
|
|
|
|
*/
|
|
|
|
ring->cycle_state = 1;
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|
|
|
/* Not necessary for new rings, but needed for re-initialized rings */
|
|
|
|
ring->enq_updates = 0;
|
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|
|
ring->deq_updates = 0;
|
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|
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}
|
|
|
|
|
2009-04-28 02:52:34 +00:00
|
|
|
/**
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|
|
* Create a new ring with zero or more segments.
|
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|
|
*
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|
|
|
* Link each segment together into a ring.
|
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|
|
* Set the end flag and the cycle toggle bit on the last segment.
|
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|
|
* See section 4.9.1 and figures 15 and 16.
|
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|
|
*/
|
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|
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static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
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|
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unsigned int num_segs, bool link_trbs, gfp_t flags)
|
|
|
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{
|
|
|
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struct xhci_ring *ring;
|
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|
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struct xhci_segment *prev;
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|
|
|
|
|
|
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ring = kzalloc(sizeof *(ring), flags);
|
2009-04-30 02:14:08 +00:00
|
|
|
xhci_dbg(xhci, "Allocating ring at %p\n", ring);
|
2009-04-28 02:52:34 +00:00
|
|
|
if (!ring)
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|
|
|
return 0;
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|
|
|
|
2009-04-28 02:58:01 +00:00
|
|
|
INIT_LIST_HEAD(&ring->td_list);
|
2009-04-28 02:52:34 +00:00
|
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if (num_segs == 0)
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return ring;
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|
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|
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ring->first_seg = xhci_segment_alloc(xhci, flags);
|
|
|
|
if (!ring->first_seg)
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|
|
|
goto fail;
|
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|
|
num_segs--;
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|
|
|
|
|
|
prev = ring->first_seg;
|
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|
|
while (num_segs > 0) {
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|
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struct xhci_segment *next;
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|
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next = xhci_segment_alloc(xhci, flags);
|
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|
|
if (!next)
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|
|
goto fail;
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xhci_link_segments(xhci, prev, next, link_trbs);
|
|
|
|
|
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|
prev = next;
|
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|
|
num_segs--;
|
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|
}
|
|
|
|
xhci_link_segments(xhci, prev, ring->first_seg, link_trbs);
|
|
|
|
|
|
|
|
if (link_trbs) {
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|
|
|
/* See section 4.9.2.1 and 6.4.4.1 */
|
|
|
|
prev->trbs[TRBS_PER_SEGMENT-1].link.control |= (LINK_TOGGLE);
|
|
|
|
xhci_dbg(xhci, "Wrote link toggle flag to"
|
2009-04-30 02:14:08 +00:00
|
|
|
" segment %p (virtual), 0x%llx (DMA)\n",
|
|
|
|
prev, (unsigned long long)prev->dma);
|
2009-04-28 02:52:34 +00:00
|
|
|
}
|
2009-12-03 17:44:29 +00:00
|
|
|
xhci_initialize_ring_info(ring);
|
2009-04-28 02:52:34 +00:00
|
|
|
return ring;
|
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|
|
|
|
|
|
fail:
|
|
|
|
xhci_ring_free(xhci, ring);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-12-09 23:59:01 +00:00
|
|
|
void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
|
|
|
|
struct xhci_virt_device *virt_dev,
|
|
|
|
unsigned int ep_index)
|
|
|
|
{
|
|
|
|
int rings_cached;
|
|
|
|
|
|
|
|
rings_cached = virt_dev->num_rings_cached;
|
|
|
|
if (rings_cached < XHCI_MAX_RINGS_CACHED) {
|
|
|
|
virt_dev->num_rings_cached++;
|
|
|
|
rings_cached = virt_dev->num_rings_cached;
|
|
|
|
virt_dev->ring_cache[rings_cached] =
|
|
|
|
virt_dev->eps[ep_index].ring;
|
|
|
|
xhci_dbg(xhci, "Cached old ring, "
|
|
|
|
"%d ring%s cached\n",
|
|
|
|
rings_cached,
|
|
|
|
(rings_cached > 1) ? "s" : "");
|
|
|
|
} else {
|
|
|
|
xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
|
|
|
|
xhci_dbg(xhci, "Ring cache full (%d rings), "
|
|
|
|
"freeing ring\n",
|
|
|
|
virt_dev->num_rings_cached);
|
|
|
|
}
|
|
|
|
virt_dev->eps[ep_index].ring = NULL;
|
|
|
|
}
|
|
|
|
|
2009-12-03 17:44:29 +00:00
|
|
|
/* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue
|
|
|
|
* pointers to the beginning of the ring.
|
|
|
|
*/
|
|
|
|
static void xhci_reinit_cached_ring(struct xhci_hcd *xhci,
|
|
|
|
struct xhci_ring *ring)
|
|
|
|
{
|
|
|
|
struct xhci_segment *seg = ring->first_seg;
|
|
|
|
do {
|
|
|
|
memset(seg->trbs, 0,
|
|
|
|
sizeof(union xhci_trb)*TRBS_PER_SEGMENT);
|
|
|
|
/* All endpoint rings have link TRBs */
|
|
|
|
xhci_link_segments(xhci, seg, seg->next, 1);
|
|
|
|
seg = seg->next;
|
|
|
|
} while (seg != ring->first_seg);
|
|
|
|
xhci_initialize_ring_info(ring);
|
|
|
|
/* td list should be empty since all URBs have been cancelled,
|
|
|
|
* but just in case...
|
|
|
|
*/
|
|
|
|
INIT_LIST_HEAD(&ring->td_list);
|
|
|
|
}
|
|
|
|
|
2009-07-27 19:05:15 +00:00
|
|
|
#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
|
|
|
|
|
|
|
|
struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
|
|
|
|
int type, gfp_t flags)
|
|
|
|
{
|
|
|
|
struct xhci_container_ctx *ctx = kzalloc(sizeof(*ctx), flags);
|
|
|
|
if (!ctx)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
|
|
|
|
ctx->type = type;
|
|
|
|
ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
|
|
|
|
if (type == XHCI_CTX_TYPE_INPUT)
|
|
|
|
ctx->size += CTX_SIZE(xhci->hcc_params);
|
|
|
|
|
|
|
|
ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma);
|
|
|
|
memset(ctx->bytes, 0, ctx->size);
|
|
|
|
return ctx;
|
|
|
|
}
|
|
|
|
|
|
|
|
void xhci_free_container_ctx(struct xhci_hcd *xhci,
|
|
|
|
struct xhci_container_ctx *ctx)
|
|
|
|
{
|
2009-12-09 23:59:03 +00:00
|
|
|
if (!ctx)
|
|
|
|
return;
|
2009-07-27 19:05:15 +00:00
|
|
|
dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
|
|
|
|
kfree(ctx);
|
|
|
|
}
|
|
|
|
|
|
|
|
struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci,
|
|
|
|
struct xhci_container_ctx *ctx)
|
|
|
|
{
|
|
|
|
BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT);
|
|
|
|
return (struct xhci_input_control_ctx *)ctx->bytes;
|
|
|
|
}
|
|
|
|
|
|
|
|
struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
|
|
|
|
struct xhci_container_ctx *ctx)
|
|
|
|
{
|
|
|
|
if (ctx->type == XHCI_CTX_TYPE_DEVICE)
|
|
|
|
return (struct xhci_slot_ctx *)ctx->bytes;
|
|
|
|
|
|
|
|
return (struct xhci_slot_ctx *)
|
|
|
|
(ctx->bytes + CTX_SIZE(xhci->hcc_params));
|
|
|
|
}
|
|
|
|
|
|
|
|
struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
|
|
|
|
struct xhci_container_ctx *ctx,
|
|
|
|
unsigned int ep_index)
|
|
|
|
{
|
|
|
|
/* increment ep index by offset of start of ep ctx array */
|
|
|
|
ep_index++;
|
|
|
|
if (ctx->type == XHCI_CTX_TYPE_INPUT)
|
|
|
|
ep_index++;
|
|
|
|
|
|
|
|
return (struct xhci_ep_ctx *)
|
|
|
|
(ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
|
|
|
|
}
|
|
|
|
|
USB: xhci: Add watchdog timer for URB cancellation.
In order to giveback a canceled URB, we must ensure that the xHCI
hardware will not access the buffer in an URB. We can't modify the
buffer pointers on endpoint rings without issuing and waiting for a stop
endpoint command. Since URBs can be canceled in interrupt context, we
can't wait on that command. The old code trusted that the host
controller would respond to the command, and would giveback the URBs in
the event handler. If the hardware never responds to the stop endpoint
command, the URBs will never be completed, and we might hang the USB
subsystem.
Implement a watchdog timer that is spawned whenever a stop endpoint
command is queued. If a stop endpoint command event is found on the
event ring during an interrupt, we need to stop the watchdog timer with
del_timer(). Since del_timer() can fail if the timer is running and
waiting on the xHCI lock, we need a way to signal to the timer that
everything is fine and it should exit. If we simply clear
EP_HALT_PENDING, a new stop endpoint command could sneak in and set it
before the watchdog timer can grab the lock.
Instead we use a combination of the EP_HALT_PENDING flag and a counter
for the number of pending stop endpoint commands
(xhci_virt_ep->stop_cmds_pending). If we need to cancel the watchdog
timer and del_timer() succeeds, we decrement the number of pending stop
endpoint commands. If del_timer() fails, we leave the number of pending
stop endpoint commands alone. In either case, we clear the
EP_HALT_PENDING flag.
The timer will decrement the number of pending stop endpoint commands
once it obtains the lock. If the timer is the tail end of the last stop
endpoint command (xhci_virt_ep->stop_cmds_pending == 0), and the
endpoint's command is still pending (EP_HALT_PENDING is set), we assume
the host is dying. The watchdog timer will set XHCI_STATE_DYING, try to
halt the xHCI host, and give back all pending URBs.
Various other places in the driver need to check whether the xHCI host
is dying. If the interrupt handler ever notices, it should immediately
stop processing events. The URB enqueue function should also return
-ESHUTDOWN. The URB dequeue function should simply return the value
of usb_hcd_check_unlink_urb() and the watchdog timer will take care of
giving the URB back. When a device is disconnected, the xHCI hardware
structures should be freed without issuing a disable slot command (since
the hardware probably won't respond to it anyway). The debugging
polling loop should stop polling if the host is dying.
When a device is disconnected, any pending watchdog timers are killed
with del_timer_sync(). It must be synchronous so that the watchdog
timer doesn't attempt to access the freed endpoint structures.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2009-10-27 17:57:01 +00:00
|
|
|
static void xhci_init_endpoint_timer(struct xhci_hcd *xhci,
|
|
|
|
struct xhci_virt_ep *ep)
|
|
|
|
{
|
|
|
|
init_timer(&ep->stop_cmd_timer);
|
|
|
|
ep->stop_cmd_timer.data = (unsigned long) ep;
|
|
|
|
ep->stop_cmd_timer.function = xhci_stop_endpoint_command_watchdog;
|
|
|
|
ep->xhci = xhci;
|
|
|
|
}
|
|
|
|
|
2009-04-28 02:58:01 +00:00
|
|
|
/* All the xhci_tds in the ring's TD list should be freed at this point */
|
2009-04-28 02:57:38 +00:00
|
|
|
void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
|
|
|
|
{
|
|
|
|
struct xhci_virt_device *dev;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Slot ID 0 is reserved */
|
|
|
|
if (slot_id == 0 || !xhci->devs[slot_id])
|
|
|
|
return;
|
|
|
|
|
|
|
|
dev = xhci->devs[slot_id];
|
2009-07-27 19:03:31 +00:00
|
|
|
xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
|
2009-04-28 02:57:38 +00:00
|
|
|
if (!dev)
|
|
|
|
return;
|
|
|
|
|
|
|
|
for (i = 0; i < 31; ++i)
|
2009-09-04 17:53:09 +00:00
|
|
|
if (dev->eps[i].ring)
|
|
|
|
xhci_ring_free(xhci, dev->eps[i].ring);
|
2009-04-28 02:57:38 +00:00
|
|
|
|
2009-12-03 17:44:29 +00:00
|
|
|
if (dev->ring_cache) {
|
|
|
|
for (i = 0; i < dev->num_rings_cached; i++)
|
|
|
|
xhci_ring_free(xhci, dev->ring_cache[i]);
|
|
|
|
kfree(dev->ring_cache);
|
|
|
|
}
|
|
|
|
|
2009-04-28 02:57:38 +00:00
|
|
|
if (dev->in_ctx)
|
2009-07-27 19:05:15 +00:00
|
|
|
xhci_free_container_ctx(xhci, dev->in_ctx);
|
2009-04-28 02:57:38 +00:00
|
|
|
if (dev->out_ctx)
|
2009-07-27 19:05:15 +00:00
|
|
|
xhci_free_container_ctx(xhci, dev->out_ctx);
|
|
|
|
|
2009-04-28 02:57:38 +00:00
|
|
|
kfree(xhci->devs[slot_id]);
|
|
|
|
xhci->devs[slot_id] = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
|
|
|
|
struct usb_device *udev, gfp_t flags)
|
|
|
|
{
|
|
|
|
struct xhci_virt_device *dev;
|
2009-09-04 17:53:09 +00:00
|
|
|
int i;
|
2009-04-28 02:57:38 +00:00
|
|
|
|
|
|
|
/* Slot ID 0 is reserved */
|
|
|
|
if (slot_id == 0 || xhci->devs[slot_id]) {
|
|
|
|
xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);
|
|
|
|
if (!xhci->devs[slot_id])
|
|
|
|
return 0;
|
|
|
|
dev = xhci->devs[slot_id];
|
|
|
|
|
2009-07-27 19:05:15 +00:00
|
|
|
/* Allocate the (output) device context that will be used in the HC. */
|
|
|
|
dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
|
2009-04-28 02:57:38 +00:00
|
|
|
if (!dev->out_ctx)
|
|
|
|
goto fail;
|
2009-07-27 19:05:15 +00:00
|
|
|
|
2009-04-30 02:14:08 +00:00
|
|
|
xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
|
2009-07-27 19:05:15 +00:00
|
|
|
(unsigned long long)dev->out_ctx->dma);
|
2009-04-28 02:57:38 +00:00
|
|
|
|
|
|
|
/* Allocate the (input) device context for address device command */
|
2009-07-27 19:05:15 +00:00
|
|
|
dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
|
2009-04-28 02:57:38 +00:00
|
|
|
if (!dev->in_ctx)
|
|
|
|
goto fail;
|
2009-07-27 19:05:15 +00:00
|
|
|
|
2009-04-30 02:14:08 +00:00
|
|
|
xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
|
2009-07-27 19:05:15 +00:00
|
|
|
(unsigned long long)dev->in_ctx->dma);
|
2009-04-28 02:57:38 +00:00
|
|
|
|
USB: xhci: Add watchdog timer for URB cancellation.
In order to giveback a canceled URB, we must ensure that the xHCI
hardware will not access the buffer in an URB. We can't modify the
buffer pointers on endpoint rings without issuing and waiting for a stop
endpoint command. Since URBs can be canceled in interrupt context, we
can't wait on that command. The old code trusted that the host
controller would respond to the command, and would giveback the URBs in
the event handler. If the hardware never responds to the stop endpoint
command, the URBs will never be completed, and we might hang the USB
subsystem.
Implement a watchdog timer that is spawned whenever a stop endpoint
command is queued. If a stop endpoint command event is found on the
event ring during an interrupt, we need to stop the watchdog timer with
del_timer(). Since del_timer() can fail if the timer is running and
waiting on the xHCI lock, we need a way to signal to the timer that
everything is fine and it should exit. If we simply clear
EP_HALT_PENDING, a new stop endpoint command could sneak in and set it
before the watchdog timer can grab the lock.
Instead we use a combination of the EP_HALT_PENDING flag and a counter
for the number of pending stop endpoint commands
(xhci_virt_ep->stop_cmds_pending). If we need to cancel the watchdog
timer and del_timer() succeeds, we decrement the number of pending stop
endpoint commands. If del_timer() fails, we leave the number of pending
stop endpoint commands alone. In either case, we clear the
EP_HALT_PENDING flag.
The timer will decrement the number of pending stop endpoint commands
once it obtains the lock. If the timer is the tail end of the last stop
endpoint command (xhci_virt_ep->stop_cmds_pending == 0), and the
endpoint's command is still pending (EP_HALT_PENDING is set), we assume
the host is dying. The watchdog timer will set XHCI_STATE_DYING, try to
halt the xHCI host, and give back all pending URBs.
Various other places in the driver need to check whether the xHCI host
is dying. If the interrupt handler ever notices, it should immediately
stop processing events. The URB enqueue function should also return
-ESHUTDOWN. The URB dequeue function should simply return the value
of usb_hcd_check_unlink_urb() and the watchdog timer will take care of
giving the URB back. When a device is disconnected, the xHCI hardware
structures should be freed without issuing a disable slot command (since
the hardware probably won't respond to it anyway). The debugging
polling loop should stop polling if the host is dying.
When a device is disconnected, any pending watchdog timers are killed
with del_timer_sync(). It must be synchronous so that the watchdog
timer doesn't attempt to access the freed endpoint structures.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2009-10-27 17:57:01 +00:00
|
|
|
/* Initialize the cancellation list and watchdog timers for each ep */
|
|
|
|
for (i = 0; i < 31; i++) {
|
|
|
|
xhci_init_endpoint_timer(xhci, &dev->eps[i]);
|
2009-09-04 17:53:09 +00:00
|
|
|
INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
|
USB: xhci: Add watchdog timer for URB cancellation.
In order to giveback a canceled URB, we must ensure that the xHCI
hardware will not access the buffer in an URB. We can't modify the
buffer pointers on endpoint rings without issuing and waiting for a stop
endpoint command. Since URBs can be canceled in interrupt context, we
can't wait on that command. The old code trusted that the host
controller would respond to the command, and would giveback the URBs in
the event handler. If the hardware never responds to the stop endpoint
command, the URBs will never be completed, and we might hang the USB
subsystem.
Implement a watchdog timer that is spawned whenever a stop endpoint
command is queued. If a stop endpoint command event is found on the
event ring during an interrupt, we need to stop the watchdog timer with
del_timer(). Since del_timer() can fail if the timer is running and
waiting on the xHCI lock, we need a way to signal to the timer that
everything is fine and it should exit. If we simply clear
EP_HALT_PENDING, a new stop endpoint command could sneak in and set it
before the watchdog timer can grab the lock.
Instead we use a combination of the EP_HALT_PENDING flag and a counter
for the number of pending stop endpoint commands
(xhci_virt_ep->stop_cmds_pending). If we need to cancel the watchdog
timer and del_timer() succeeds, we decrement the number of pending stop
endpoint commands. If del_timer() fails, we leave the number of pending
stop endpoint commands alone. In either case, we clear the
EP_HALT_PENDING flag.
The timer will decrement the number of pending stop endpoint commands
once it obtains the lock. If the timer is the tail end of the last stop
endpoint command (xhci_virt_ep->stop_cmds_pending == 0), and the
endpoint's command is still pending (EP_HALT_PENDING is set), we assume
the host is dying. The watchdog timer will set XHCI_STATE_DYING, try to
halt the xHCI host, and give back all pending URBs.
Various other places in the driver need to check whether the xHCI host
is dying. If the interrupt handler ever notices, it should immediately
stop processing events. The URB enqueue function should also return
-ESHUTDOWN. The URB dequeue function should simply return the value
of usb_hcd_check_unlink_urb() and the watchdog timer will take care of
giving the URB back. When a device is disconnected, the xHCI hardware
structures should be freed without issuing a disable slot command (since
the hardware probably won't respond to it anyway). The debugging
polling loop should stop polling if the host is dying.
When a device is disconnected, any pending watchdog timers are killed
with del_timer_sync(). It must be synchronous so that the watchdog
timer doesn't attempt to access the freed endpoint structures.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2009-10-27 17:57:01 +00:00
|
|
|
}
|
2009-09-04 17:53:09 +00:00
|
|
|
|
2009-04-28 02:57:38 +00:00
|
|
|
/* Allocate endpoint 0 ring */
|
2009-09-04 17:53:09 +00:00
|
|
|
dev->eps[0].ring = xhci_ring_alloc(xhci, 1, true, flags);
|
|
|
|
if (!dev->eps[0].ring)
|
2009-04-28 02:57:38 +00:00
|
|
|
goto fail;
|
|
|
|
|
2009-12-03 17:44:29 +00:00
|
|
|
/* Allocate pointers to the ring cache */
|
|
|
|
dev->ring_cache = kzalloc(
|
|
|
|
sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED,
|
|
|
|
flags);
|
|
|
|
if (!dev->ring_cache)
|
|
|
|
goto fail;
|
|
|
|
dev->num_rings_cached = 0;
|
|
|
|
|
USB: xhci: Bandwidth allocation support
Since the xHCI host controller hardware (xHC) has an internal schedule, it
needs a better representation of what devices are consuming bandwidth on
the bus. Each device is represented by a device context, with data about
the device, endpoints, and pointers to each endpoint ring.
We need to update the endpoint information for a device context before a
new configuration or alternate interface setting is selected. We setup an
input device context with modified endpoint information and newly
allocated endpoint rings, and then submit a Configure Endpoint Command to
the hardware.
The host controller can reject the new configuration if it exceeds the bus
bandwidth, or the host controller doesn't have enough internal resources
for the configuration. If the command fails, we still have the older
device context with the previous configuration. If the command succeeds,
we free the old endpoint rings.
The root hub isn't a real device, so always say yes to any bandwidth
changes for it.
The USB core will enable, disable, and then enable endpoint 0 several
times during the initialization sequence. The device will always have an
endpoint ring for endpoint 0 and bandwidth allocated for that, unless the
device is disconnected or gets a SetAddress 0 request. So we don't pay
attention for when xhci_check_bandwidth() is called for a re-add of
endpoint 0.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2009-04-28 02:58:38 +00:00
|
|
|
init_completion(&dev->cmd_completion);
|
2009-09-04 17:53:13 +00:00
|
|
|
INIT_LIST_HEAD(&dev->cmd_list);
|
USB: xhci: Bandwidth allocation support
Since the xHCI host controller hardware (xHC) has an internal schedule, it
needs a better representation of what devices are consuming bandwidth on
the bus. Each device is represented by a device context, with data about
the device, endpoints, and pointers to each endpoint ring.
We need to update the endpoint information for a device context before a
new configuration or alternate interface setting is selected. We setup an
input device context with modified endpoint information and newly
allocated endpoint rings, and then submit a Configure Endpoint Command to
the hardware.
The host controller can reject the new configuration if it exceeds the bus
bandwidth, or the host controller doesn't have enough internal resources
for the configuration. If the command fails, we still have the older
device context with the previous configuration. If the command succeeds,
we free the old endpoint rings.
The root hub isn't a real device, so always say yes to any bandwidth
changes for it.
The USB core will enable, disable, and then enable endpoint 0 several
times during the initialization sequence. The device will always have an
endpoint ring for endpoint 0 and bandwidth allocated for that, unless the
device is disconnected or gets a SetAddress 0 request. So we don't pay
attention for when xhci_check_bandwidth() is called for a re-add of
endpoint 0.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2009-04-28 02:58:38 +00:00
|
|
|
|
2009-07-27 19:05:08 +00:00
|
|
|
/* Point to output device context in dcbaa. */
|
2009-07-27 19:05:15 +00:00
|
|
|
xhci->dcbaa->dev_context_ptrs[slot_id] = dev->out_ctx->dma;
|
2009-04-30 02:14:08 +00:00
|
|
|
xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
|
2009-04-28 02:57:38 +00:00
|
|
|
slot_id,
|
2009-07-27 19:03:31 +00:00
|
|
|
&xhci->dcbaa->dev_context_ptrs[slot_id],
|
2009-07-27 19:05:08 +00:00
|
|
|
(unsigned long long) xhci->dcbaa->dev_context_ptrs[slot_id]);
|
2009-04-28 02:57:38 +00:00
|
|
|
|
|
|
|
return 1;
|
|
|
|
fail:
|
|
|
|
xhci_free_virt_device(xhci, slot_id);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Setup an xHCI virtual device for a Set Address command */
|
|
|
|
int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
|
|
|
|
{
|
|
|
|
struct xhci_virt_device *dev;
|
|
|
|
struct xhci_ep_ctx *ep0_ctx;
|
|
|
|
struct usb_device *top_dev;
|
2009-07-27 19:05:15 +00:00
|
|
|
struct xhci_slot_ctx *slot_ctx;
|
|
|
|
struct xhci_input_control_ctx *ctrl_ctx;
|
2009-04-28 02:57:38 +00:00
|
|
|
|
|
|
|
dev = xhci->devs[udev->slot_id];
|
|
|
|
/* Slot ID 0 is reserved */
|
|
|
|
if (udev->slot_id == 0 || !dev) {
|
|
|
|
xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
|
|
|
|
udev->slot_id);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2009-07-27 19:05:15 +00:00
|
|
|
ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
|
|
|
|
ctrl_ctx = xhci_get_input_control_ctx(xhci, dev->in_ctx);
|
|
|
|
slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
|
2009-04-28 02:57:38 +00:00
|
|
|
|
|
|
|
/* 2) New slot context and endpoint 0 context are valid*/
|
2009-07-27 19:05:15 +00:00
|
|
|
ctrl_ctx->add_flags = SLOT_FLAG | EP0_FLAG;
|
2009-04-28 02:57:38 +00:00
|
|
|
|
|
|
|
/* 3) Only the control endpoint is valid - one endpoint context */
|
2009-07-27 19:05:15 +00:00
|
|
|
slot_ctx->dev_info |= LAST_CTX(1);
|
2009-04-28 02:57:38 +00:00
|
|
|
|
2009-09-04 17:53:17 +00:00
|
|
|
slot_ctx->dev_info |= (u32) udev->route;
|
2009-04-28 02:57:38 +00:00
|
|
|
switch (udev->speed) {
|
|
|
|
case USB_SPEED_SUPER:
|
2009-07-27 19:05:15 +00:00
|
|
|
slot_ctx->dev_info |= (u32) SLOT_SPEED_SS;
|
2009-04-28 02:57:38 +00:00
|
|
|
break;
|
|
|
|
case USB_SPEED_HIGH:
|
2009-07-27 19:05:15 +00:00
|
|
|
slot_ctx->dev_info |= (u32) SLOT_SPEED_HS;
|
2009-04-28 02:57:38 +00:00
|
|
|
break;
|
|
|
|
case USB_SPEED_FULL:
|
2009-07-27 19:05:15 +00:00
|
|
|
slot_ctx->dev_info |= (u32) SLOT_SPEED_FS;
|
2009-04-28 02:57:38 +00:00
|
|
|
break;
|
|
|
|
case USB_SPEED_LOW:
|
2009-07-27 19:05:15 +00:00
|
|
|
slot_ctx->dev_info |= (u32) SLOT_SPEED_LS;
|
2009-04-28 02:57:38 +00:00
|
|
|
break;
|
2010-01-14 19:08:04 +00:00
|
|
|
case USB_SPEED_WIRELESS:
|
2009-04-28 02:57:38 +00:00
|
|
|
xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
|
|
|
|
return -EINVAL;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
/* Speed was set earlier, this shouldn't happen. */
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
/* Find the root hub port this device is under */
|
|
|
|
for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
|
|
|
|
top_dev = top_dev->parent)
|
|
|
|
/* Found device below root hub */;
|
2009-07-27 19:05:15 +00:00
|
|
|
slot_ctx->dev_info2 |= (u32) ROOT_HUB_PORT(top_dev->portnum);
|
2009-04-28 02:57:38 +00:00
|
|
|
xhci_dbg(xhci, "Set root hub portnum to %d\n", top_dev->portnum);
|
|
|
|
|
|
|
|
/* Is this a LS/FS device under a HS hub? */
|
|
|
|
if ((udev->speed == USB_SPEED_LOW || udev->speed == USB_SPEED_FULL) &&
|
|
|
|
udev->tt) {
|
2009-07-27 19:05:15 +00:00
|
|
|
slot_ctx->tt_info = udev->tt->hub->slot_id;
|
|
|
|
slot_ctx->tt_info |= udev->ttport << 8;
|
2009-09-04 17:53:19 +00:00
|
|
|
if (udev->tt->multi)
|
|
|
|
slot_ctx->dev_info |= DEV_MTT;
|
2009-04-28 02:57:38 +00:00
|
|
|
}
|
2009-04-30 02:14:08 +00:00
|
|
|
xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
|
2009-04-28 02:57:38 +00:00
|
|
|
xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
|
|
|
|
|
|
|
|
/* Step 4 - ring already allocated */
|
|
|
|
/* Step 5 */
|
|
|
|
ep0_ctx->ep_info2 = EP_TYPE(CTRL_EP);
|
|
|
|
/*
|
|
|
|
* XXX: Not sure about wireless USB devices.
|
|
|
|
*/
|
2009-08-07 21:04:46 +00:00
|
|
|
switch (udev->speed) {
|
|
|
|
case USB_SPEED_SUPER:
|
2009-04-28 02:57:38 +00:00
|
|
|
ep0_ctx->ep_info2 |= MAX_PACKET(512);
|
2009-08-07 21:04:46 +00:00
|
|
|
break;
|
|
|
|
case USB_SPEED_HIGH:
|
|
|
|
/* USB core guesses at a 64-byte max packet first for FS devices */
|
|
|
|
case USB_SPEED_FULL:
|
|
|
|
ep0_ctx->ep_info2 |= MAX_PACKET(64);
|
|
|
|
break;
|
|
|
|
case USB_SPEED_LOW:
|
2009-04-28 02:57:38 +00:00
|
|
|
ep0_ctx->ep_info2 |= MAX_PACKET(8);
|
2009-08-07 21:04:46 +00:00
|
|
|
break;
|
2010-01-14 19:08:04 +00:00
|
|
|
case USB_SPEED_WIRELESS:
|
2009-08-07 21:04:46 +00:00
|
|
|
xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
|
|
|
|
return -EINVAL;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
/* New speed? */
|
|
|
|
BUG();
|
|
|
|
}
|
2009-04-28 02:57:38 +00:00
|
|
|
/* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
|
|
|
|
ep0_ctx->ep_info2 |= MAX_BURST(0);
|
|
|
|
ep0_ctx->ep_info2 |= ERROR_COUNT(3);
|
|
|
|
|
2009-07-27 19:03:31 +00:00
|
|
|
ep0_ctx->deq =
|
2009-09-04 17:53:09 +00:00
|
|
|
dev->eps[0].ring->first_seg->dma;
|
|
|
|
ep0_ctx->deq |= dev->eps[0].ring->cycle_state;
|
2009-04-28 02:57:38 +00:00
|
|
|
|
|
|
|
/* Steps 7 and 8 were done in xhci_alloc_virt_device() */
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
USB: xhci: Bandwidth allocation support
Since the xHCI host controller hardware (xHC) has an internal schedule, it
needs a better representation of what devices are consuming bandwidth on
the bus. Each device is represented by a device context, with data about
the device, endpoints, and pointers to each endpoint ring.
We need to update the endpoint information for a device context before a
new configuration or alternate interface setting is selected. We setup an
input device context with modified endpoint information and newly
allocated endpoint rings, and then submit a Configure Endpoint Command to
the hardware.
The host controller can reject the new configuration if it exceeds the bus
bandwidth, or the host controller doesn't have enough internal resources
for the configuration. If the command fails, we still have the older
device context with the previous configuration. If the command succeeds,
we free the old endpoint rings.
The root hub isn't a real device, so always say yes to any bandwidth
changes for it.
The USB core will enable, disable, and then enable endpoint 0 several
times during the initialization sequence. The device will always have an
endpoint ring for endpoint 0 and bandwidth allocated for that, unless the
device is disconnected or gets a SetAddress 0 request. So we don't pay
attention for when xhci_check_bandwidth() is called for a re-add of
endpoint 0.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2009-04-28 02:58:38 +00:00
|
|
|
/* Return the polling or NAK interval.
|
|
|
|
*
|
|
|
|
* The polling interval is expressed in "microframes". If xHCI's Interval field
|
|
|
|
* is set to N, it will service the endpoint every 2^(Interval)*125us.
|
|
|
|
*
|
|
|
|
* The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
|
|
|
|
* is set to 0.
|
|
|
|
*/
|
|
|
|
static inline unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
|
|
|
|
struct usb_host_endpoint *ep)
|
|
|
|
{
|
|
|
|
unsigned int interval = 0;
|
|
|
|
|
|
|
|
switch (udev->speed) {
|
|
|
|
case USB_SPEED_HIGH:
|
|
|
|
/* Max NAK rate */
|
|
|
|
if (usb_endpoint_xfer_control(&ep->desc) ||
|
|
|
|
usb_endpoint_xfer_bulk(&ep->desc))
|
|
|
|
interval = ep->desc.bInterval;
|
|
|
|
/* Fall through - SS and HS isoc/int have same decoding */
|
|
|
|
case USB_SPEED_SUPER:
|
|
|
|
if (usb_endpoint_xfer_int(&ep->desc) ||
|
|
|
|
usb_endpoint_xfer_isoc(&ep->desc)) {
|
|
|
|
if (ep->desc.bInterval == 0)
|
|
|
|
interval = 0;
|
|
|
|
else
|
|
|
|
interval = ep->desc.bInterval - 1;
|
|
|
|
if (interval > 15)
|
|
|
|
interval = 15;
|
|
|
|
if (interval != ep->desc.bInterval + 1)
|
|
|
|
dev_warn(&udev->dev, "ep %#x - rounding interval to %d microframes\n",
|
|
|
|
ep->desc.bEndpointAddress, 1 << interval);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
/* Convert bInterval (in 1-255 frames) to microframes and round down to
|
|
|
|
* nearest power of 2.
|
|
|
|
*/
|
|
|
|
case USB_SPEED_FULL:
|
|
|
|
case USB_SPEED_LOW:
|
|
|
|
if (usb_endpoint_xfer_int(&ep->desc) ||
|
|
|
|
usb_endpoint_xfer_isoc(&ep->desc)) {
|
|
|
|
interval = fls(8*ep->desc.bInterval) - 1;
|
|
|
|
if (interval > 10)
|
|
|
|
interval = 10;
|
|
|
|
if (interval < 3)
|
|
|
|
interval = 3;
|
|
|
|
if ((1 << interval) != 8*ep->desc.bInterval)
|
2010-03-16 19:59:24 +00:00
|
|
|
dev_warn(&udev->dev,
|
|
|
|
"ep %#x - rounding interval"
|
|
|
|
" to %d microframes, "
|
|
|
|
"ep desc says %d microframes\n",
|
|
|
|
ep->desc.bEndpointAddress,
|
|
|
|
1 << interval,
|
|
|
|
8*ep->desc.bInterval);
|
USB: xhci: Bandwidth allocation support
Since the xHCI host controller hardware (xHC) has an internal schedule, it
needs a better representation of what devices are consuming bandwidth on
the bus. Each device is represented by a device context, with data about
the device, endpoints, and pointers to each endpoint ring.
We need to update the endpoint information for a device context before a
new configuration or alternate interface setting is selected. We setup an
input device context with modified endpoint information and newly
allocated endpoint rings, and then submit a Configure Endpoint Command to
the hardware.
The host controller can reject the new configuration if it exceeds the bus
bandwidth, or the host controller doesn't have enough internal resources
for the configuration. If the command fails, we still have the older
device context with the previous configuration. If the command succeeds,
we free the old endpoint rings.
The root hub isn't a real device, so always say yes to any bandwidth
changes for it.
The USB core will enable, disable, and then enable endpoint 0 several
times during the initialization sequence. The device will always have an
endpoint ring for endpoint 0 and bandwidth allocated for that, unless the
device is disconnected or gets a SetAddress 0 request. So we don't pay
attention for when xhci_check_bandwidth() is called for a re-add of
endpoint 0.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2009-04-28 02:58:38 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
return EP_INTERVAL(interval);
|
|
|
|
}
|
|
|
|
|
2010-04-16 15:07:04 +00:00
|
|
|
/* The "Mult" field in the endpoint context is only set for SuperSpeed devices.
|
|
|
|
* High speed endpoint descriptors can define "the number of additional
|
|
|
|
* transaction opportunities per microframe", but that goes in the Max Burst
|
|
|
|
* endpoint context field.
|
|
|
|
*/
|
|
|
|
static inline u32 xhci_get_endpoint_mult(struct usb_device *udev,
|
|
|
|
struct usb_host_endpoint *ep)
|
|
|
|
{
|
|
|
|
if (udev->speed != USB_SPEED_SUPER || !ep->ss_ep_comp)
|
|
|
|
return 0;
|
|
|
|
return ep->ss_ep_comp->desc.bmAttributes;
|
|
|
|
}
|
|
|
|
|
USB: xhci: Bandwidth allocation support
Since the xHCI host controller hardware (xHC) has an internal schedule, it
needs a better representation of what devices are consuming bandwidth on
the bus. Each device is represented by a device context, with data about
the device, endpoints, and pointers to each endpoint ring.
We need to update the endpoint information for a device context before a
new configuration or alternate interface setting is selected. We setup an
input device context with modified endpoint information and newly
allocated endpoint rings, and then submit a Configure Endpoint Command to
the hardware.
The host controller can reject the new configuration if it exceeds the bus
bandwidth, or the host controller doesn't have enough internal resources
for the configuration. If the command fails, we still have the older
device context with the previous configuration. If the command succeeds,
we free the old endpoint rings.
The root hub isn't a real device, so always say yes to any bandwidth
changes for it.
The USB core will enable, disable, and then enable endpoint 0 several
times during the initialization sequence. The device will always have an
endpoint ring for endpoint 0 and bandwidth allocated for that, unless the
device is disconnected or gets a SetAddress 0 request. So we don't pay
attention for when xhci_check_bandwidth() is called for a re-add of
endpoint 0.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2009-04-28 02:58:38 +00:00
|
|
|
static inline u32 xhci_get_endpoint_type(struct usb_device *udev,
|
|
|
|
struct usb_host_endpoint *ep)
|
|
|
|
{
|
|
|
|
int in;
|
|
|
|
u32 type;
|
|
|
|
|
|
|
|
in = usb_endpoint_dir_in(&ep->desc);
|
|
|
|
if (usb_endpoint_xfer_control(&ep->desc)) {
|
|
|
|
type = EP_TYPE(CTRL_EP);
|
|
|
|
} else if (usb_endpoint_xfer_bulk(&ep->desc)) {
|
|
|
|
if (in)
|
|
|
|
type = EP_TYPE(BULK_IN_EP);
|
|
|
|
else
|
|
|
|
type = EP_TYPE(BULK_OUT_EP);
|
|
|
|
} else if (usb_endpoint_xfer_isoc(&ep->desc)) {
|
|
|
|
if (in)
|
|
|
|
type = EP_TYPE(ISOC_IN_EP);
|
|
|
|
else
|
|
|
|
type = EP_TYPE(ISOC_OUT_EP);
|
|
|
|
} else if (usb_endpoint_xfer_int(&ep->desc)) {
|
|
|
|
if (in)
|
|
|
|
type = EP_TYPE(INT_IN_EP);
|
|
|
|
else
|
|
|
|
type = EP_TYPE(INT_OUT_EP);
|
|
|
|
} else {
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
return type;
|
|
|
|
}
|
|
|
|
|
USB: xhci: properly set endpoint context fields for periodic eps.
For periodic endpoints, we must let the xHCI hardware know the maximum
payload an endpoint can transfer in one service interval. The xHCI
specification refers to this as the Maximum Endpoint Service Interval Time
Payload (Max ESIT Payload). This is used by the hardware for bandwidth
management and scheduling of packets.
For SuperSpeed endpoints, the maximum is calculated by multiplying the max
packet size by the number of bursts and the number of opportunities to
transfer within a service interval (the Mult field of the SuperSpeed
Endpoint companion descriptor). Devices advertise this in the
wBytesPerInterval field of their SuperSpeed Endpoint Companion Descriptor.
For high speed devices, this is taken by multiplying the max packet size by the
"number of additional transaction opportunities per microframe" (the high
bits of the wMaxPacketSize field in the endpoint descriptor).
For FS/LS devices, this is just the max packet size.
The other thing we must set in the endpoint context is the Average TRB
Length. This is supposed to be the average of the total bytes in the
transfer descriptor (TD), divided by the number of transfer request blocks
(TRBs) it takes to describe the TD. This gives the host controller an
indication of whether the driver will be enqueuing a scatter gather list
with many entries comprised of small buffers, or one contiguous buffer.
It also takes into account the number of extra TRBs you need for every TD.
This includes No-op TRBs and Link TRBs used to link ring segments
together. Some drivers may choose to chain an Event Data TRB on the end
of every TD, thus increasing the average number of TRBs per TD. The Linux
xHCI driver does not use Event Data TRBs.
In theory, if there was an API to allow drivers to state what their
bandwidth requirements are, we could set this field accurately. For now,
we set it to the same number as the Max ESIT payload.
The Average TRB Length should also be set for bulk and control endpoints,
but I have no idea how to guess what it should be.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Cc: stable <stable@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2010-04-16 15:07:27 +00:00
|
|
|
/* Return the maximum endpoint service interval time (ESIT) payload.
|
|
|
|
* Basically, this is the maxpacket size, multiplied by the burst size
|
|
|
|
* and mult size.
|
|
|
|
*/
|
|
|
|
static inline u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci,
|
|
|
|
struct usb_device *udev,
|
|
|
|
struct usb_host_endpoint *ep)
|
|
|
|
{
|
|
|
|
int max_burst;
|
|
|
|
int max_packet;
|
|
|
|
|
|
|
|
/* Only applies for interrupt or isochronous endpoints */
|
|
|
|
if (usb_endpoint_xfer_control(&ep->desc) ||
|
|
|
|
usb_endpoint_xfer_bulk(&ep->desc))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (udev->speed == USB_SPEED_SUPER) {
|
|
|
|
if (ep->ss_ep_comp)
|
|
|
|
return ep->ss_ep_comp->desc.wBytesPerInterval;
|
|
|
|
xhci_warn(xhci, "WARN no SS endpoint companion descriptor.\n");
|
|
|
|
/* Assume no bursts, no multiple opportunities to send. */
|
|
|
|
return ep->desc.wMaxPacketSize;
|
|
|
|
}
|
|
|
|
|
|
|
|
max_packet = ep->desc.wMaxPacketSize & 0x3ff;
|
|
|
|
max_burst = (ep->desc.wMaxPacketSize & 0x1800) >> 11;
|
|
|
|
/* A 0 in max burst means 1 transfer per ESIT */
|
|
|
|
return max_packet * (max_burst + 1);
|
|
|
|
}
|
|
|
|
|
USB: xhci: Bandwidth allocation support
Since the xHCI host controller hardware (xHC) has an internal schedule, it
needs a better representation of what devices are consuming bandwidth on
the bus. Each device is represented by a device context, with data about
the device, endpoints, and pointers to each endpoint ring.
We need to update the endpoint information for a device context before a
new configuration or alternate interface setting is selected. We setup an
input device context with modified endpoint information and newly
allocated endpoint rings, and then submit a Configure Endpoint Command to
the hardware.
The host controller can reject the new configuration if it exceeds the bus
bandwidth, or the host controller doesn't have enough internal resources
for the configuration. If the command fails, we still have the older
device context with the previous configuration. If the command succeeds,
we free the old endpoint rings.
The root hub isn't a real device, so always say yes to any bandwidth
changes for it.
The USB core will enable, disable, and then enable endpoint 0 several
times during the initialization sequence. The device will always have an
endpoint ring for endpoint 0 and bandwidth allocated for that, unless the
device is disconnected or gets a SetAddress 0 request. So we don't pay
attention for when xhci_check_bandwidth() is called for a re-add of
endpoint 0.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2009-04-28 02:58:38 +00:00
|
|
|
int xhci_endpoint_init(struct xhci_hcd *xhci,
|
|
|
|
struct xhci_virt_device *virt_dev,
|
|
|
|
struct usb_device *udev,
|
2009-05-14 18:44:22 +00:00
|
|
|
struct usb_host_endpoint *ep,
|
|
|
|
gfp_t mem_flags)
|
USB: xhci: Bandwidth allocation support
Since the xHCI host controller hardware (xHC) has an internal schedule, it
needs a better representation of what devices are consuming bandwidth on
the bus. Each device is represented by a device context, with data about
the device, endpoints, and pointers to each endpoint ring.
We need to update the endpoint information for a device context before a
new configuration or alternate interface setting is selected. We setup an
input device context with modified endpoint information and newly
allocated endpoint rings, and then submit a Configure Endpoint Command to
the hardware.
The host controller can reject the new configuration if it exceeds the bus
bandwidth, or the host controller doesn't have enough internal resources
for the configuration. If the command fails, we still have the older
device context with the previous configuration. If the command succeeds,
we free the old endpoint rings.
The root hub isn't a real device, so always say yes to any bandwidth
changes for it.
The USB core will enable, disable, and then enable endpoint 0 several
times during the initialization sequence. The device will always have an
endpoint ring for endpoint 0 and bandwidth allocated for that, unless the
device is disconnected or gets a SetAddress 0 request. So we don't pay
attention for when xhci_check_bandwidth() is called for a re-add of
endpoint 0.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2009-04-28 02:58:38 +00:00
|
|
|
{
|
|
|
|
unsigned int ep_index;
|
|
|
|
struct xhci_ep_ctx *ep_ctx;
|
|
|
|
struct xhci_ring *ep_ring;
|
|
|
|
unsigned int max_packet;
|
|
|
|
unsigned int max_burst;
|
USB: xhci: properly set endpoint context fields for periodic eps.
For periodic endpoints, we must let the xHCI hardware know the maximum
payload an endpoint can transfer in one service interval. The xHCI
specification refers to this as the Maximum Endpoint Service Interval Time
Payload (Max ESIT Payload). This is used by the hardware for bandwidth
management and scheduling of packets.
For SuperSpeed endpoints, the maximum is calculated by multiplying the max
packet size by the number of bursts and the number of opportunities to
transfer within a service interval (the Mult field of the SuperSpeed
Endpoint companion descriptor). Devices advertise this in the
wBytesPerInterval field of their SuperSpeed Endpoint Companion Descriptor.
For high speed devices, this is taken by multiplying the max packet size by the
"number of additional transaction opportunities per microframe" (the high
bits of the wMaxPacketSize field in the endpoint descriptor).
For FS/LS devices, this is just the max packet size.
The other thing we must set in the endpoint context is the Average TRB
Length. This is supposed to be the average of the total bytes in the
transfer descriptor (TD), divided by the number of transfer request blocks
(TRBs) it takes to describe the TD. This gives the host controller an
indication of whether the driver will be enqueuing a scatter gather list
with many entries comprised of small buffers, or one contiguous buffer.
It also takes into account the number of extra TRBs you need for every TD.
This includes No-op TRBs and Link TRBs used to link ring segments
together. Some drivers may choose to chain an Event Data TRB on the end
of every TD, thus increasing the average number of TRBs per TD. The Linux
xHCI driver does not use Event Data TRBs.
In theory, if there was an API to allow drivers to state what their
bandwidth requirements are, we could set this field accurately. For now,
we set it to the same number as the Max ESIT payload.
The Average TRB Length should also be set for bulk and control endpoints,
but I have no idea how to guess what it should be.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Cc: stable <stable@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2010-04-16 15:07:27 +00:00
|
|
|
u32 max_esit_payload;
|
USB: xhci: Bandwidth allocation support
Since the xHCI host controller hardware (xHC) has an internal schedule, it
needs a better representation of what devices are consuming bandwidth on
the bus. Each device is represented by a device context, with data about
the device, endpoints, and pointers to each endpoint ring.
We need to update the endpoint information for a device context before a
new configuration or alternate interface setting is selected. We setup an
input device context with modified endpoint information and newly
allocated endpoint rings, and then submit a Configure Endpoint Command to
the hardware.
The host controller can reject the new configuration if it exceeds the bus
bandwidth, or the host controller doesn't have enough internal resources
for the configuration. If the command fails, we still have the older
device context with the previous configuration. If the command succeeds,
we free the old endpoint rings.
The root hub isn't a real device, so always say yes to any bandwidth
changes for it.
The USB core will enable, disable, and then enable endpoint 0 several
times during the initialization sequence. The device will always have an
endpoint ring for endpoint 0 and bandwidth allocated for that, unless the
device is disconnected or gets a SetAddress 0 request. So we don't pay
attention for when xhci_check_bandwidth() is called for a re-add of
endpoint 0.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2009-04-28 02:58:38 +00:00
|
|
|
|
|
|
|
ep_index = xhci_get_endpoint_index(&ep->desc);
|
2009-07-27 19:05:15 +00:00
|
|
|
ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
|
USB: xhci: Bandwidth allocation support
Since the xHCI host controller hardware (xHC) has an internal schedule, it
needs a better representation of what devices are consuming bandwidth on
the bus. Each device is represented by a device context, with data about
the device, endpoints, and pointers to each endpoint ring.
We need to update the endpoint information for a device context before a
new configuration or alternate interface setting is selected. We setup an
input device context with modified endpoint information and newly
allocated endpoint rings, and then submit a Configure Endpoint Command to
the hardware.
The host controller can reject the new configuration if it exceeds the bus
bandwidth, or the host controller doesn't have enough internal resources
for the configuration. If the command fails, we still have the older
device context with the previous configuration. If the command succeeds,
we free the old endpoint rings.
The root hub isn't a real device, so always say yes to any bandwidth
changes for it.
The USB core will enable, disable, and then enable endpoint 0 several
times during the initialization sequence. The device will always have an
endpoint ring for endpoint 0 and bandwidth allocated for that, unless the
device is disconnected or gets a SetAddress 0 request. So we don't pay
attention for when xhci_check_bandwidth() is called for a re-add of
endpoint 0.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2009-04-28 02:58:38 +00:00
|
|
|
|
|
|
|
/* Set up the endpoint ring */
|
2009-09-04 17:53:09 +00:00
|
|
|
virt_dev->eps[ep_index].new_ring =
|
|
|
|
xhci_ring_alloc(xhci, 1, true, mem_flags);
|
2009-12-03 17:44:29 +00:00
|
|
|
if (!virt_dev->eps[ep_index].new_ring) {
|
|
|
|
/* Attempt to use the ring cache */
|
|
|
|
if (virt_dev->num_rings_cached == 0)
|
|
|
|
return -ENOMEM;
|
|
|
|
virt_dev->eps[ep_index].new_ring =
|
|
|
|
virt_dev->ring_cache[virt_dev->num_rings_cached];
|
|
|
|
virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL;
|
|
|
|
virt_dev->num_rings_cached--;
|
|
|
|
xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring);
|
|
|
|
}
|
2009-09-04 17:53:09 +00:00
|
|
|
ep_ring = virt_dev->eps[ep_index].new_ring;
|
2009-07-27 19:03:31 +00:00
|
|
|
ep_ctx->deq = ep_ring->first_seg->dma | ep_ring->cycle_state;
|
USB: xhci: Bandwidth allocation support
Since the xHCI host controller hardware (xHC) has an internal schedule, it
needs a better representation of what devices are consuming bandwidth on
the bus. Each device is represented by a device context, with data about
the device, endpoints, and pointers to each endpoint ring.
We need to update the endpoint information for a device context before a
new configuration or alternate interface setting is selected. We setup an
input device context with modified endpoint information and newly
allocated endpoint rings, and then submit a Configure Endpoint Command to
the hardware.
The host controller can reject the new configuration if it exceeds the bus
bandwidth, or the host controller doesn't have enough internal resources
for the configuration. If the command fails, we still have the older
device context with the previous configuration. If the command succeeds,
we free the old endpoint rings.
The root hub isn't a real device, so always say yes to any bandwidth
changes for it.
The USB core will enable, disable, and then enable endpoint 0 several
times during the initialization sequence. The device will always have an
endpoint ring for endpoint 0 and bandwidth allocated for that, unless the
device is disconnected or gets a SetAddress 0 request. So we don't pay
attention for when xhci_check_bandwidth() is called for a re-add of
endpoint 0.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2009-04-28 02:58:38 +00:00
|
|
|
|
|
|
|
ep_ctx->ep_info = xhci_get_endpoint_interval(udev, ep);
|
2010-04-16 15:07:04 +00:00
|
|
|
ep_ctx->ep_info |= EP_MULT(xhci_get_endpoint_mult(udev, ep));
|
USB: xhci: Bandwidth allocation support
Since the xHCI host controller hardware (xHC) has an internal schedule, it
needs a better representation of what devices are consuming bandwidth on
the bus. Each device is represented by a device context, with data about
the device, endpoints, and pointers to each endpoint ring.
We need to update the endpoint information for a device context before a
new configuration or alternate interface setting is selected. We setup an
input device context with modified endpoint information and newly
allocated endpoint rings, and then submit a Configure Endpoint Command to
the hardware.
The host controller can reject the new configuration if it exceeds the bus
bandwidth, or the host controller doesn't have enough internal resources
for the configuration. If the command fails, we still have the older
device context with the previous configuration. If the command succeeds,
we free the old endpoint rings.
The root hub isn't a real device, so always say yes to any bandwidth
changes for it.
The USB core will enable, disable, and then enable endpoint 0 several
times during the initialization sequence. The device will always have an
endpoint ring for endpoint 0 and bandwidth allocated for that, unless the
device is disconnected or gets a SetAddress 0 request. So we don't pay
attention for when xhci_check_bandwidth() is called for a re-add of
endpoint 0.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2009-04-28 02:58:38 +00:00
|
|
|
|
|
|
|
/* FIXME dig Mult and streams info out of ep companion desc */
|
|
|
|
|
2009-07-27 19:04:27 +00:00
|
|
|
/* Allow 3 retries for everything but isoc;
|
|
|
|
* error count = 0 means infinite retries.
|
|
|
|
*/
|
USB: xhci: Bandwidth allocation support
Since the xHCI host controller hardware (xHC) has an internal schedule, it
needs a better representation of what devices are consuming bandwidth on
the bus. Each device is represented by a device context, with data about
the device, endpoints, and pointers to each endpoint ring.
We need to update the endpoint information for a device context before a
new configuration or alternate interface setting is selected. We setup an
input device context with modified endpoint information and newly
allocated endpoint rings, and then submit a Configure Endpoint Command to
the hardware.
The host controller can reject the new configuration if it exceeds the bus
bandwidth, or the host controller doesn't have enough internal resources
for the configuration. If the command fails, we still have the older
device context with the previous configuration. If the command succeeds,
we free the old endpoint rings.
The root hub isn't a real device, so always say yes to any bandwidth
changes for it.
The USB core will enable, disable, and then enable endpoint 0 several
times during the initialization sequence. The device will always have an
endpoint ring for endpoint 0 and bandwidth allocated for that, unless the
device is disconnected or gets a SetAddress 0 request. So we don't pay
attention for when xhci_check_bandwidth() is called for a re-add of
endpoint 0.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2009-04-28 02:58:38 +00:00
|
|
|
if (!usb_endpoint_xfer_isoc(&ep->desc))
|
|
|
|
ep_ctx->ep_info2 = ERROR_COUNT(3);
|
|
|
|
else
|
2009-07-27 19:04:27 +00:00
|
|
|
ep_ctx->ep_info2 = ERROR_COUNT(1);
|
USB: xhci: Bandwidth allocation support
Since the xHCI host controller hardware (xHC) has an internal schedule, it
needs a better representation of what devices are consuming bandwidth on
the bus. Each device is represented by a device context, with data about
the device, endpoints, and pointers to each endpoint ring.
We need to update the endpoint information for a device context before a
new configuration or alternate interface setting is selected. We setup an
input device context with modified endpoint information and newly
allocated endpoint rings, and then submit a Configure Endpoint Command to
the hardware.
The host controller can reject the new configuration if it exceeds the bus
bandwidth, or the host controller doesn't have enough internal resources
for the configuration. If the command fails, we still have the older
device context with the previous configuration. If the command succeeds,
we free the old endpoint rings.
The root hub isn't a real device, so always say yes to any bandwidth
changes for it.
The USB core will enable, disable, and then enable endpoint 0 several
times during the initialization sequence. The device will always have an
endpoint ring for endpoint 0 and bandwidth allocated for that, unless the
device is disconnected or gets a SetAddress 0 request. So we don't pay
attention for when xhci_check_bandwidth() is called for a re-add of
endpoint 0.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2009-04-28 02:58:38 +00:00
|
|
|
|
|
|
|
ep_ctx->ep_info2 |= xhci_get_endpoint_type(udev, ep);
|
|
|
|
|
|
|
|
/* Set the max packet size and max burst */
|
|
|
|
switch (udev->speed) {
|
|
|
|
case USB_SPEED_SUPER:
|
|
|
|
max_packet = ep->desc.wMaxPacketSize;
|
|
|
|
ep_ctx->ep_info2 |= MAX_PACKET(max_packet);
|
2009-04-28 02:58:50 +00:00
|
|
|
/* dig out max burst from ep companion desc */
|
2009-07-27 19:04:38 +00:00
|
|
|
if (!ep->ss_ep_comp) {
|
|
|
|
xhci_warn(xhci, "WARN no SS endpoint companion descriptor.\n");
|
|
|
|
max_packet = 0;
|
|
|
|
} else {
|
|
|
|
max_packet = ep->ss_ep_comp->desc.bMaxBurst;
|
|
|
|
}
|
2009-04-28 02:58:50 +00:00
|
|
|
ep_ctx->ep_info2 |= MAX_BURST(max_packet);
|
USB: xhci: Bandwidth allocation support
Since the xHCI host controller hardware (xHC) has an internal schedule, it
needs a better representation of what devices are consuming bandwidth on
the bus. Each device is represented by a device context, with data about
the device, endpoints, and pointers to each endpoint ring.
We need to update the endpoint information for a device context before a
new configuration or alternate interface setting is selected. We setup an
input device context with modified endpoint information and newly
allocated endpoint rings, and then submit a Configure Endpoint Command to
the hardware.
The host controller can reject the new configuration if it exceeds the bus
bandwidth, or the host controller doesn't have enough internal resources
for the configuration. If the command fails, we still have the older
device context with the previous configuration. If the command succeeds,
we free the old endpoint rings.
The root hub isn't a real device, so always say yes to any bandwidth
changes for it.
The USB core will enable, disable, and then enable endpoint 0 several
times during the initialization sequence. The device will always have an
endpoint ring for endpoint 0 and bandwidth allocated for that, unless the
device is disconnected or gets a SetAddress 0 request. So we don't pay
attention for when xhci_check_bandwidth() is called for a re-add of
endpoint 0.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2009-04-28 02:58:38 +00:00
|
|
|
break;
|
|
|
|
case USB_SPEED_HIGH:
|
|
|
|
/* bits 11:12 specify the number of additional transaction
|
|
|
|
* opportunities per microframe (USB 2.0, section 9.6.6)
|
|
|
|
*/
|
|
|
|
if (usb_endpoint_xfer_isoc(&ep->desc) ||
|
|
|
|
usb_endpoint_xfer_int(&ep->desc)) {
|
|
|
|
max_burst = (ep->desc.wMaxPacketSize & 0x1800) >> 11;
|
|
|
|
ep_ctx->ep_info2 |= MAX_BURST(max_burst);
|
|
|
|
}
|
|
|
|
/* Fall through */
|
|
|
|
case USB_SPEED_FULL:
|
|
|
|
case USB_SPEED_LOW:
|
|
|
|
max_packet = ep->desc.wMaxPacketSize & 0x3ff;
|
|
|
|
ep_ctx->ep_info2 |= MAX_PACKET(max_packet);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
BUG();
|
|
|
|
}
|
USB: xhci: properly set endpoint context fields for periodic eps.
For periodic endpoints, we must let the xHCI hardware know the maximum
payload an endpoint can transfer in one service interval. The xHCI
specification refers to this as the Maximum Endpoint Service Interval Time
Payload (Max ESIT Payload). This is used by the hardware for bandwidth
management and scheduling of packets.
For SuperSpeed endpoints, the maximum is calculated by multiplying the max
packet size by the number of bursts and the number of opportunities to
transfer within a service interval (the Mult field of the SuperSpeed
Endpoint companion descriptor). Devices advertise this in the
wBytesPerInterval field of their SuperSpeed Endpoint Companion Descriptor.
For high speed devices, this is taken by multiplying the max packet size by the
"number of additional transaction opportunities per microframe" (the high
bits of the wMaxPacketSize field in the endpoint descriptor).
For FS/LS devices, this is just the max packet size.
The other thing we must set in the endpoint context is the Average TRB
Length. This is supposed to be the average of the total bytes in the
transfer descriptor (TD), divided by the number of transfer request blocks
(TRBs) it takes to describe the TD. This gives the host controller an
indication of whether the driver will be enqueuing a scatter gather list
with many entries comprised of small buffers, or one contiguous buffer.
It also takes into account the number of extra TRBs you need for every TD.
This includes No-op TRBs and Link TRBs used to link ring segments
together. Some drivers may choose to chain an Event Data TRB on the end
of every TD, thus increasing the average number of TRBs per TD. The Linux
xHCI driver does not use Event Data TRBs.
In theory, if there was an API to allow drivers to state what their
bandwidth requirements are, we could set this field accurately. For now,
we set it to the same number as the Max ESIT payload.
The Average TRB Length should also be set for bulk and control endpoints,
but I have no idea how to guess what it should be.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Cc: stable <stable@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2010-04-16 15:07:27 +00:00
|
|
|
max_esit_payload = xhci_get_max_esit_payload(xhci, udev, ep);
|
|
|
|
ep_ctx->tx_info = MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* XXX no idea how to calculate the average TRB buffer length for bulk
|
|
|
|
* endpoints, as the driver gives us no clue how big each scatter gather
|
|
|
|
* list entry (or buffer) is going to be.
|
|
|
|
*
|
|
|
|
* For isochronous and interrupt endpoints, we set it to the max
|
|
|
|
* available, until we have new API in the USB core to allow drivers to
|
|
|
|
* declare how much bandwidth they actually need.
|
|
|
|
*
|
|
|
|
* Normally, it would be calculated by taking the total of the buffer
|
|
|
|
* lengths in the TD and then dividing by the number of TRBs in a TD,
|
|
|
|
* including link TRBs, No-op TRBs, and Event data TRBs. Since we don't
|
|
|
|
* use Event Data TRBs, and we don't chain in a link TRB on short
|
|
|
|
* transfers, we're basically dividing by 1.
|
|
|
|
*/
|
|
|
|
ep_ctx->tx_info |= AVG_TRB_LENGTH_FOR_EP(max_esit_payload);
|
|
|
|
|
USB: xhci: Bandwidth allocation support
Since the xHCI host controller hardware (xHC) has an internal schedule, it
needs a better representation of what devices are consuming bandwidth on
the bus. Each device is represented by a device context, with data about
the device, endpoints, and pointers to each endpoint ring.
We need to update the endpoint information for a device context before a
new configuration or alternate interface setting is selected. We setup an
input device context with modified endpoint information and newly
allocated endpoint rings, and then submit a Configure Endpoint Command to
the hardware.
The host controller can reject the new configuration if it exceeds the bus
bandwidth, or the host controller doesn't have enough internal resources
for the configuration. If the command fails, we still have the older
device context with the previous configuration. If the command succeeds,
we free the old endpoint rings.
The root hub isn't a real device, so always say yes to any bandwidth
changes for it.
The USB core will enable, disable, and then enable endpoint 0 several
times during the initialization sequence. The device will always have an
endpoint ring for endpoint 0 and bandwidth allocated for that, unless the
device is disconnected or gets a SetAddress 0 request. So we don't pay
attention for when xhci_check_bandwidth() is called for a re-add of
endpoint 0.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2009-04-28 02:58:38 +00:00
|
|
|
/* FIXME Debug endpoint context */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void xhci_endpoint_zero(struct xhci_hcd *xhci,
|
|
|
|
struct xhci_virt_device *virt_dev,
|
|
|
|
struct usb_host_endpoint *ep)
|
|
|
|
{
|
|
|
|
unsigned int ep_index;
|
|
|
|
struct xhci_ep_ctx *ep_ctx;
|
|
|
|
|
|
|
|
ep_index = xhci_get_endpoint_index(&ep->desc);
|
2009-07-27 19:05:15 +00:00
|
|
|
ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
|
USB: xhci: Bandwidth allocation support
Since the xHCI host controller hardware (xHC) has an internal schedule, it
needs a better representation of what devices are consuming bandwidth on
the bus. Each device is represented by a device context, with data about
the device, endpoints, and pointers to each endpoint ring.
We need to update the endpoint information for a device context before a
new configuration or alternate interface setting is selected. We setup an
input device context with modified endpoint information and newly
allocated endpoint rings, and then submit a Configure Endpoint Command to
the hardware.
The host controller can reject the new configuration if it exceeds the bus
bandwidth, or the host controller doesn't have enough internal resources
for the configuration. If the command fails, we still have the older
device context with the previous configuration. If the command succeeds,
we free the old endpoint rings.
The root hub isn't a real device, so always say yes to any bandwidth
changes for it.
The USB core will enable, disable, and then enable endpoint 0 several
times during the initialization sequence. The device will always have an
endpoint ring for endpoint 0 and bandwidth allocated for that, unless the
device is disconnected or gets a SetAddress 0 request. So we don't pay
attention for when xhci_check_bandwidth() is called for a re-add of
endpoint 0.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2009-04-28 02:58:38 +00:00
|
|
|
|
|
|
|
ep_ctx->ep_info = 0;
|
|
|
|
ep_ctx->ep_info2 = 0;
|
2009-07-27 19:03:31 +00:00
|
|
|
ep_ctx->deq = 0;
|
USB: xhci: Bandwidth allocation support
Since the xHCI host controller hardware (xHC) has an internal schedule, it
needs a better representation of what devices are consuming bandwidth on
the bus. Each device is represented by a device context, with data about
the device, endpoints, and pointers to each endpoint ring.
We need to update the endpoint information for a device context before a
new configuration or alternate interface setting is selected. We setup an
input device context with modified endpoint information and newly
allocated endpoint rings, and then submit a Configure Endpoint Command to
the hardware.
The host controller can reject the new configuration if it exceeds the bus
bandwidth, or the host controller doesn't have enough internal resources
for the configuration. If the command fails, we still have the older
device context with the previous configuration. If the command succeeds,
we free the old endpoint rings.
The root hub isn't a real device, so always say yes to any bandwidth
changes for it.
The USB core will enable, disable, and then enable endpoint 0 several
times during the initialization sequence. The device will always have an
endpoint ring for endpoint 0 and bandwidth allocated for that, unless the
device is disconnected or gets a SetAddress 0 request. So we don't pay
attention for when xhci_check_bandwidth() is called for a re-add of
endpoint 0.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2009-04-28 02:58:38 +00:00
|
|
|
ep_ctx->tx_info = 0;
|
|
|
|
/* Don't free the endpoint ring until the set interface or configuration
|
|
|
|
* request succeeds.
|
|
|
|
*/
|
|
|
|
}
|
|
|
|
|
2009-08-07 21:04:43 +00:00
|
|
|
/* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
|
|
|
|
* Useful when you want to change one particular aspect of the endpoint and then
|
|
|
|
* issue a configure endpoint command.
|
|
|
|
*/
|
|
|
|
void xhci_endpoint_copy(struct xhci_hcd *xhci,
|
2009-09-04 17:53:13 +00:00
|
|
|
struct xhci_container_ctx *in_ctx,
|
|
|
|
struct xhci_container_ctx *out_ctx,
|
|
|
|
unsigned int ep_index)
|
2009-08-07 21:04:43 +00:00
|
|
|
{
|
|
|
|
struct xhci_ep_ctx *out_ep_ctx;
|
|
|
|
struct xhci_ep_ctx *in_ep_ctx;
|
|
|
|
|
2009-09-04 17:53:13 +00:00
|
|
|
out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
|
|
|
|
in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
|
2009-08-07 21:04:43 +00:00
|
|
|
|
|
|
|
in_ep_ctx->ep_info = out_ep_ctx->ep_info;
|
|
|
|
in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
|
|
|
|
in_ep_ctx->deq = out_ep_ctx->deq;
|
|
|
|
in_ep_ctx->tx_info = out_ep_ctx->tx_info;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
|
|
|
|
* Useful when you want to change one particular aspect of the endpoint and then
|
|
|
|
* issue a configure endpoint command. Only the context entries field matters,
|
|
|
|
* but we'll copy the whole thing anyway.
|
|
|
|
*/
|
2009-09-04 17:53:13 +00:00
|
|
|
void xhci_slot_copy(struct xhci_hcd *xhci,
|
|
|
|
struct xhci_container_ctx *in_ctx,
|
|
|
|
struct xhci_container_ctx *out_ctx)
|
2009-08-07 21:04:43 +00:00
|
|
|
{
|
|
|
|
struct xhci_slot_ctx *in_slot_ctx;
|
|
|
|
struct xhci_slot_ctx *out_slot_ctx;
|
|
|
|
|
2009-09-04 17:53:13 +00:00
|
|
|
in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
|
|
|
|
out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
|
2009-08-07 21:04:43 +00:00
|
|
|
|
|
|
|
in_slot_ctx->dev_info = out_slot_ctx->dev_info;
|
|
|
|
in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
|
|
|
|
in_slot_ctx->tt_info = out_slot_ctx->tt_info;
|
|
|
|
in_slot_ctx->dev_state = out_slot_ctx->dev_state;
|
|
|
|
}
|
|
|
|
|
2009-07-27 19:05:03 +00:00
|
|
|
/* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
|
|
|
|
static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
struct device *dev = xhci_to_hcd(xhci)->self.controller;
|
|
|
|
int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
|
|
|
|
|
|
|
|
xhci_dbg(xhci, "Allocating %d scratchpad buffers\n", num_sp);
|
|
|
|
|
|
|
|
if (!num_sp)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags);
|
|
|
|
if (!xhci->scratchpad)
|
|
|
|
goto fail_sp;
|
|
|
|
|
|
|
|
xhci->scratchpad->sp_array =
|
|
|
|
pci_alloc_consistent(to_pci_dev(dev),
|
|
|
|
num_sp * sizeof(u64),
|
|
|
|
&xhci->scratchpad->sp_dma);
|
|
|
|
if (!xhci->scratchpad->sp_array)
|
|
|
|
goto fail_sp2;
|
|
|
|
|
|
|
|
xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags);
|
|
|
|
if (!xhci->scratchpad->sp_buffers)
|
|
|
|
goto fail_sp3;
|
|
|
|
|
|
|
|
xhci->scratchpad->sp_dma_buffers =
|
|
|
|
kzalloc(sizeof(dma_addr_t) * num_sp, flags);
|
|
|
|
|
|
|
|
if (!xhci->scratchpad->sp_dma_buffers)
|
|
|
|
goto fail_sp4;
|
|
|
|
|
|
|
|
xhci->dcbaa->dev_context_ptrs[0] = xhci->scratchpad->sp_dma;
|
|
|
|
for (i = 0; i < num_sp; i++) {
|
|
|
|
dma_addr_t dma;
|
|
|
|
void *buf = pci_alloc_consistent(to_pci_dev(dev),
|
|
|
|
xhci->page_size, &dma);
|
|
|
|
if (!buf)
|
|
|
|
goto fail_sp5;
|
|
|
|
|
|
|
|
xhci->scratchpad->sp_array[i] = dma;
|
|
|
|
xhci->scratchpad->sp_buffers[i] = buf;
|
|
|
|
xhci->scratchpad->sp_dma_buffers[i] = dma;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
fail_sp5:
|
|
|
|
for (i = i - 1; i >= 0; i--) {
|
|
|
|
pci_free_consistent(to_pci_dev(dev), xhci->page_size,
|
|
|
|
xhci->scratchpad->sp_buffers[i],
|
|
|
|
xhci->scratchpad->sp_dma_buffers[i]);
|
|
|
|
}
|
|
|
|
kfree(xhci->scratchpad->sp_dma_buffers);
|
|
|
|
|
|
|
|
fail_sp4:
|
|
|
|
kfree(xhci->scratchpad->sp_buffers);
|
|
|
|
|
|
|
|
fail_sp3:
|
|
|
|
pci_free_consistent(to_pci_dev(dev), num_sp * sizeof(u64),
|
|
|
|
xhci->scratchpad->sp_array,
|
|
|
|
xhci->scratchpad->sp_dma);
|
|
|
|
|
|
|
|
fail_sp2:
|
|
|
|
kfree(xhci->scratchpad);
|
|
|
|
xhci->scratchpad = NULL;
|
|
|
|
|
|
|
|
fail_sp:
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void scratchpad_free(struct xhci_hcd *xhci)
|
|
|
|
{
|
|
|
|
int num_sp;
|
|
|
|
int i;
|
|
|
|
struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
|
|
|
|
|
|
|
|
if (!xhci->scratchpad)
|
|
|
|
return;
|
|
|
|
|
|
|
|
num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
|
|
|
|
|
|
|
|
for (i = 0; i < num_sp; i++) {
|
|
|
|
pci_free_consistent(pdev, xhci->page_size,
|
|
|
|
xhci->scratchpad->sp_buffers[i],
|
|
|
|
xhci->scratchpad->sp_dma_buffers[i]);
|
|
|
|
}
|
|
|
|
kfree(xhci->scratchpad->sp_dma_buffers);
|
|
|
|
kfree(xhci->scratchpad->sp_buffers);
|
|
|
|
pci_free_consistent(pdev, num_sp * sizeof(u64),
|
|
|
|
xhci->scratchpad->sp_array,
|
|
|
|
xhci->scratchpad->sp_dma);
|
|
|
|
kfree(xhci->scratchpad);
|
|
|
|
xhci->scratchpad = NULL;
|
|
|
|
}
|
|
|
|
|
2009-09-04 17:53:13 +00:00
|
|
|
struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
|
2009-12-09 23:59:03 +00:00
|
|
|
bool allocate_in_ctx, bool allocate_completion,
|
|
|
|
gfp_t mem_flags)
|
2009-09-04 17:53:13 +00:00
|
|
|
{
|
|
|
|
struct xhci_command *command;
|
|
|
|
|
|
|
|
command = kzalloc(sizeof(*command), mem_flags);
|
|
|
|
if (!command)
|
|
|
|
return NULL;
|
|
|
|
|
2009-12-09 23:59:03 +00:00
|
|
|
if (allocate_in_ctx) {
|
|
|
|
command->in_ctx =
|
|
|
|
xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
|
|
|
|
mem_flags);
|
|
|
|
if (!command->in_ctx) {
|
|
|
|
kfree(command);
|
|
|
|
return NULL;
|
|
|
|
}
|
2009-11-21 11:51:47 +00:00
|
|
|
}
|
2009-09-04 17:53:13 +00:00
|
|
|
|
|
|
|
if (allocate_completion) {
|
|
|
|
command->completion =
|
|
|
|
kzalloc(sizeof(struct completion), mem_flags);
|
|
|
|
if (!command->completion) {
|
|
|
|
xhci_free_container_ctx(xhci, command->in_ctx);
|
2009-11-21 11:51:47 +00:00
|
|
|
kfree(command);
|
2009-09-04 17:53:13 +00:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
init_completion(command->completion);
|
|
|
|
}
|
|
|
|
|
|
|
|
command->status = 0;
|
|
|
|
INIT_LIST_HEAD(&command->cmd_list);
|
|
|
|
return command;
|
|
|
|
}
|
|
|
|
|
|
|
|
void xhci_free_command(struct xhci_hcd *xhci,
|
|
|
|
struct xhci_command *command)
|
|
|
|
{
|
|
|
|
xhci_free_container_ctx(xhci,
|
|
|
|
command->in_ctx);
|
|
|
|
kfree(command->completion);
|
|
|
|
kfree(command);
|
|
|
|
}
|
|
|
|
|
2009-04-28 02:52:28 +00:00
|
|
|
void xhci_mem_cleanup(struct xhci_hcd *xhci)
|
|
|
|
{
|
2009-04-28 02:52:34 +00:00
|
|
|
struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
|
|
|
|
int size;
|
2009-04-28 02:57:38 +00:00
|
|
|
int i;
|
2009-04-28 02:52:34 +00:00
|
|
|
|
|
|
|
/* Free the Event Ring Segment Table and the actual Event Ring */
|
2009-11-04 06:02:22 +00:00
|
|
|
if (xhci->ir_set) {
|
|
|
|
xhci_writel(xhci, 0, &xhci->ir_set->erst_size);
|
|
|
|
xhci_write_64(xhci, 0, &xhci->ir_set->erst_base);
|
|
|
|
xhci_write_64(xhci, 0, &xhci->ir_set->erst_dequeue);
|
|
|
|
}
|
2009-04-28 02:52:34 +00:00
|
|
|
size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
|
|
|
|
if (xhci->erst.entries)
|
|
|
|
pci_free_consistent(pdev, size,
|
|
|
|
xhci->erst.entries, xhci->erst.erst_dma_addr);
|
|
|
|
xhci->erst.entries = NULL;
|
|
|
|
xhci_dbg(xhci, "Freed ERST\n");
|
|
|
|
if (xhci->event_ring)
|
|
|
|
xhci_ring_free(xhci, xhci->event_ring);
|
|
|
|
xhci->event_ring = NULL;
|
|
|
|
xhci_dbg(xhci, "Freed event ring\n");
|
|
|
|
|
2009-07-27 19:03:31 +00:00
|
|
|
xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
|
2009-04-28 02:52:34 +00:00
|
|
|
if (xhci->cmd_ring)
|
|
|
|
xhci_ring_free(xhci, xhci->cmd_ring);
|
|
|
|
xhci->cmd_ring = NULL;
|
|
|
|
xhci_dbg(xhci, "Freed command ring\n");
|
2009-04-28 02:57:38 +00:00
|
|
|
|
|
|
|
for (i = 1; i < MAX_HC_SLOTS; ++i)
|
|
|
|
xhci_free_virt_device(xhci, i);
|
|
|
|
|
2009-04-28 02:52:34 +00:00
|
|
|
if (xhci->segment_pool)
|
|
|
|
dma_pool_destroy(xhci->segment_pool);
|
|
|
|
xhci->segment_pool = NULL;
|
|
|
|
xhci_dbg(xhci, "Freed segment pool\n");
|
2009-04-28 02:57:38 +00:00
|
|
|
|
|
|
|
if (xhci->device_pool)
|
|
|
|
dma_pool_destroy(xhci->device_pool);
|
|
|
|
xhci->device_pool = NULL;
|
|
|
|
xhci_dbg(xhci, "Freed device context pool\n");
|
|
|
|
|
2009-07-27 19:03:31 +00:00
|
|
|
xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
|
2009-04-28 02:53:42 +00:00
|
|
|
if (xhci->dcbaa)
|
|
|
|
pci_free_consistent(pdev, sizeof(*xhci->dcbaa),
|
|
|
|
xhci->dcbaa, xhci->dcbaa->dma);
|
|
|
|
xhci->dcbaa = NULL;
|
2009-04-28 02:57:38 +00:00
|
|
|
|
2009-11-04 19:22:19 +00:00
|
|
|
scratchpad_free(xhci);
|
2009-04-28 02:52:28 +00:00
|
|
|
xhci->page_size = 0;
|
|
|
|
xhci->page_shift = 0;
|
|
|
|
}
|
|
|
|
|
2009-11-09 21:35:23 +00:00
|
|
|
static int xhci_test_trb_in_td(struct xhci_hcd *xhci,
|
|
|
|
struct xhci_segment *input_seg,
|
|
|
|
union xhci_trb *start_trb,
|
|
|
|
union xhci_trb *end_trb,
|
|
|
|
dma_addr_t input_dma,
|
|
|
|
struct xhci_segment *result_seg,
|
|
|
|
char *test_name, int test_number)
|
|
|
|
{
|
|
|
|
unsigned long long start_dma;
|
|
|
|
unsigned long long end_dma;
|
|
|
|
struct xhci_segment *seg;
|
|
|
|
|
|
|
|
start_dma = xhci_trb_virt_to_dma(input_seg, start_trb);
|
|
|
|
end_dma = xhci_trb_virt_to_dma(input_seg, end_trb);
|
|
|
|
|
|
|
|
seg = trb_in_td(input_seg, start_trb, end_trb, input_dma);
|
|
|
|
if (seg != result_seg) {
|
|
|
|
xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n",
|
|
|
|
test_name, test_number);
|
|
|
|
xhci_warn(xhci, "Tested TRB math w/ seg %p and "
|
|
|
|
"input DMA 0x%llx\n",
|
|
|
|
input_seg,
|
|
|
|
(unsigned long long) input_dma);
|
|
|
|
xhci_warn(xhci, "starting TRB %p (0x%llx DMA), "
|
|
|
|
"ending TRB %p (0x%llx DMA)\n",
|
|
|
|
start_trb, start_dma,
|
|
|
|
end_trb, end_dma);
|
|
|
|
xhci_warn(xhci, "Expected seg %p, got seg %p\n",
|
|
|
|
result_seg, seg);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
|
|
|
|
static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci, gfp_t mem_flags)
|
|
|
|
{
|
|
|
|
struct {
|
|
|
|
dma_addr_t input_dma;
|
|
|
|
struct xhci_segment *result_seg;
|
|
|
|
} simple_test_vector [] = {
|
|
|
|
/* A zeroed DMA field should fail */
|
|
|
|
{ 0, NULL },
|
|
|
|
/* One TRB before the ring start should fail */
|
|
|
|
{ xhci->event_ring->first_seg->dma - 16, NULL },
|
|
|
|
/* One byte before the ring start should fail */
|
|
|
|
{ xhci->event_ring->first_seg->dma - 1, NULL },
|
|
|
|
/* Starting TRB should succeed */
|
|
|
|
{ xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg },
|
|
|
|
/* Ending TRB should succeed */
|
|
|
|
{ xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16,
|
|
|
|
xhci->event_ring->first_seg },
|
|
|
|
/* One byte after the ring end should fail */
|
|
|
|
{ xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL },
|
|
|
|
/* One TRB after the ring end should fail */
|
|
|
|
{ xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL },
|
|
|
|
/* An address of all ones should fail */
|
|
|
|
{ (dma_addr_t) (~0), NULL },
|
|
|
|
};
|
|
|
|
struct {
|
|
|
|
struct xhci_segment *input_seg;
|
|
|
|
union xhci_trb *start_trb;
|
|
|
|
union xhci_trb *end_trb;
|
|
|
|
dma_addr_t input_dma;
|
|
|
|
struct xhci_segment *result_seg;
|
|
|
|
} complex_test_vector [] = {
|
|
|
|
/* Test feeding a valid DMA address from a different ring */
|
|
|
|
{ .input_seg = xhci->event_ring->first_seg,
|
|
|
|
.start_trb = xhci->event_ring->first_seg->trbs,
|
|
|
|
.end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
|
|
|
|
.input_dma = xhci->cmd_ring->first_seg->dma,
|
|
|
|
.result_seg = NULL,
|
|
|
|
},
|
|
|
|
/* Test feeding a valid end TRB from a different ring */
|
|
|
|
{ .input_seg = xhci->event_ring->first_seg,
|
|
|
|
.start_trb = xhci->event_ring->first_seg->trbs,
|
|
|
|
.end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
|
|
|
|
.input_dma = xhci->cmd_ring->first_seg->dma,
|
|
|
|
.result_seg = NULL,
|
|
|
|
},
|
|
|
|
/* Test feeding a valid start and end TRB from a different ring */
|
|
|
|
{ .input_seg = xhci->event_ring->first_seg,
|
|
|
|
.start_trb = xhci->cmd_ring->first_seg->trbs,
|
|
|
|
.end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
|
|
|
|
.input_dma = xhci->cmd_ring->first_seg->dma,
|
|
|
|
.result_seg = NULL,
|
|
|
|
},
|
|
|
|
/* TRB in this ring, but after this TD */
|
|
|
|
{ .input_seg = xhci->event_ring->first_seg,
|
|
|
|
.start_trb = &xhci->event_ring->first_seg->trbs[0],
|
|
|
|
.end_trb = &xhci->event_ring->first_seg->trbs[3],
|
|
|
|
.input_dma = xhci->event_ring->first_seg->dma + 4*16,
|
|
|
|
.result_seg = NULL,
|
|
|
|
},
|
|
|
|
/* TRB in this ring, but before this TD */
|
|
|
|
{ .input_seg = xhci->event_ring->first_seg,
|
|
|
|
.start_trb = &xhci->event_ring->first_seg->trbs[3],
|
|
|
|
.end_trb = &xhci->event_ring->first_seg->trbs[6],
|
|
|
|
.input_dma = xhci->event_ring->first_seg->dma + 2*16,
|
|
|
|
.result_seg = NULL,
|
|
|
|
},
|
|
|
|
/* TRB in this ring, but after this wrapped TD */
|
|
|
|
{ .input_seg = xhci->event_ring->first_seg,
|
|
|
|
.start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
|
|
|
|
.end_trb = &xhci->event_ring->first_seg->trbs[1],
|
|
|
|
.input_dma = xhci->event_ring->first_seg->dma + 2*16,
|
|
|
|
.result_seg = NULL,
|
|
|
|
},
|
|
|
|
/* TRB in this ring, but before this wrapped TD */
|
|
|
|
{ .input_seg = xhci->event_ring->first_seg,
|
|
|
|
.start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
|
|
|
|
.end_trb = &xhci->event_ring->first_seg->trbs[1],
|
|
|
|
.input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16,
|
|
|
|
.result_seg = NULL,
|
|
|
|
},
|
|
|
|
/* TRB not in this ring, and we have a wrapped TD */
|
|
|
|
{ .input_seg = xhci->event_ring->first_seg,
|
|
|
|
.start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
|
|
|
|
.end_trb = &xhci->event_ring->first_seg->trbs[1],
|
|
|
|
.input_dma = xhci->cmd_ring->first_seg->dma + 2*16,
|
|
|
|
.result_seg = NULL,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
unsigned int num_tests;
|
|
|
|
int i, ret;
|
|
|
|
|
|
|
|
num_tests = sizeof(simple_test_vector) / sizeof(simple_test_vector[0]);
|
|
|
|
for (i = 0; i < num_tests; i++) {
|
|
|
|
ret = xhci_test_trb_in_td(xhci,
|
|
|
|
xhci->event_ring->first_seg,
|
|
|
|
xhci->event_ring->first_seg->trbs,
|
|
|
|
&xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
|
|
|
|
simple_test_vector[i].input_dma,
|
|
|
|
simple_test_vector[i].result_seg,
|
|
|
|
"Simple", i);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
num_tests = sizeof(complex_test_vector) / sizeof(complex_test_vector[0]);
|
|
|
|
for (i = 0; i < num_tests; i++) {
|
|
|
|
ret = xhci_test_trb_in_td(xhci,
|
|
|
|
complex_test_vector[i].input_seg,
|
|
|
|
complex_test_vector[i].start_trb,
|
|
|
|
complex_test_vector[i].end_trb,
|
|
|
|
complex_test_vector[i].input_dma,
|
|
|
|
complex_test_vector[i].result_seg,
|
|
|
|
"Complex", i);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
xhci_dbg(xhci, "TRB math tests passed.\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2009-04-28 02:52:28 +00:00
|
|
|
int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
|
|
|
|
{
|
2009-04-28 02:52:34 +00:00
|
|
|
dma_addr_t dma;
|
|
|
|
struct device *dev = xhci_to_hcd(xhci)->self.controller;
|
2009-04-28 02:52:28 +00:00
|
|
|
unsigned int val, val2;
|
2009-07-27 19:03:31 +00:00
|
|
|
u64 val_64;
|
2009-04-28 02:52:34 +00:00
|
|
|
struct xhci_segment *seg;
|
2009-04-28 02:52:28 +00:00
|
|
|
u32 page_size;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
page_size = xhci_readl(xhci, &xhci->op_regs->page_size);
|
|
|
|
xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size);
|
|
|
|
for (i = 0; i < 16; i++) {
|
|
|
|
if ((0x1 & page_size) != 0)
|
|
|
|
break;
|
|
|
|
page_size = page_size >> 1;
|
|
|
|
}
|
|
|
|
if (i < 16)
|
|
|
|
xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024);
|
|
|
|
else
|
|
|
|
xhci_warn(xhci, "WARN: no supported page size\n");
|
|
|
|
/* Use 4K pages, since that's common and the minimum the HC supports */
|
|
|
|
xhci->page_shift = 12;
|
|
|
|
xhci->page_size = 1 << xhci->page_shift;
|
|
|
|
xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Program the Number of Device Slots Enabled field in the CONFIG
|
|
|
|
* register with the max value of slots the HC can handle.
|
|
|
|
*/
|
|
|
|
val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1));
|
|
|
|
xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n",
|
|
|
|
(unsigned int) val);
|
|
|
|
val2 = xhci_readl(xhci, &xhci->op_regs->config_reg);
|
|
|
|
val |= (val2 & ~HCS_SLOTS_MASK);
|
|
|
|
xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n",
|
|
|
|
(unsigned int) val);
|
|
|
|
xhci_writel(xhci, val, &xhci->op_regs->config_reg);
|
|
|
|
|
2009-04-28 02:53:42 +00:00
|
|
|
/*
|
|
|
|
* Section 5.4.8 - doorbell array must be
|
|
|
|
* "physically contiguous and 64-byte (cache line) aligned".
|
|
|
|
*/
|
|
|
|
xhci->dcbaa = pci_alloc_consistent(to_pci_dev(dev),
|
|
|
|
sizeof(*xhci->dcbaa), &dma);
|
|
|
|
if (!xhci->dcbaa)
|
|
|
|
goto fail;
|
|
|
|
memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
|
|
|
|
xhci->dcbaa->dma = dma;
|
2009-04-30 02:14:08 +00:00
|
|
|
xhci_dbg(xhci, "// Device context base array address = 0x%llx (DMA), %p (virt)\n",
|
|
|
|
(unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
|
2009-07-27 19:03:31 +00:00
|
|
|
xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
|
2009-04-28 02:53:42 +00:00
|
|
|
|
2009-04-28 02:52:34 +00:00
|
|
|
/*
|
|
|
|
* Initialize the ring segment pool. The ring must be a contiguous
|
|
|
|
* structure comprised of TRBs. The TRBs must be 16 byte aligned,
|
|
|
|
* however, the command ring segment needs 64-byte aligned segments,
|
|
|
|
* so we pick the greater alignment need.
|
|
|
|
*/
|
|
|
|
xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
|
|
|
|
SEGMENT_SIZE, 64, xhci->page_size);
|
2009-07-27 19:05:15 +00:00
|
|
|
|
2009-04-28 02:57:38 +00:00
|
|
|
/* See Table 46 and Note on Figure 55 */
|
|
|
|
xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
|
2009-07-27 19:05:15 +00:00
|
|
|
2112, 64, xhci->page_size);
|
2009-04-28 02:57:38 +00:00
|
|
|
if (!xhci->segment_pool || !xhci->device_pool)
|
2009-04-28 02:52:34 +00:00
|
|
|
goto fail;
|
|
|
|
|
|
|
|
/* Set up the command ring to have one segments for now. */
|
|
|
|
xhci->cmd_ring = xhci_ring_alloc(xhci, 1, true, flags);
|
|
|
|
if (!xhci->cmd_ring)
|
|
|
|
goto fail;
|
2009-04-30 02:14:08 +00:00
|
|
|
xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring);
|
|
|
|
xhci_dbg(xhci, "First segment DMA is 0x%llx\n",
|
|
|
|
(unsigned long long)xhci->cmd_ring->first_seg->dma);
|
2009-04-28 02:52:34 +00:00
|
|
|
|
|
|
|
/* Set the address in the Command Ring Control register */
|
2009-07-27 19:03:31 +00:00
|
|
|
val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
|
|
|
|
val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
|
|
|
|
(xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
|
2009-04-28 02:52:34 +00:00
|
|
|
xhci->cmd_ring->cycle_state;
|
2009-07-27 19:03:31 +00:00
|
|
|
xhci_dbg(xhci, "// Setting command ring address to 0x%x\n", val);
|
|
|
|
xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
|
2009-04-28 02:52:34 +00:00
|
|
|
xhci_dbg_cmd_ptrs(xhci);
|
|
|
|
|
|
|
|
val = xhci_readl(xhci, &xhci->cap_regs->db_off);
|
|
|
|
val &= DBOFF_MASK;
|
|
|
|
xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x"
|
|
|
|
" from cap regs base addr\n", val);
|
|
|
|
xhci->dba = (void *) xhci->cap_regs + val;
|
|
|
|
xhci_dbg_regs(xhci);
|
|
|
|
xhci_print_run_regs(xhci);
|
|
|
|
/* Set ir_set to interrupt register set 0 */
|
|
|
|
xhci->ir_set = (void *) xhci->run_regs->ir_set;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Event ring setup: Allocate a normal ring, but also setup
|
|
|
|
* the event ring segment table (ERST). Section 4.9.3.
|
|
|
|
*/
|
|
|
|
xhci_dbg(xhci, "// Allocating event ring\n");
|
|
|
|
xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, false, flags);
|
|
|
|
if (!xhci->event_ring)
|
|
|
|
goto fail;
|
2009-11-09 21:35:23 +00:00
|
|
|
if (xhci_check_trb_in_td_math(xhci, flags) < 0)
|
|
|
|
goto fail;
|
2009-04-28 02:52:34 +00:00
|
|
|
|
|
|
|
xhci->erst.entries = pci_alloc_consistent(to_pci_dev(dev),
|
|
|
|
sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS, &dma);
|
|
|
|
if (!xhci->erst.entries)
|
|
|
|
goto fail;
|
2009-04-30 02:14:08 +00:00
|
|
|
xhci_dbg(xhci, "// Allocated event ring segment table at 0x%llx\n",
|
|
|
|
(unsigned long long)dma);
|
2009-04-28 02:52:34 +00:00
|
|
|
|
|
|
|
memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
|
|
|
|
xhci->erst.num_entries = ERST_NUM_SEGS;
|
|
|
|
xhci->erst.erst_dma_addr = dma;
|
2009-04-30 02:14:08 +00:00
|
|
|
xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n",
|
2009-04-28 02:52:34 +00:00
|
|
|
xhci->erst.num_entries,
|
2009-04-30 02:14:08 +00:00
|
|
|
xhci->erst.entries,
|
|
|
|
(unsigned long long)xhci->erst.erst_dma_addr);
|
2009-04-28 02:52:34 +00:00
|
|
|
|
|
|
|
/* set ring base address and size for each segment table entry */
|
|
|
|
for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
|
|
|
|
struct xhci_erst_entry *entry = &xhci->erst.entries[val];
|
2009-07-27 19:03:31 +00:00
|
|
|
entry->seg_addr = seg->dma;
|
2009-04-28 02:52:34 +00:00
|
|
|
entry->seg_size = TRBS_PER_SEGMENT;
|
|
|
|
entry->rsvd = 0;
|
|
|
|
seg = seg->next;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* set ERST count with the number of entries in the segment table */
|
|
|
|
val = xhci_readl(xhci, &xhci->ir_set->erst_size);
|
|
|
|
val &= ERST_SIZE_MASK;
|
|
|
|
val |= ERST_NUM_SEGS;
|
|
|
|
xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
|
|
|
|
val);
|
|
|
|
xhci_writel(xhci, val, &xhci->ir_set->erst_size);
|
|
|
|
|
|
|
|
xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n");
|
|
|
|
/* set the segment table base address */
|
2009-04-30 02:14:08 +00:00
|
|
|
xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%llx\n",
|
|
|
|
(unsigned long long)xhci->erst.erst_dma_addr);
|
2009-07-27 19:03:31 +00:00
|
|
|
val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
|
|
|
|
val_64 &= ERST_PTR_MASK;
|
|
|
|
val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
|
|
|
|
xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
|
2009-04-28 02:52:34 +00:00
|
|
|
|
|
|
|
/* Set the event ring dequeue address */
|
2009-04-30 02:05:20 +00:00
|
|
|
xhci_set_hc_event_deq(xhci);
|
2009-04-28 02:52:34 +00:00
|
|
|
xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n");
|
|
|
|
xhci_print_ir_set(xhci, xhci->ir_set, 0);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* XXX: Might need to set the Interrupter Moderation Register to
|
|
|
|
* something other than the default (~1ms minimum between interrupts).
|
|
|
|
* See section 5.5.1.2.
|
|
|
|
*/
|
2009-04-28 02:57:38 +00:00
|
|
|
init_completion(&xhci->addr_dev);
|
|
|
|
for (i = 0; i < MAX_HC_SLOTS; ++i)
|
|
|
|
xhci->devs[i] = 0;
|
2009-04-28 02:52:28 +00:00
|
|
|
|
2009-07-27 19:05:03 +00:00
|
|
|
if (scratchpad_alloc(xhci, flags))
|
|
|
|
goto fail;
|
|
|
|
|
2009-04-28 02:52:28 +00:00
|
|
|
return 0;
|
2009-07-27 19:05:03 +00:00
|
|
|
|
2009-04-28 02:52:28 +00:00
|
|
|
fail:
|
|
|
|
xhci_warn(xhci, "Couldn't initialize memory\n");
|
|
|
|
xhci_mem_cleanup(xhci);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|