blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 21:50:22 +00:00
|
|
|
/*
|
2009-09-24 14:11:24 +00:00
|
|
|
* Copyright 2007-2009 Analog Devices Inc.
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 21:50:22 +00:00
|
|
|
*
|
2009-09-24 14:11:24 +00:00
|
|
|
* Licensed under the GPL-2 or later.
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 21:50:22 +00:00
|
|
|
*/
|
|
|
|
|
|
2008-05-07 03:41:26 +00:00
|
|
|
/*
|
|
|
|
|
* NOTE! The single-stepping code assumes that all interrupt handlers
|
|
|
|
|
* start by saving SYSCFG on the stack with their first instruction.
|
|
|
|
|
*/
|
|
|
|
|
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 21:50:22 +00:00
|
|
|
/*
|
|
|
|
|
* Code to save processor context.
|
|
|
|
|
* We even save the register which are preserved by a function call
|
|
|
|
|
* - r4, r5, r6, r7, p3, p4, p5
|
|
|
|
|
*/
|
|
|
|
|
.macro save_context_with_interrupts
|
|
|
|
|
[--sp] = SYSCFG;
|
|
|
|
|
|
|
|
|
|
[--sp] = P0; /*orig_p0*/
|
|
|
|
|
[--sp] = R0; /*orig_r0*/
|
|
|
|
|
|
|
|
|
|
[--sp] = ( R7:0, P5:0 );
|
|
|
|
|
[--sp] = fp;
|
|
|
|
|
[--sp] = usp;
|
|
|
|
|
|
|
|
|
|
[--sp] = i0;
|
|
|
|
|
[--sp] = i1;
|
|
|
|
|
[--sp] = i2;
|
|
|
|
|
[--sp] = i3;
|
|
|
|
|
|
|
|
|
|
[--sp] = m0;
|
|
|
|
|
[--sp] = m1;
|
|
|
|
|
[--sp] = m2;
|
|
|
|
|
[--sp] = m3;
|
|
|
|
|
|
|
|
|
|
[--sp] = l0;
|
|
|
|
|
[--sp] = l1;
|
|
|
|
|
[--sp] = l2;
|
|
|
|
|
[--sp] = l3;
|
|
|
|
|
|
|
|
|
|
[--sp] = b0;
|
|
|
|
|
[--sp] = b1;
|
|
|
|
|
[--sp] = b2;
|
|
|
|
|
[--sp] = b3;
|
|
|
|
|
[--sp] = a0.x;
|
|
|
|
|
[--sp] = a0.w;
|
|
|
|
|
[--sp] = a1.x;
|
|
|
|
|
[--sp] = a1.w;
|
|
|
|
|
|
|
|
|
|
[--sp] = LC0;
|
|
|
|
|
[--sp] = LC1;
|
|
|
|
|
[--sp] = LT0;
|
|
|
|
|
[--sp] = LT1;
|
|
|
|
|
[--sp] = LB0;
|
|
|
|
|
[--sp] = LB1;
|
|
|
|
|
|
|
|
|
|
[--sp] = ASTAT;
|
|
|
|
|
|
|
|
|
|
[--sp] = r0; /* Skip reserved */
|
|
|
|
|
[--sp] = RETS;
|
|
|
|
|
r0 = RETI;
|
|
|
|
|
[--sp] = r0;
|
|
|
|
|
[--sp] = RETX;
|
|
|
|
|
[--sp] = RETN;
|
|
|
|
|
[--sp] = RETE;
|
|
|
|
|
[--sp] = SEQSTAT;
|
|
|
|
|
[--sp] = r0; /* Skip IPEND as well. */
|
|
|
|
|
/* Switch to other method of keeping interrupts disabled. */
|
|
|
|
|
#ifdef CONFIG_DEBUG_HWERR
|
|
|
|
|
r0 = 0x3f;
|
|
|
|
|
sti r0;
|
|
|
|
|
#else
|
|
|
|
|
cli r0;
|
2010-01-19 04:35:28 +00:00
|
|
|
#endif
|
|
|
|
|
#ifdef CONFIG_TRACE_IRQFLAGS
|
|
|
|
|
sp += -12;
|
|
|
|
|
call _trace_hardirqs_off;
|
|
|
|
|
sp += 12;
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 21:50:22 +00:00
|
|
|
#endif
|
|
|
|
|
[--sp] = RETI; /*orig_pc*/
|
|
|
|
|
/* Clear all L registers. */
|
|
|
|
|
r0 = 0 (x);
|
|
|
|
|
l0 = r0;
|
|
|
|
|
l1 = r0;
|
|
|
|
|
l2 = r0;
|
|
|
|
|
l3 = r0;
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
.macro save_context_syscall
|
|
|
|
|
[--sp] = SYSCFG;
|
|
|
|
|
|
|
|
|
|
[--sp] = P0; /*orig_p0*/
|
|
|
|
|
[--sp] = R0; /*orig_r0*/
|
|
|
|
|
[--sp] = ( R7:0, P5:0 );
|
|
|
|
|
[--sp] = fp;
|
|
|
|
|
[--sp] = usp;
|
|
|
|
|
|
|
|
|
|
[--sp] = i0;
|
|
|
|
|
[--sp] = i1;
|
|
|
|
|
[--sp] = i2;
|
|
|
|
|
[--sp] = i3;
|
|
|
|
|
|
|
|
|
|
[--sp] = m0;
|
|
|
|
|
[--sp] = m1;
|
|
|
|
|
[--sp] = m2;
|
|
|
|
|
[--sp] = m3;
|
|
|
|
|
|
|
|
|
|
[--sp] = l0;
|
|
|
|
|
[--sp] = l1;
|
|
|
|
|
[--sp] = l2;
|
|
|
|
|
[--sp] = l3;
|
|
|
|
|
|
|
|
|
|
[--sp] = b0;
|
|
|
|
|
[--sp] = b1;
|
|
|
|
|
[--sp] = b2;
|
|
|
|
|
[--sp] = b3;
|
|
|
|
|
[--sp] = a0.x;
|
|
|
|
|
[--sp] = a0.w;
|
|
|
|
|
[--sp] = a1.x;
|
|
|
|
|
[--sp] = a1.w;
|
|
|
|
|
|
|
|
|
|
[--sp] = LC0;
|
|
|
|
|
[--sp] = LC1;
|
|
|
|
|
[--sp] = LT0;
|
|
|
|
|
[--sp] = LT1;
|
|
|
|
|
[--sp] = LB0;
|
|
|
|
|
[--sp] = LB1;
|
|
|
|
|
|
|
|
|
|
[--sp] = ASTAT;
|
|
|
|
|
|
|
|
|
|
[--sp] = r0; /* Skip reserved */
|
|
|
|
|
[--sp] = RETS;
|
|
|
|
|
r0 = RETI;
|
|
|
|
|
[--sp] = r0;
|
|
|
|
|
[--sp] = RETX;
|
|
|
|
|
[--sp] = RETN;
|
|
|
|
|
[--sp] = RETE;
|
|
|
|
|
[--sp] = SEQSTAT;
|
|
|
|
|
[--sp] = r0; /* Skip IPEND as well. */
|
|
|
|
|
[--sp] = RETI; /*orig_pc*/
|
|
|
|
|
/* Clear all L registers. */
|
|
|
|
|
r0 = 0 (x);
|
|
|
|
|
l0 = r0;
|
|
|
|
|
l1 = r0;
|
|
|
|
|
l2 = r0;
|
|
|
|
|
l3 = r0;
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
.macro save_context_no_interrupts
|
|
|
|
|
[--sp] = SYSCFG;
|
|
|
|
|
[--sp] = P0; /* orig_p0 */
|
|
|
|
|
[--sp] = R0; /* orig_r0 */
|
|
|
|
|
[--sp] = ( R7:0, P5:0 );
|
|
|
|
|
[--sp] = fp;
|
|
|
|
|
[--sp] = usp;
|
|
|
|
|
|
|
|
|
|
[--sp] = i0;
|
|
|
|
|
[--sp] = i1;
|
|
|
|
|
[--sp] = i2;
|
|
|
|
|
[--sp] = i3;
|
|
|
|
|
|
|
|
|
|
[--sp] = m0;
|
|
|
|
|
[--sp] = m1;
|
|
|
|
|
[--sp] = m2;
|
|
|
|
|
[--sp] = m3;
|
|
|
|
|
|
|
|
|
|
[--sp] = l0;
|
|
|
|
|
[--sp] = l1;
|
|
|
|
|
[--sp] = l2;
|
|
|
|
|
[--sp] = l3;
|
|
|
|
|
|
|
|
|
|
[--sp] = b0;
|
|
|
|
|
[--sp] = b1;
|
|
|
|
|
[--sp] = b2;
|
|
|
|
|
[--sp] = b3;
|
|
|
|
|
[--sp] = a0.x;
|
|
|
|
|
[--sp] = a0.w;
|
|
|
|
|
[--sp] = a1.x;
|
|
|
|
|
[--sp] = a1.w;
|
|
|
|
|
|
|
|
|
|
[--sp] = LC0;
|
|
|
|
|
[--sp] = LC1;
|
|
|
|
|
[--sp] = LT0;
|
|
|
|
|
[--sp] = LT1;
|
|
|
|
|
[--sp] = LB0;
|
|
|
|
|
[--sp] = LB1;
|
|
|
|
|
|
|
|
|
|
[--sp] = ASTAT;
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_KGDB
|
|
|
|
|
fp = 0(Z);
|
|
|
|
|
r1 = sp;
|
|
|
|
|
r1 += 60;
|
|
|
|
|
r1 += 60;
|
|
|
|
|
r1 += 60;
|
|
|
|
|
[--sp] = r1;
|
|
|
|
|
#else
|
|
|
|
|
[--sp] = r0; /* Skip reserved */
|
|
|
|
|
#endif
|
|
|
|
|
[--sp] = RETS;
|
|
|
|
|
r0 = RETI;
|
|
|
|
|
[--sp] = r0;
|
|
|
|
|
[--sp] = RETX;
|
|
|
|
|
[--sp] = RETN;
|
|
|
|
|
[--sp] = RETE;
|
|
|
|
|
[--sp] = SEQSTAT;
|
2009-07-07 02:47:14 +00:00
|
|
|
#ifdef CONFIG_DEBUG_KERNEL
|
|
|
|
|
p1.l = lo(IPEND);
|
|
|
|
|
p1.h = hi(IPEND);
|
|
|
|
|
r1 = [p1];
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 21:50:22 +00:00
|
|
|
[--sp] = r1;
|
|
|
|
|
#else
|
|
|
|
|
[--sp] = r0; /* Skip IPEND as well. */
|
|
|
|
|
#endif
|
|
|
|
|
[--sp] = r0; /*orig_pc*/
|
|
|
|
|
/* Clear all L registers. */
|
|
|
|
|
r0 = 0 (x);
|
|
|
|
|
l0 = r0;
|
|
|
|
|
l1 = r0;
|
|
|
|
|
l2 = r0;
|
|
|
|
|
l3 = r0;
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
.macro restore_context_no_interrupts
|
|
|
|
|
sp += 4; /* Skip orig_pc */
|
|
|
|
|
sp += 4; /* Skip IPEND */
|
|
|
|
|
SEQSTAT = [sp++];
|
|
|
|
|
RETE = [sp++];
|
|
|
|
|
RETN = [sp++];
|
|
|
|
|
RETX = [sp++];
|
|
|
|
|
r0 = [sp++];
|
|
|
|
|
RETI = r0; /* Restore RETI indirectly when in exception */
|
|
|
|
|
RETS = [sp++];
|
|
|
|
|
|
|
|
|
|
sp += 4; /* Skip Reserved */
|
|
|
|
|
|
|
|
|
|
ASTAT = [sp++];
|
|
|
|
|
|
|
|
|
|
LB1 = [sp++];
|
|
|
|
|
LB0 = [sp++];
|
|
|
|
|
LT1 = [sp++];
|
|
|
|
|
LT0 = [sp++];
|
|
|
|
|
LC1 = [sp++];
|
|
|
|
|
LC0 = [sp++];
|
|
|
|
|
|
|
|
|
|
a1.w = [sp++];
|
|
|
|
|
a1.x = [sp++];
|
|
|
|
|
a0.w = [sp++];
|
|
|
|
|
a0.x = [sp++];
|
|
|
|
|
b3 = [sp++];
|
|
|
|
|
b2 = [sp++];
|
|
|
|
|
b1 = [sp++];
|
|
|
|
|
b0 = [sp++];
|
|
|
|
|
|
|
|
|
|
l3 = [sp++];
|
|
|
|
|
l2 = [sp++];
|
|
|
|
|
l1 = [sp++];
|
|
|
|
|
l0 = [sp++];
|
|
|
|
|
|
|
|
|
|
m3 = [sp++];
|
|
|
|
|
m2 = [sp++];
|
|
|
|
|
m1 = [sp++];
|
|
|
|
|
m0 = [sp++];
|
|
|
|
|
|
|
|
|
|
i3 = [sp++];
|
|
|
|
|
i2 = [sp++];
|
|
|
|
|
i1 = [sp++];
|
|
|
|
|
i0 = [sp++];
|
|
|
|
|
|
|
|
|
|
sp += 4;
|
|
|
|
|
fp = [sp++];
|
|
|
|
|
|
|
|
|
|
( R7 : 0, P5 : 0) = [ SP ++ ];
|
|
|
|
|
sp += 8; /* Skip orig_r0/orig_p0 */
|
|
|
|
|
SYSCFG = [sp++];
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
.macro restore_context_with_interrupts
|
|
|
|
|
sp += 4; /* Skip orig_pc */
|
|
|
|
|
sp += 4; /* Skip IPEND */
|
|
|
|
|
SEQSTAT = [sp++];
|
|
|
|
|
RETE = [sp++];
|
|
|
|
|
RETN = [sp++];
|
|
|
|
|
RETX = [sp++];
|
|
|
|
|
RETI = [sp++];
|
2010-01-19 04:35:28 +00:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_TRACE_IRQFLAGS
|
|
|
|
|
sp += -12;
|
|
|
|
|
call _trace_hardirqs_on;
|
|
|
|
|
sp += 12;
|
|
|
|
|
#endif
|
|
|
|
|
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 21:50:22 +00:00
|
|
|
RETS = [sp++];
|
|
|
|
|
|
2009-01-07 15:14:39 +00:00
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
|
GET_PDA(p0, r0);
|
|
|
|
|
r0 = [p0 + PDA_IRQFLAGS];
|
|
|
|
|
#else
|
2008-11-18 09:48:22 +00:00
|
|
|
p0.h = _bfin_irq_flags;
|
|
|
|
|
p0.l = _bfin_irq_flags;
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 21:50:22 +00:00
|
|
|
r0 = [p0];
|
2009-01-07 15:14:39 +00:00
|
|
|
#endif
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 21:50:22 +00:00
|
|
|
sti r0;
|
|
|
|
|
|
|
|
|
|
sp += 4; /* Skip Reserved */
|
|
|
|
|
|
|
|
|
|
ASTAT = [sp++];
|
|
|
|
|
|
|
|
|
|
LB1 = [sp++];
|
|
|
|
|
LB0 = [sp++];
|
|
|
|
|
LT1 = [sp++];
|
|
|
|
|
LT0 = [sp++];
|
|
|
|
|
LC1 = [sp++];
|
|
|
|
|
LC0 = [sp++];
|
|
|
|
|
|
|
|
|
|
a1.w = [sp++];
|
|
|
|
|
a1.x = [sp++];
|
|
|
|
|
a0.w = [sp++];
|
|
|
|
|
a0.x = [sp++];
|
|
|
|
|
b3 = [sp++];
|
|
|
|
|
b2 = [sp++];
|
|
|
|
|
b1 = [sp++];
|
|
|
|
|
b0 = [sp++];
|
|
|
|
|
|
|
|
|
|
l3 = [sp++];
|
|
|
|
|
l2 = [sp++];
|
|
|
|
|
l1 = [sp++];
|
|
|
|
|
l0 = [sp++];
|
|
|
|
|
|
|
|
|
|
m3 = [sp++];
|
|
|
|
|
m2 = [sp++];
|
|
|
|
|
m1 = [sp++];
|
|
|
|
|
m0 = [sp++];
|
|
|
|
|
|
|
|
|
|
i3 = [sp++];
|
|
|
|
|
i2 = [sp++];
|
|
|
|
|
i1 = [sp++];
|
|
|
|
|
i0 = [sp++];
|
|
|
|
|
|
|
|
|
|
sp += 4;
|
|
|
|
|
fp = [sp++];
|
|
|
|
|
|
|
|
|
|
( R7 : 0, P5 : 0) = [ SP ++ ];
|
|
|
|
|
sp += 8; /* Skip orig_r0/orig_p0 */
|
|
|
|
|
csync;
|
|
|
|
|
SYSCFG = [sp++];
|
|
|
|
|
csync;
|
|
|
|
|
.endm
|
2009-01-07 15:14:38 +00:00
|
|
|
|
|
|
|
|
.macro save_context_cplb
|
|
|
|
|
[--sp] = (R7:0, P5:0);
|
|
|
|
|
[--sp] = fp;
|
|
|
|
|
|
|
|
|
|
[--sp] = a0.x;
|
|
|
|
|
[--sp] = a0.w;
|
|
|
|
|
[--sp] = a1.x;
|
|
|
|
|
[--sp] = a1.w;
|
|
|
|
|
|
|
|
|
|
[--sp] = LC0;
|
|
|
|
|
[--sp] = LC1;
|
|
|
|
|
[--sp] = LT0;
|
|
|
|
|
[--sp] = LT1;
|
|
|
|
|
[--sp] = LB0;
|
|
|
|
|
[--sp] = LB1;
|
|
|
|
|
|
|
|
|
|
[--sp] = RETS;
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
.macro restore_context_cplb
|
|
|
|
|
RETS = [sp++];
|
|
|
|
|
|
|
|
|
|
LB1 = [sp++];
|
|
|
|
|
LB0 = [sp++];
|
|
|
|
|
LT1 = [sp++];
|
|
|
|
|
LT0 = [sp++];
|
|
|
|
|
LC1 = [sp++];
|
|
|
|
|
LC0 = [sp++];
|
|
|
|
|
|
|
|
|
|
a1.w = [sp++];
|
|
|
|
|
a1.x = [sp++];
|
|
|
|
|
a0.w = [sp++];
|
|
|
|
|
a0.x = [sp++];
|
|
|
|
|
|
|
|
|
|
fp = [sp++];
|
|
|
|
|
|
|
|
|
|
(R7:0, P5:0) = [SP++];
|
|
|
|
|
.endm
|
2010-01-07 04:11:17 +00:00
|
|
|
|
|
|
|
|
.macro pseudo_long_call func:req, scratch:req
|
|
|
|
|
#ifdef CONFIG_ROMKERNEL
|
|
|
|
|
\scratch\().l = \func;
|
|
|
|
|
\scratch\().h = \func;
|
|
|
|
|
call (\scratch);
|
|
|
|
|
#else
|
|
|
|
|
call \func;
|
|
|
|
|
#endif
|
|
|
|
|
.endm
|