2016-06-29 21:05:23 +02:00
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config SUNXI_CCU
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bool "Clock support for Allwinner SoCs"
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2016-09-08 23:28:29 +02:00
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depends on ARCH_SUNXI || COMPILE_TEST
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2017-03-27 11:57:53 +02:00
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select RESET_CONTROLLER
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2016-06-29 21:05:23 +02:00
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default ARCH_SUNXI
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2016-06-29 21:05:24 +02:00
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if SUNXI_CCU
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# Base clock types
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2016-06-29 21:05:28 +02:00
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config SUNXI_CCU_DIV
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bool
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select SUNXI_CCU_MUX
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2016-06-29 21:05:24 +02:00
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config SUNXI_CCU_FRAC
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bool
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2016-06-29 21:05:25 +02:00
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config SUNXI_CCU_GATE
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2017-04-27 13:02:31 +02:00
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def_bool y
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2016-06-29 21:05:25 +02:00
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2016-06-29 21:05:26 +02:00
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config SUNXI_CCU_MUX
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bool
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2016-08-30 10:38:07 +02:00
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config SUNXI_CCU_MULT
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bool
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select SUNXI_CCU_MUX
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2016-06-29 21:05:27 +02:00
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config SUNXI_CCU_PHASE
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bool
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2016-06-29 21:05:29 +02:00
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# Multi-factor clocks
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2016-06-29 21:05:30 +02:00
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config SUNXI_CCU_NK
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bool
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select SUNXI_CCU_GATE
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2016-06-29 21:05:32 +02:00
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config SUNXI_CCU_NKM
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bool
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select SUNXI_CCU_GATE
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2016-06-29 21:05:33 +02:00
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config SUNXI_CCU_NKMP
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bool
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select SUNXI_CCU_GATE
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2016-06-29 21:05:31 +02:00
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config SUNXI_CCU_NM
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bool
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select SUNXI_CCU_FRAC
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select SUNXI_CCU_GATE
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2016-06-29 21:05:29 +02:00
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config SUNXI_CCU_MP
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bool
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select SUNXI_CCU_GATE
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select SUNXI_CCU_MUX
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2016-06-29 21:05:34 +02:00
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# SoC Drivers
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2016-07-06 08:31:34 +02:00
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config SUN50I_A64_CCU
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bool "Support for the Allwinner A64 CCU"
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select SUNXI_CCU_DIV
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select SUNXI_CCU_NK
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select SUNXI_CCU_NKM
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select SUNXI_CCU_NKMP
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select SUNXI_CCU_NM
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select SUNXI_CCU_MP
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select SUNXI_CCU_PHASE
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default ARM64 && ARCH_SUNXI
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2017-03-02 17:43:57 +00:00
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depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
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2016-07-06 08:31:34 +02:00
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2016-10-04 10:09:58 +02:00
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config SUN5I_CCU
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bool "Support for the Allwinner sun5i family CCM"
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select SUNXI_CCU_DIV
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2017-02-02 15:33:57 +01:00
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select SUNXI_CCU_MULT
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2016-10-04 10:09:58 +02:00
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select SUNXI_CCU_NK
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select SUNXI_CCU_NKM
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select SUNXI_CCU_NM
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select SUNXI_CCU_MP
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select SUNXI_CCU_PHASE
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default MACH_SUN5I
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2017-03-02 17:43:57 +00:00
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depends on MACH_SUN5I || COMPILE_TEST
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2016-10-04 10:09:58 +02:00
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2016-08-25 14:21:59 +08:00
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config SUN6I_A31_CCU
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bool "Support for the Allwinner A31/A31s CCU"
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select SUNXI_CCU_DIV
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select SUNXI_CCU_NK
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select SUNXI_CCU_NKM
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2017-02-14 22:29:45 +01:00
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select SUNXI_CCU_NKMP
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2016-08-25 14:21:59 +08:00
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select SUNXI_CCU_NM
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select SUNXI_CCU_MP
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select SUNXI_CCU_PHASE
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default MACH_SUN6I
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2017-03-02 17:43:57 +00:00
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depends on MACH_SUN6I || COMPILE_TEST
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2016-08-25 14:21:59 +08:00
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2016-08-31 16:55:00 +02:00
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config SUN8I_A23_CCU
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bool "Support for the Allwinner A23 CCU"
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select SUNXI_CCU_DIV
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select SUNXI_CCU_MULT
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select SUNXI_CCU_NK
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select SUNXI_CCU_NKM
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select SUNXI_CCU_NKMP
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select SUNXI_CCU_NM
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select SUNXI_CCU_MP
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select SUNXI_CCU_PHASE
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default MACH_SUN8I
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2017-03-02 17:43:57 +00:00
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depends on MACH_SUN8I || COMPILE_TEST
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2016-08-31 16:55:00 +02:00
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2016-08-24 14:10:15 +02:00
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config SUN8I_A33_CCU
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bool "Support for the Allwinner A33 CCU"
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select SUNXI_CCU_DIV
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select SUNXI_CCU_MULT
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select SUNXI_CCU_NK
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select SUNXI_CCU_NKM
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select SUNXI_CCU_NKMP
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select SUNXI_CCU_NM
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select SUNXI_CCU_MP
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select SUNXI_CCU_PHASE
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default MACH_SUN8I
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2017-03-02 17:43:57 +00:00
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depends on MACH_SUN8I || COMPILE_TEST
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2016-08-24 14:10:15 +02:00
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clk: sunxi-ng: Add driver for A83T CCU
The A83T clock control unit is a hybrid of some new style clock designs
from the A80, and old style layout from the other Allwinner SoCs.
Like the A80, the SoC does not have a low speed 32.768 kHz oscillator.
Unlike the A80, there is no clock input either. The only low speed clock
available is the internal oscillator which runs at around 16 MHz,
divided by 512, yielding a low speed clock around 31.250 kHz.
Also, the MMC2 module clock supports switching to a "new timing" mode.
This mode divides the clock output by half, and disables the CCU based
clock delays. The MMC controller must be configure to the same mode,
and then use its internal clock delays.
This driver does not support runtime switching of the timing modes.
Instead, the new timing mode is enforced at probe time. Consumers can
check which mode is active by trying to get the current phase delay
of the MMC2 phase clocks, which will return -ENOTSUPP if the new
timing mode is active.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-05-19 15:06:09 +08:00
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config SUN8I_A83T_CCU
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bool "Support for the Allwinner A83T CCU"
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select SUNXI_CCU_DIV
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select SUNXI_CCU_GATE
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select SUNXI_CCU_MP
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2017-05-22 22:29:40 +02:00
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select SUNXI_CCU_MULT
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clk: sunxi-ng: Add driver for A83T CCU
The A83T clock control unit is a hybrid of some new style clock designs
from the A80, and old style layout from the other Allwinner SoCs.
Like the A80, the SoC does not have a low speed 32.768 kHz oscillator.
Unlike the A80, there is no clock input either. The only low speed clock
available is the internal oscillator which runs at around 16 MHz,
divided by 512, yielding a low speed clock around 31.250 kHz.
Also, the MMC2 module clock supports switching to a "new timing" mode.
This mode divides the clock output by half, and disables the CCU based
clock delays. The MMC controller must be configure to the same mode,
and then use its internal clock delays.
This driver does not support runtime switching of the timing modes.
Instead, the new timing mode is enforced at probe time. Consumers can
check which mode is active by trying to get the current phase delay
of the MMC2 phase clocks, which will return -ENOTSUPP if the new
timing mode is active.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-05-19 15:06:09 +08:00
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select SUNXI_CCU_MUX
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select SUNXI_CCU_NKMP
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select SUNXI_CCU_NM
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select SUNXI_CCU_PHASE
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default MACH_SUN8I
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2016-06-29 21:05:34 +02:00
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config SUN8I_H3_CCU
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bool "Support for the Allwinner H3 CCU"
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select SUNXI_CCU_DIV
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select SUNXI_CCU_NK
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select SUNXI_CCU_NKM
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select SUNXI_CCU_NKMP
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select SUNXI_CCU_NM
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select SUNXI_CCU_MP
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select SUNXI_CCU_PHASE
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2017-03-02 04:13:39 +08:00
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default MACH_SUN8I || (ARM64 && ARCH_SUNXI)
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2017-03-02 17:43:57 +00:00
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depends on MACH_SUN8I || (ARM64 && ARCH_SUNXI) || COMPILE_TEST
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2016-06-29 21:05:34 +02:00
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2017-01-20 01:54:45 +08:00
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config SUN8I_V3S_CCU
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bool "Support for the Allwinner V3s CCU"
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select SUNXI_CCU_DIV
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select SUNXI_CCU_NK
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select SUNXI_CCU_NKM
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select SUNXI_CCU_NKMP
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select SUNXI_CCU_NM
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select SUNXI_CCU_MP
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select SUNXI_CCU_PHASE
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default MACH_SUN8I
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2017-03-02 17:43:57 +00:00
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depends on MACH_SUN8I || COMPILE_TEST
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2017-01-20 01:54:45 +08:00
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2017-05-15 00:30:34 +08:00
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config SUN8I_DE2_CCU
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bool "Support for the Allwinner SoCs DE2 CCU"
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select SUNXI_CCU_DIV
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select SUNXI_CCU_GATE
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|
2017-01-28 20:22:34 +08:00
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config SUN9I_A80_CCU
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bool "Support for the Allwinner A80 CCU"
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select SUNXI_CCU_DIV
|
2017-04-10 14:15:44 +02:00
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select SUNXI_CCU_MULT
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2017-01-28 20:22:34 +08:00
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select SUNXI_CCU_GATE
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select SUNXI_CCU_NKMP
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select SUNXI_CCU_NM
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select SUNXI_CCU_MP
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select SUNXI_CCU_PHASE
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default MACH_SUN9I
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2017-03-02 17:43:57 +00:00
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depends on MACH_SUN9I || COMPILE_TEST
|
2017-01-28 20:22:34 +08:00
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2017-04-04 17:50:57 +08:00
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config SUN8I_R_CCU
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bool "Support for Allwinner SoCs' PRCM CCUs"
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select SUNXI_CCU_DIV
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select SUNXI_CCU_GATE
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2017-05-17 23:19:01 +02:00
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select SUNXI_CCU_MP
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2017-04-04 17:50:57 +08:00
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default MACH_SUN8I || (ARCH_SUNXI && ARM64)
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2017-01-28 20:22:34 +08:00
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2016-06-29 21:05:24 +02:00
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endif
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