2005-04-16 22:20:36 +00:00
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/*
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* Copyright (C) 2000 YAEGASHI Takeshi
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* Hitachi HD64461 companion chip support
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*/
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#include <linux/sched.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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2008-11-28 08:58:30 +00:00
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#include <linux/io.h>
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2005-04-16 22:20:36 +00:00
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#include <asm/irq.h>
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2006-09-27 04:42:57 +00:00
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#include <asm/hd64461.h>
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2005-04-16 22:20:36 +00:00
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2007-09-11 03:48:45 +00:00
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/* This belongs in cpu specific */
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#define INTC_ICR1 0xA4140010UL
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2008-11-28 08:58:30 +00:00
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static void hd64461_mask_irq(unsigned int irq)
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2005-04-16 22:20:36 +00:00
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{
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unsigned short nimr;
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unsigned short mask = 1 << (irq - HD64461_IRQBASE);
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2008-11-28 08:58:30 +00:00
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nimr = __raw_readw(HD64461_NIMR);
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2005-04-16 22:20:36 +00:00
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nimr |= mask;
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2008-11-28 08:58:30 +00:00
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__raw_writew(nimr, HD64461_NIMR);
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2005-04-16 22:20:36 +00:00
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}
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2008-11-28 08:58:30 +00:00
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static void hd64461_unmask_irq(unsigned int irq)
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2005-04-16 22:20:36 +00:00
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{
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unsigned short nimr;
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unsigned short mask = 1 << (irq - HD64461_IRQBASE);
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2008-11-28 08:58:30 +00:00
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nimr = __raw_readw(HD64461_NIMR);
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2005-04-16 22:20:36 +00:00
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nimr &= ~mask;
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2008-11-28 08:58:30 +00:00
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__raw_writew(nimr, HD64461_NIMR);
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2005-04-16 22:20:36 +00:00
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}
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2008-11-28 08:58:30 +00:00
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static void hd64461_mask_and_ack_irq(unsigned int irq)
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2005-04-16 22:20:36 +00:00
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{
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2008-11-28 08:58:30 +00:00
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hd64461_mask_irq(irq);
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2005-04-16 22:20:36 +00:00
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#ifdef CONFIG_HD64461_ENABLER
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if (irq == HD64461_IRQBASE + 13)
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2008-11-28 08:58:30 +00:00
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__raw_writeb(0x00, HD64461_PCC1CSCR);
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2005-04-16 22:20:36 +00:00
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#endif
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}
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2008-11-28 08:58:30 +00:00
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static struct irq_chip hd64461_irq_chip = {
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.name = "HD64461-IRQ",
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.mask = hd64461_mask_irq,
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.mask_ack = hd64461_mask_and_ack_irq,
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.unmask = hd64461_unmask_irq,
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2005-04-16 22:20:36 +00:00
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};
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2009-03-20 02:08:22 +00:00
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static void hd64461_irq_demux(unsigned int irq, struct irq_desc *desc)
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2005-04-16 22:20:36 +00:00
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{
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2010-01-26 03:58:40 +00:00
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unsigned short intv = __raw_readw(HD64461_NIRR);
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2009-03-20 02:08:22 +00:00
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struct irq_desc *ext_desc;
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unsigned int ext_irq = HD64461_IRQBASE;
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intv &= (1 << HD64461_IRQ_NUM) - 1;
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while (intv) {
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if (intv & 1) {
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ext_desc = irq_desc + ext_irq;
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handle_level_irq(ext_irq, ext_desc);
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}
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intv >>= 1;
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ext_irq++;
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2005-04-16 22:20:36 +00:00
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}
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}
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int __init setup_hd64461(void)
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{
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int i;
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if (!MACH_HD64461)
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return 0;
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printk(KERN_INFO
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"HD64461 configured at 0x%x on irq %d(mapped into %d to %d)\n",
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2009-05-20 02:27:13 +00:00
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HD64461_IOBASE, CONFIG_HD64461_IRQ, HD64461_IRQBASE,
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2005-04-16 22:20:36 +00:00
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HD64461_IRQBASE + 15);
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2008-11-28 08:58:30 +00:00
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/* Should be at processor specific part.. */
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#if defined(CONFIG_CPU_SUBTYPE_SH7709)
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__raw_writew(0x2240, INTC_ICR1);
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2005-04-16 22:20:36 +00:00
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#endif
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2008-11-28 08:58:30 +00:00
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__raw_writew(0xffff, HD64461_NIMR);
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2005-04-16 22:20:36 +00:00
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2007-09-11 03:48:45 +00:00
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/* IRQ 80 -> 95 belongs to HD64461 */
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2008-11-28 08:58:30 +00:00
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for (i = HD64461_IRQBASE; i < HD64461_IRQBASE + 16; i++)
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set_irq_chip_and_handler(i, &hd64461_irq_chip,
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handle_level_irq);
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2005-04-16 22:20:36 +00:00
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2009-03-20 02:08:22 +00:00
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set_irq_chained_handler(CONFIG_HD64461_IRQ, hd64461_irq_demux);
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set_irq_type(CONFIG_HD64461_IRQ, IRQ_TYPE_LEVEL_LOW);
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2005-04-16 22:20:36 +00:00
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#ifdef CONFIG_HD64461_ENABLER
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printk(KERN_INFO "HD64461: enabling PCMCIA devices\n");
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2008-11-28 08:58:30 +00:00
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__raw_writeb(0x4c, HD64461_PCC1CSCIER);
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__raw_writeb(0x00, HD64461_PCC1CSCR);
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2005-04-16 22:20:36 +00:00
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#endif
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return 0;
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}
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module_init(setup_hd64461);
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