mirror of
https://github.com/FEX-Emu/linux.git
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504 lines
11 KiB
C
504 lines
11 KiB
C
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/*
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* arch/arm/plat-s5pc1xx/gpiolib.c
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*
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* Copyright 2009 Samsung Electronics Co
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* Kyungmin Park <kyungmin.park@samsung.com>
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*
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* S5PC1XX - GPIOlib support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <mach/map.h>
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#include <mach/gpio-core.h>
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#include <plat/gpio-cfg.h>
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#include <plat/gpio-cfg-helpers.h>
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#include <plat/regs-gpio.h>
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/* S5PC100 GPIO bank summary:
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*
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* Bank GPIOs Style INT Type
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* A0 8 4Bit GPIO_INT0
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* A1 5 4Bit GPIO_INT1
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* B 8 4Bit GPIO_INT2
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* C 5 4Bit GPIO_INT3
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* D 7 4Bit GPIO_INT4
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* E0 8 4Bit GPIO_INT5
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* E1 6 4Bit GPIO_INT6
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* F0 8 4Bit GPIO_INT7
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* F1 8 4Bit GPIO_INT8
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* F2 8 4Bit GPIO_INT9
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* F3 4 4Bit GPIO_INT10
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* G0 8 4Bit GPIO_INT11
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* G1 3 4Bit GPIO_INT12
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* G2 7 4Bit GPIO_INT13
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* G3 7 4Bit GPIO_INT14
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* H0 8 4Bit WKUP_INT
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* H1 8 4Bit WKUP_INT
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* H2 8 4Bit WKUP_INT
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* H3 8 4Bit WKUP_INT
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* I 8 4Bit GPIO_INT15
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* J0 8 4Bit GPIO_INT16
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* J1 5 4Bit GPIO_INT17
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* J2 8 4Bit GPIO_INT18
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* J3 8 4Bit GPIO_INT19
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* J4 4 4Bit GPIO_INT20
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* K0 8 4Bit None
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* K1 6 4Bit None
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* K2 8 4Bit None
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* K3 8 4Bit None
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* L0 8 4Bit None
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* L1 8 4Bit None
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* L2 8 4Bit None
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* L3 8 4Bit None
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*/
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#define OFF_GPCON (0x00)
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#define OFF_GPDAT (0x04)
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#define con_4bit_shift(__off) ((__off) * 4)
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#if 1
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#define gpio_dbg(x...) do { } while (0)
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#else
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#define gpio_dbg(x...) printk(KERN_DEBUG x)
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#endif
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/* The s5pc1xx_gpiolib routines are to control the gpio banks where
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* the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
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* following example:
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*
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* base + 0x00: Control register, 4 bits per gpio
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* gpio n: 4 bits starting at (4*n)
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* 0000 = input, 0001 = output, others mean special-function
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* base + 0x04: Data register, 1 bit per gpio
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* bit n: data bit n
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*
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* Note, since the data register is one bit per gpio and is at base + 0x4
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* we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of
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* the output.
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*/
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static int s5pc1xx_gpiolib_input(struct gpio_chip *chip, unsigned offset)
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{
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struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
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void __iomem *base = ourchip->base;
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unsigned long con;
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con = __raw_readl(base + OFF_GPCON);
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con &= ~(0xf << con_4bit_shift(offset));
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__raw_writel(con, base + OFF_GPCON);
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gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
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return 0;
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}
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static int s5pc1xx_gpiolib_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
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void __iomem *base = ourchip->base;
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unsigned long con;
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unsigned long dat;
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con = __raw_readl(base + OFF_GPCON);
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con &= ~(0xf << con_4bit_shift(offset));
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con |= 0x1 << con_4bit_shift(offset);
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dat = __raw_readl(base + OFF_GPDAT);
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if (value)
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dat |= 1 << offset;
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else
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dat &= ~(1 << offset);
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__raw_writel(dat, base + OFF_GPDAT);
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__raw_writel(con, base + OFF_GPCON);
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__raw_writel(dat, base + OFF_GPDAT);
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gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
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return 0;
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}
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static int s5pc1xx_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
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{
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return S3C_IRQ_GPIO(chip->base + offset);
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}
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static int s5pc1xx_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
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{
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int base;
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base = chip->base - S5PC100_GPH0(0);
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if (base == 0)
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return IRQ_EINT(offset);
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base = chip->base - S5PC100_GPH1(0);
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if (base == 0)
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return IRQ_EINT(8 + offset);
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base = chip->base - S5PC100_GPH2(0);
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if (base == 0)
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return IRQ_EINT(16 + offset);
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base = chip->base - S5PC100_GPH3(0);
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if (base == 0)
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return IRQ_EINT(24 + offset);
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return -EINVAL;
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}
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static struct s3c_gpio_cfg gpio_cfg = {
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.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
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.set_pull = s3c_gpio_setpull_updown,
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.get_pull = s3c_gpio_getpull_updown,
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};
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static struct s3c_gpio_cfg gpio_cfg_eint = {
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.cfg_eint = 0xf,
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.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
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.set_pull = s3c_gpio_setpull_updown,
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.get_pull = s3c_gpio_getpull_updown,
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};
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static struct s3c_gpio_cfg gpio_cfg_noint = {
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.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
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.set_pull = s3c_gpio_setpull_updown,
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.get_pull = s3c_gpio_getpull_updown,
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};
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static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
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{
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.base = S5PC100_GPA0_BASE,
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.config = &gpio_cfg,
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.chip = {
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.base = S5PC100_GPA0(0),
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.ngpio = S5PC100_GPIO_A0_NR,
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.label = "GPA0",
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},
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}, {
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.base = S5PC100_GPA1_BASE,
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.config = &gpio_cfg,
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.chip = {
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.base = S5PC100_GPA1(0),
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.ngpio = S5PC100_GPIO_A1_NR,
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.label = "GPA1",
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},
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}, {
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.base = S5PC100_GPB_BASE,
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.config = &gpio_cfg,
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.chip = {
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.base = S5PC100_GPB(0),
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.ngpio = S5PC100_GPIO_B_NR,
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.label = "GPB",
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},
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}, {
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.base = S5PC100_GPC_BASE,
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.config = &gpio_cfg,
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.chip = {
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.base = S5PC100_GPC(0),
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.ngpio = S5PC100_GPIO_C_NR,
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.label = "GPC",
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},
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}, {
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.base = S5PC100_GPD_BASE,
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.config = &gpio_cfg,
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.chip = {
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.base = S5PC100_GPD(0),
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.ngpio = S5PC100_GPIO_D_NR,
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.label = "GPD",
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},
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}, {
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.base = S5PC100_GPE0_BASE,
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.config = &gpio_cfg,
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.chip = {
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.base = S5PC100_GPE0(0),
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.ngpio = S5PC100_GPIO_E0_NR,
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.label = "GPE0",
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},
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}, {
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.base = S5PC100_GPE1_BASE,
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.config = &gpio_cfg,
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.chip = {
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.base = S5PC100_GPE1(0),
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.ngpio = S5PC100_GPIO_E1_NR,
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.label = "GPE1",
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},
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}, {
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.base = S5PC100_GPF0_BASE,
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.config = &gpio_cfg,
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.chip = {
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.base = S5PC100_GPF0(0),
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.ngpio = S5PC100_GPIO_F0_NR,
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.label = "GPF0",
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},
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}, {
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.base = S5PC100_GPF1_BASE,
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.config = &gpio_cfg,
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.chip = {
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.base = S5PC100_GPF1(0),
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.ngpio = S5PC100_GPIO_F1_NR,
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.label = "GPF1",
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},
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}, {
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.base = S5PC100_GPF2_BASE,
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.config = &gpio_cfg,
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.chip = {
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.base = S5PC100_GPF2(0),
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.ngpio = S5PC100_GPIO_F2_NR,
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.label = "GPF2",
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},
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}, {
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.base = S5PC100_GPF3_BASE,
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.config = &gpio_cfg,
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.chip = {
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.base = S5PC100_GPF3(0),
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.ngpio = S5PC100_GPIO_F3_NR,
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.label = "GPF3",
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},
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}, {
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.base = S5PC100_GPG0_BASE,
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.config = &gpio_cfg,
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.chip = {
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.base = S5PC100_GPG0(0),
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.ngpio = S5PC100_GPIO_G0_NR,
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.label = "GPG0",
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},
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}, {
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.base = S5PC100_GPG1_BASE,
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.config = &gpio_cfg,
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.chip = {
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.base = S5PC100_GPG1(0),
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.ngpio = S5PC100_GPIO_G1_NR,
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.label = "GPG1",
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},
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}, {
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.base = S5PC100_GPG2_BASE,
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.config = &gpio_cfg,
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.chip = {
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.base = S5PC100_GPG2(0),
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.ngpio = S5PC100_GPIO_G2_NR,
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.label = "GPG2",
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},
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}, {
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.base = S5PC100_GPG3_BASE,
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.config = &gpio_cfg,
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.chip = {
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.base = S5PC100_GPG3(0),
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.ngpio = S5PC100_GPIO_G3_NR,
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.label = "GPG3",
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},
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}, {
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.base = S5PC100_GPH0_BASE,
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.config = &gpio_cfg_eint,
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.chip = {
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.base = S5PC100_GPH0(0),
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.ngpio = S5PC100_GPIO_H0_NR,
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.label = "GPH0",
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},
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}, {
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.base = S5PC100_GPH1_BASE,
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.config = &gpio_cfg_eint,
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.chip = {
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.base = S5PC100_GPH1(0),
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.ngpio = S5PC100_GPIO_H1_NR,
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.label = "GPH1",
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},
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}, {
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.base = S5PC100_GPH2_BASE,
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.config = &gpio_cfg_eint,
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.chip = {
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.base = S5PC100_GPH2(0),
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.ngpio = S5PC100_GPIO_H2_NR,
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.label = "GPH2",
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},
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}, {
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.base = S5PC100_GPH3_BASE,
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.config = &gpio_cfg_eint,
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.chip = {
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.base = S5PC100_GPH3(0),
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.ngpio = S5PC100_GPIO_H3_NR,
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.label = "GPH3",
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},
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}, {
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.base = S5PC100_GPI_BASE,
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.config = &gpio_cfg,
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.chip = {
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.base = S5PC100_GPI(0),
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.ngpio = S5PC100_GPIO_I_NR,
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.label = "GPI",
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},
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}, {
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.base = S5PC100_GPJ0_BASE,
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.config = &gpio_cfg,
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.chip = {
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.base = S5PC100_GPJ0(0),
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.ngpio = S5PC100_GPIO_J0_NR,
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.label = "GPJ0",
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},
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}, {
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.base = S5PC100_GPJ1_BASE,
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.config = &gpio_cfg,
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.chip = {
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.base = S5PC100_GPJ1(0),
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.ngpio = S5PC100_GPIO_J1_NR,
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.label = "GPJ1",
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},
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}, {
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.base = S5PC100_GPJ2_BASE,
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.config = &gpio_cfg,
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.chip = {
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.base = S5PC100_GPJ2(0),
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.ngpio = S5PC100_GPIO_J2_NR,
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.label = "GPJ2",
|
||
|
|
},
|
||
|
|
}, {
|
||
|
|
.base = S5PC100_GPJ3_BASE,
|
||
|
|
.config = &gpio_cfg,
|
||
|
|
.chip = {
|
||
|
|
.base = S5PC100_GPJ3(0),
|
||
|
|
.ngpio = S5PC100_GPIO_J3_NR,
|
||
|
|
.label = "GPJ3",
|
||
|
|
},
|
||
|
|
}, {
|
||
|
|
.base = S5PC100_GPJ4_BASE,
|
||
|
|
.config = &gpio_cfg,
|
||
|
|
.chip = {
|
||
|
|
.base = S5PC100_GPJ4(0),
|
||
|
|
.ngpio = S5PC100_GPIO_J4_NR,
|
||
|
|
.label = "GPJ4",
|
||
|
|
},
|
||
|
|
}, {
|
||
|
|
.base = S5PC100_GPK0_BASE,
|
||
|
|
.config = &gpio_cfg_noint,
|
||
|
|
.chip = {
|
||
|
|
.base = S5PC100_GPK0(0),
|
||
|
|
.ngpio = S5PC100_GPIO_K0_NR,
|
||
|
|
.label = "GPK0",
|
||
|
|
},
|
||
|
|
}, {
|
||
|
|
.base = S5PC100_GPK1_BASE,
|
||
|
|
.config = &gpio_cfg_noint,
|
||
|
|
.chip = {
|
||
|
|
.base = S5PC100_GPK1(0),
|
||
|
|
.ngpio = S5PC100_GPIO_K1_NR,
|
||
|
|
.label = "GPK1",
|
||
|
|
},
|
||
|
|
}, {
|
||
|
|
.base = S5PC100_GPK2_BASE,
|
||
|
|
.config = &gpio_cfg_noint,
|
||
|
|
.chip = {
|
||
|
|
.base = S5PC100_GPK2(0),
|
||
|
|
.ngpio = S5PC100_GPIO_K2_NR,
|
||
|
|
.label = "GPK2",
|
||
|
|
},
|
||
|
|
}, {
|
||
|
|
.base = S5PC100_GPK3_BASE,
|
||
|
|
.config = &gpio_cfg_noint,
|
||
|
|
.chip = {
|
||
|
|
.base = S5PC100_GPK3(0),
|
||
|
|
.ngpio = S5PC100_GPIO_K3_NR,
|
||
|
|
.label = "GPK3",
|
||
|
|
},
|
||
|
|
}, {
|
||
|
|
.base = S5PC100_GPL0_BASE,
|
||
|
|
.config = &gpio_cfg_noint,
|
||
|
|
.chip = {
|
||
|
|
.base = S5PC100_GPL0(0),
|
||
|
|
.ngpio = S5PC100_GPIO_L0_NR,
|
||
|
|
.label = "GPL0",
|
||
|
|
},
|
||
|
|
}, {
|
||
|
|
.base = S5PC100_GPL1_BASE,
|
||
|
|
.config = &gpio_cfg_noint,
|
||
|
|
.chip = {
|
||
|
|
.base = S5PC100_GPL1(0),
|
||
|
|
.ngpio = S5PC100_GPIO_L1_NR,
|
||
|
|
.label = "GPL1",
|
||
|
|
},
|
||
|
|
}, {
|
||
|
|
.base = S5PC100_GPL2_BASE,
|
||
|
|
.config = &gpio_cfg_noint,
|
||
|
|
.chip = {
|
||
|
|
.base = S5PC100_GPL2(0),
|
||
|
|
.ngpio = S5PC100_GPIO_L2_NR,
|
||
|
|
.label = "GPL2",
|
||
|
|
},
|
||
|
|
}, {
|
||
|
|
.base = S5PC100_GPL3_BASE,
|
||
|
|
.config = &gpio_cfg_noint,
|
||
|
|
.chip = {
|
||
|
|
.base = S5PC100_GPL3(0),
|
||
|
|
.ngpio = S5PC100_GPIO_L3_NR,
|
||
|
|
.label = "GPL3",
|
||
|
|
},
|
||
|
|
}, {
|
||
|
|
.base = S5PC100_GPL4_BASE,
|
||
|
|
.config = &gpio_cfg_noint,
|
||
|
|
.chip = {
|
||
|
|
.base = S5PC100_GPL4(0),
|
||
|
|
.ngpio = S5PC100_GPIO_L4_NR,
|
||
|
|
.label = "GPL4",
|
||
|
|
},
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
/* FIXME move from irq-gpio.c */
|
||
|
|
extern struct irq_chip s5pc1xx_gpioint;
|
||
|
|
extern void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
|
||
|
|
|
||
|
|
static __init void s5pc1xx_gpiolib_link(struct s3c_gpio_chip *chip)
|
||
|
|
{
|
||
|
|
chip->chip.direction_input = s5pc1xx_gpiolib_input;
|
||
|
|
chip->chip.direction_output = s5pc1xx_gpiolib_output;
|
||
|
|
chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
|
||
|
|
|
||
|
|
/* Interrupt */
|
||
|
|
if (chip->config == &gpio_cfg) {
|
||
|
|
int i, irq;
|
||
|
|
|
||
|
|
chip->chip.to_irq = s5pc1xx_gpiolib_to_irq;
|
||
|
|
|
||
|
|
for (i = 0; i < chip->chip.ngpio; i++) {
|
||
|
|
irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i;
|
||
|
|
set_irq_chip(irq, &s5pc1xx_gpioint);
|
||
|
|
set_irq_data(irq, &chip->chip);
|
||
|
|
set_irq_handler(irq, handle_level_irq);
|
||
|
|
set_irq_flags(irq, IRQF_VALID);
|
||
|
|
}
|
||
|
|
} else if (chip->config == &gpio_cfg_eint)
|
||
|
|
chip->chip.to_irq = s5pc1xx_gpiolib_to_eint;
|
||
|
|
}
|
||
|
|
|
||
|
|
static __init void s5pc1xx_gpiolib_add(struct s3c_gpio_chip *chips,
|
||
|
|
int nr_chips,
|
||
|
|
void (*fn)(struct s3c_gpio_chip *))
|
||
|
|
{
|
||
|
|
for (; nr_chips > 0; nr_chips--, chips++) {
|
||
|
|
if (fn)
|
||
|
|
(fn)(chips);
|
||
|
|
s3c_gpiolib_add(chips);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static __init int s5pc1xx_gpiolib_init(void)
|
||
|
|
{
|
||
|
|
struct s3c_gpio_chip *chips;
|
||
|
|
int nr_chips;
|
||
|
|
|
||
|
|
chips = s5pc100_gpio_chips;
|
||
|
|
nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
|
||
|
|
|
||
|
|
s5pc1xx_gpiolib_add(chips, nr_chips, s5pc1xx_gpiolib_link);
|
||
|
|
/* Interrupt */
|
||
|
|
set_irq_chained_handler(IRQ_GPIOINT, s5pc1xx_irq_gpioint_handler);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
core_initcall(s5pc1xx_gpiolib_init);
|