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clk: mvebu: use correct bit for 98DX3236 NAND

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The correct fieldbit value for the NAND PLL reload trigger is 27.

Fixes: commit e120c17a70 ("clk: mvebu: support for 98DX3236 SoC")
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Chris Packham 2018-05-24 17:23:41 +12:00 committed by Stephen Boyd
parent 60cc43fc88
commit 00c5a926af
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/mvebu/clk-corediv.c
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@ -72,7 +72,7 @@ static const struct clk_corediv_desc mvebu_corediv_desc[] = {
};
static const struct clk_corediv_desc mv98dx3236_corediv_desc[] = {
{ .mask = 0x0f, .offset = 6, .fieldbit = 26 }, /* NAND clock */
{ .mask = 0x0f, .offset = 6, .fieldbit = 27 }, /* NAND clock */
};
#define to_corediv_clk(p) container_of(p, struct clk_corediv, hw)