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powerpc/mm: Remove unused register usage in SW TLB miss handling
Long ago we had some code that actually used the CTR in the SW TLB miss handlers (603/e300). Since we don't use it no reason to waste cycles saving it off and restoring it (we actually didn't restore it in the fast path case). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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@ -475,12 +475,11 @@ SystemCall:
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. = 0x1000
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InstructionTLBMiss:
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/*
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* r0: stored ctr
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* r0: scratch
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* r1: linux style pte ( later becomes ppc hardware pte )
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* r2: ptr to linux-style pte
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* r3: scratch
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*/
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mfctr r0
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/* Get PTE (linux-style) and check access */
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mfspr r3,SPRN_IMISS
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lis r1,PAGE_OFFSET@h /* check if kernel address */
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@ -531,7 +530,6 @@ InstructionAddressInvalid:
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addis r1,r1,0x2000
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mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */
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mtctr r0 /* Restore CTR */
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andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
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or r2,r2,r1
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mtspr SPRN_SRR1,r2
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@ -552,12 +550,11 @@ InstructionAddressInvalid:
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. = 0x1100
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DataLoadTLBMiss:
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/*
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* r0: stored ctr
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* r0: scratch
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* r1: linux style pte ( later becomes ppc hardware pte )
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* r2: ptr to linux-style pte
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* r3: scratch
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*/
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mfctr r0
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/* Get PTE (linux-style) and check access */
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mfspr r3,SPRN_DMISS
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lis r1,PAGE_OFFSET@h /* check if kernel address */
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@ -607,7 +604,6 @@ DataAddressInvalid:
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rlwinm r1,r3,9,6,6 /* Get load/store bit */
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addis r1,r1,0x2000
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mtspr SPRN_DSISR,r1
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mtctr r0 /* Restore CTR */
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andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
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mtspr SPRN_SRR1,r2
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mfspr r1,SPRN_DMISS /* Get failing address */
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@ -627,12 +623,11 @@ DataAddressInvalid:
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. = 0x1200
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DataStoreTLBMiss:
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/*
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* r0: stored ctr
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* r0: scratch
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* r1: linux style pte ( later becomes ppc hardware pte )
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* r2: ptr to linux-style pte
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* r3: scratch
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*/
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mfctr r0
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/* Get PTE (linux-style) and check access */
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mfspr r3,SPRN_DMISS
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lis r1,PAGE_OFFSET@h /* check if kernel address */
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