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ARM: OMAP2: Add 34xx clock code
This patch add 34xx clock code. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Paul Walmsley
Tony Lindgren
parent
b045d08098
commit
02e19a960a
@ -11,6 +11,7 @@ obj-$(CONFIG_PM) += pm.o sleep.o
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# Clock framework
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obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o
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obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o
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# Specific board support
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obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
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235
arch/arm/mach-omap2/clock34xx.c
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235
arch/arm/mach-omap2/clock34xx.c
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@ -0,0 +1,235 @@
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/*
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* OMAP3-specific clock framework functions
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*
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* Copyright (C) 2007 Texas Instruments, Inc.
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* Copyright (C) 2007 Nokia Corporation
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*
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* Written by Paul Walmsley
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*
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* Parts of this code are based on code written by
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* Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sram.h>
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#include <asm/div64.h>
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#include <asm/bitops.h>
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#include "memory.h"
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#include "clock.h"
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#include "clock34xx.h"
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#include "prm.h"
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#include "prm-regbits-34xx.h"
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#include "cm.h"
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#include "cm-regbits-34xx.h"
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/* CM_CLKEN_PLL*.EN* bit values */
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#define DPLL_LOCKED 0x7
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/**
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* omap3_dpll_recalc - recalculate DPLL rate
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* @clk: DPLL struct clk
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*
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* Recalculate and propagate the DPLL rate.
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*/
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static void omap3_dpll_recalc(struct clk *clk)
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{
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clk->rate = omap2_get_dpll_rate(clk);
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propagate_rate(clk);
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}
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/**
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* omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
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* @clk: DPLL output struct clk
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*
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* Using parent clock DPLL data, look up DPLL state. If locked, set our
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* rate to the dpll_clk * 2; otherwise, just use dpll_clk.
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*/
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static void omap3_clkoutx2_recalc(struct clk *clk)
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{
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const struct dpll_data *dd;
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u32 v;
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struct clk *pclk;
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/* Walk up the parents of clk, looking for a DPLL */
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pclk = clk->parent;
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while (pclk && !pclk->dpll_data)
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pclk = pclk->parent;
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/* clk does not have a DPLL as a parent? */
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WARN_ON(!pclk);
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dd = pclk->dpll_data;
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WARN_ON(!dd->control_reg || !dd->enable_mask);
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v = __raw_readl(dd->control_reg) & dd->enable_mask;
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v >>= __ffs(dd->enable_mask);
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if (v != DPLL_LOCKED)
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clk->rate = clk->parent->rate;
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else
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clk->rate = clk->parent->rate * 2;
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if (clk->flags & RATE_PROPAGATES)
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propagate_rate(clk);
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}
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/*
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* As it is structured now, this will prevent an OMAP2/3 multiboot
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* kernel from compiling. This will need further attention.
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*/
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#if defined(CONFIG_ARCH_OMAP3)
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static struct clk_functions omap2_clk_functions = {
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.clk_enable = omap2_clk_enable,
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.clk_disable = omap2_clk_disable,
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.clk_round_rate = omap2_clk_round_rate,
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.clk_set_rate = omap2_clk_set_rate,
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.clk_set_parent = omap2_clk_set_parent,
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.clk_disable_unused = omap2_clk_disable_unused,
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};
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/*
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* Set clocks for bypass mode for reboot to work.
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*/
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void omap2_clk_prepare_for_reboot(void)
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{
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/* REVISIT: Not ready for 343x */
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#if 0
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u32 rate;
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if (vclk == NULL || sclk == NULL)
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return;
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rate = clk_get_rate(sclk);
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clk_set_rate(vclk, rate);
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#endif
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}
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/* REVISIT: Move this init stuff out into clock.c */
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/*
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* Switch the MPU rate if specified on cmdline.
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* We cannot do this early until cmdline is parsed.
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*/
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static int __init omap2_clk_arch_init(void)
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{
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if (!mpurate)
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return -EINVAL;
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/* REVISIT: not yet ready for 343x */
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#if 0
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if (omap2_select_table_rate(&virt_prcm_set, mpurate))
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printk(KERN_ERR "Could not find matching MPU rate\n");
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#endif
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recalculate_root_clocks();
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printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): "
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"%ld.%01ld/%ld/%ld MHz\n",
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(osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
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(core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ;
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return 0;
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}
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arch_initcall(omap2_clk_arch_init);
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int __init omap2_clk_init(void)
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{
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/* struct prcm_config *prcm; */
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struct clk **clkp;
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/* u32 clkrate; */
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u32 cpu_clkflg;
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/* REVISIT: Ultimately this will be used for multiboot */
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#if 0
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if (cpu_is_omap242x()) {
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cpu_mask = RATE_IN_242X;
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cpu_clkflg = CLOCK_IN_OMAP242X;
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clkp = onchip_24xx_clks;
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} else if (cpu_is_omap2430()) {
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cpu_mask = RATE_IN_243X;
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cpu_clkflg = CLOCK_IN_OMAP243X;
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clkp = onchip_24xx_clks;
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}
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#endif
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if (cpu_is_omap34xx()) {
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cpu_mask = RATE_IN_343X;
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cpu_clkflg = CLOCK_IN_OMAP343X;
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clkp = onchip_34xx_clks;
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/*
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* Update this if there are further clock changes between ES2
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* and production parts
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*/
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if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0)) {
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/* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
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cpu_clkflg |= CLOCK_IN_OMAP3430ES1;
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} else {
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cpu_mask |= RATE_IN_3430ES2;
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cpu_clkflg |= CLOCK_IN_OMAP3430ES2;
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}
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}
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clk_init(&omap2_clk_functions);
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for (clkp = onchip_34xx_clks;
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clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks);
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clkp++) {
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if ((*clkp)->flags & cpu_clkflg)
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clk_register(*clkp);
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}
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/* REVISIT: Not yet ready for OMAP3 */
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#if 0
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/* Check the MPU rate set by bootloader */
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clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
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for (prcm = rate_table; prcm->mpu_speed; prcm++) {
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if (!(prcm->flags & cpu_mask))
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continue;
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if (prcm->xtal_speed != sys_ck.rate)
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continue;
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if (prcm->dpll_speed <= clkrate)
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break;
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}
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curr_prcm_set = prcm;
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#endif
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recalculate_root_clocks();
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printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
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"%ld.%01ld/%ld/%ld MHz\n",
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(osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
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(core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ;
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/*
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* Only enable those clocks we will need, let the drivers
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* enable other clocks as necessary
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*/
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clk_enable_init_clocks();
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/* Avoid sleeping during omap2_clk_prepare_for_reboot() */
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/* REVISIT: not yet ready for 343x */
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#if 0
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vclk = clk_get(NULL, "virt_prcm_set");
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sclk = clk_get(NULL, "sys_ck");
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#endif
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return 0;
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}
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#endif
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