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drm/i915: handle interrupt on new chipset
Update interrupt handling methods for IGDNG with new registers for display and graphics interrupt functions. As we won't use irq-based vblank sync in dri2, so display interrupt on new chip will be used for hotplug only in future. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
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d765898970
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036a4a7d92
drivers/gpu/drm/i915
@ -1162,7 +1162,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
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dev->driver->get_vblank_counter = i915_get_vblank_counter;
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dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
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if (IS_G4X(dev)) {
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if (IS_G4X(dev) || IS_IGDNG(dev)) {
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dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
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dev->driver->get_vblank_counter = gm45_get_vblank_counter;
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}
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@ -167,6 +167,11 @@ typedef struct drm_i915_private {
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/** Cached value of IMR to avoid reads in updating the bitfield */
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u32 irq_mask_reg;
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u32 pipestat[2];
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/** splitted irq regs for graphics and display engine on IGDNG,
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irq_mask_reg is still used for display irq. */
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u32 gt_irq_mask_reg;
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u32 gt_irq_enable_reg;
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u32 de_irq_enable_reg;
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u32 hotplug_supported_mask;
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struct work_struct hotplug_work;
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@ -1714,7 +1714,10 @@ i915_wait_request(struct drm_device *dev, uint32_t seqno)
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BUG_ON(seqno == 0);
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if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
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ier = I915_READ(IER);
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if (IS_IGDNG(dev))
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ier = I915_READ(DEIER) | I915_READ(GTIER);
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else
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ier = I915_READ(IER);
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if (!ier) {
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DRM_ERROR("something (likely vbetool) disabled "
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"interrupts, re-enabling\n");
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@ -57,6 +57,47 @@
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#define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
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DRM_I915_VBLANK_PIPE_B)
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void
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igdng_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
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dev_priv->gt_irq_mask_reg &= ~mask;
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I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
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(void) I915_READ(GTIMR);
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}
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}
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static inline void
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igdng_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
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dev_priv->gt_irq_mask_reg |= mask;
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I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
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(void) I915_READ(GTIMR);
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}
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}
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/* For display hotplug interrupt */
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void
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igdng_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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if ((dev_priv->irq_mask_reg & mask) != 0) {
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dev_priv->irq_mask_reg &= ~mask;
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I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
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(void) I915_READ(DEIMR);
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}
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}
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static inline void
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igdng_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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if ((dev_priv->irq_mask_reg & mask) != mask) {
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dev_priv->irq_mask_reg |= mask;
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I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
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(void) I915_READ(DEIMR);
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}
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}
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void
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i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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@ -196,6 +237,47 @@ static void i915_hotplug_work_func(struct work_struct *work)
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drm_sysfs_hotplug_event(dev);
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}
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irqreturn_t igdng_irq_handler(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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int ret = IRQ_NONE;
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u32 de_iir, gt_iir;
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u32 new_de_iir, new_gt_iir;
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struct drm_i915_master_private *master_priv;
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de_iir = I915_READ(DEIIR);
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gt_iir = I915_READ(GTIIR);
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for (;;) {
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if (de_iir == 0 && gt_iir == 0)
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break;
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ret = IRQ_HANDLED;
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I915_WRITE(DEIIR, de_iir);
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new_de_iir = I915_READ(DEIIR);
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I915_WRITE(GTIIR, gt_iir);
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new_gt_iir = I915_READ(GTIIR);
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if (dev->primary->master) {
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master_priv = dev->primary->master->driver_priv;
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if (master_priv->sarea_priv)
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master_priv->sarea_priv->last_dispatch =
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READ_BREADCRUMB(dev_priv);
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}
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if (gt_iir & GT_USER_INTERRUPT) {
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dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
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DRM_WAKEUP(&dev_priv->irq_queue);
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}
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de_iir = new_de_iir;
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gt_iir = new_gt_iir;
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}
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return ret;
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}
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irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
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{
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struct drm_device *dev = (struct drm_device *) arg;
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@ -212,6 +294,9 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
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atomic_inc(&dev_priv->irq_received);
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if (IS_IGDNG(dev))
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return igdng_irq_handler(dev);
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iir = I915_READ(IIR);
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if (IS_I965G(dev)) {
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@ -349,8 +434,12 @@ void i915_user_irq_get(struct drm_device *dev)
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unsigned long irqflags;
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spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
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if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1))
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i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
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if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
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if (IS_IGDNG(dev))
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igdng_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
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else
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i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
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}
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spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
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}
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@ -361,8 +450,12 @@ void i915_user_irq_put(struct drm_device *dev)
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spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
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BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
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if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0))
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i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
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if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
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if (IS_IGDNG(dev))
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igdng_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
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else
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i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
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}
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spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
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}
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@ -455,6 +548,9 @@ int i915_enable_vblank(struct drm_device *dev, int pipe)
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if (!(pipeconf & PIPEACONF_ENABLE))
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return -EINVAL;
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if (IS_IGDNG(dev))
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return 0;
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spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
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if (IS_I965G(dev))
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i915_enable_pipestat(dev_priv, pipe,
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@ -474,6 +570,9 @@ void i915_disable_vblank(struct drm_device *dev, int pipe)
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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unsigned long irqflags;
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if (IS_IGDNG(dev))
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return;
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spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
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i915_disable_pipestat(dev_priv, pipe,
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PIPE_VBLANK_INTERRUPT_ENABLE |
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@ -547,12 +646,65 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
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/* drm_dma.h hooks
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*/
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static void igdng_irq_preinstall(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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I915_WRITE(HWSTAM, 0xeffe);
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/* XXX hotplug from PCH */
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I915_WRITE(DEIMR, 0xffffffff);
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I915_WRITE(DEIER, 0x0);
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(void) I915_READ(DEIER);
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/* and GT */
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I915_WRITE(GTIMR, 0xffffffff);
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I915_WRITE(GTIER, 0x0);
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(void) I915_READ(GTIER);
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}
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static int igdng_irq_postinstall(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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/* enable kind of interrupts always enabled */
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u32 display_mask = DE_MASTER_IRQ_CONTROL /*| DE_PCH_EVENT */;
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u32 render_mask = GT_USER_INTERRUPT;
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dev_priv->irq_mask_reg = ~display_mask;
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dev_priv->de_irq_enable_reg = display_mask;
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/* should always can generate irq */
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I915_WRITE(DEIIR, I915_READ(DEIIR));
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I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
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I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
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(void) I915_READ(DEIER);
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/* user interrupt should be enabled, but masked initial */
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dev_priv->gt_irq_mask_reg = 0xffffffff;
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dev_priv->gt_irq_enable_reg = render_mask;
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I915_WRITE(GTIIR, I915_READ(GTIIR));
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I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
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I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
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(void) I915_READ(GTIER);
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return 0;
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}
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void i915_driver_irq_preinstall(struct drm_device * dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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atomic_set(&dev_priv->irq_received, 0);
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INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
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if (IS_IGDNG(dev)) {
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igdng_irq_preinstall(dev);
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return;
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}
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if (I915_HAS_HOTPLUG(dev)) {
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I915_WRITE(PORT_HOTPLUG_EN, 0);
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I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
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@ -564,7 +716,6 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
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I915_WRITE(IMR, 0xffffffff);
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I915_WRITE(IER, 0x0);
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(void) I915_READ(IER);
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INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
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}
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int i915_driver_irq_postinstall(struct drm_device *dev)
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@ -572,8 +723,13 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
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DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
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dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
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if (IS_IGDNG(dev))
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return igdng_irq_postinstall(dev);
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/* Unmask the interrupts that we always want on. */
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dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
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@ -613,11 +769,24 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
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(void) I915_READ(IER);
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opregion_enable_asle(dev);
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DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
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return 0;
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}
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static void igdng_irq_uninstall(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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I915_WRITE(HWSTAM, 0xffffffff);
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I915_WRITE(DEIMR, 0xffffffff);
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I915_WRITE(DEIER, 0x0);
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I915_WRITE(DEIIR, I915_READ(DEIIR));
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I915_WRITE(GTIMR, 0xffffffff);
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I915_WRITE(GTIER, 0x0);
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I915_WRITE(GTIIR, I915_READ(GTIIR));
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}
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void i915_driver_irq_uninstall(struct drm_device * dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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@ -627,6 +796,11 @@ void i915_driver_irq_uninstall(struct drm_device * dev)
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dev_priv->vblank_pipe = 0;
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if (IS_IGDNG(dev)) {
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igdng_irq_uninstall(dev);
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return;
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}
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if (I915_HAS_HOTPLUG(dev)) {
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I915_WRITE(PORT_HOTPLUG_EN, 0);
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I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
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