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Fixes for various omap variants, mostly minor fixes for various SoCs

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with the bigger changes being for the dra7 clocks and hwmod data:
 
 - Fix wl12xx for dm3730-evm
 
 - Fix omap4 prm save and clea
 
 - Fix hwmod clkdm use count
 
 - Fix hwmod data for pcie on dra7
 
 - Fix lockdep for hwmod
 
 - Fix USB on most omap3 boars by enabling it in the defconfig
 
 - Fix the bypass clock source for omap5 and dra7
 
 - Fix the ehrpwm clock for am33xx and am43xx
 
 - Enable AES and SHAM for BeagleBone white
 
 - Use rmii clock for am335x-lxm
 
 - Fix polling intervals for omap5 thermal zones
 
 - Fix slewctrl for am33xx and am43xx
 
 - Fix dra7-evm dcan pinctrl
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJU+kTzAAoJEBvUPslcq6VzwIwQAN0eIx/Ay47tarYrhIbC2BAI
 6GpCAk2GUzBdkdzPOhcjDUFEXs764JIi5+q2wRE9MNDpJZxDh2ORv2fmk9KhIIZw
 d08Rv7kEqwg4JKOF0o+hZH5+eOG1Q3wpvN1fmX49XehKcmY8rHec9oDUdk/yhtPy
 a9B4rNRrvtfPXGCPMNs/mZtkdX/af1JYyhdjTOZixCc3IAptu3n88tX2ukw1g1LK
 kK60BTZmEfoD+N3/ZgBU+caJKA9raesq+PhBOcOECIsyXpg8yYwmNlQX119svZaz
 sg7aTd6cFxdhuRmDK21gjP62O2R5EukQs8zJULl9675sy8vA+C9n/pRalqeSudy5
 rmpYXcRUPzFxySIWfJ4mDz90k8SWWRKb1CSl1QK2uyysR899UdkTwlk9A15LiTqw
 sX7ZdyebiE5WdCgLdH+4KMNcF0iGSFRr9jUsP3ouhO8TghnvryQLJw1gWFZgdQwk
 n4jYtl6nSnJBey78yikAFUad94pFyUddGJOAMsUx1qCnrsIk4ug5AcVjbhwDZOvL
 hP7fFaZ/68gEbFELglg0+xYo/9vgON6iVex7o1p4e4dOsE1UCnD9qvT4h1j3mdoj
 yrXN0M9SYRsasKwEwx+LgF4Md04nPGidh4QiCKruZWwBF3rXo8HTuifvejwnjnm1
 OapxrodYFj1K2PlMp+h9
 =C0ct
 -----END PGP SIGNATURE-----

Merge tag 'fixes-v4.0-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes

Pull "omap fixes against v4.0-rc2" from Tony Lindgren:

Fixes for various omap variants, mostly minor fixes for various SoCs
with the bigger changes being for the dra7 clocks and hwmod data:

- Fix wl12xx for dm3730-evm

- Fix omap4 prm save and clea

- Fix hwmod clkdm use count

- Fix hwmod data for pcie on dra7

- Fix lockdep for hwmod

- Fix USB on most omap3 boars by enabling it in the defconfig

- Fix the bypass clock source for omap5 and dra7

- Fix the ehrpwm clock for am33xx and am43xx

- Enable AES and SHAM for BeagleBone white

- Use rmii clock for am335x-lxm

- Fix polling intervals for omap5 thermal zones

- Fix slewctrl for am33xx and am43xx

- Fix dra7-evm dcan pinctrl

* tag 'fixes-v4.0-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP2+: Fix wl12xx on dm3730-evm with mainline u-boot
  ARM: OMAP: enable TWL4030_USB in omap2plus_defconfig
  ARM: dts: dra7x-evm: avoid possible contention while muxing on CAN lines
  ARM: dts: dra7x-evm: Don't use dcan1_rx.gpio1_15 in DCAN pinctrl
  ARM: dts: am43xx: fix SLEWCTRL_FAST pinctrl binding
  ARM: dts: am33xx: fix SLEWCTRL_FAST pinctrl binding
  ARM: dts: OMAP5: fix polling intervals for thermal zones
  ARM: dts: am335x-lxm: Use rmii-clock-ext
  ARM: dts: am335x-bone-common: enable aes and sham
  ARM: dts: am43xx-clocks: Fix ehrpwm tbclk data on am43xx
  ARM: dts: am33xx-clocks: Fix ehrpwm tbclk data on am33xx
  ARM: dts: OMAP5: Fix the bypass clock source for dpll_iva and others
  ARM: dts: DRA7x: Fix the bypass clock source for dpll_iva and others
  ARM: OMAP4+: PRM: fix omap4 version of prm_save_and_clear_irqen
  ARM: OMAP2+: hwmod: fix deassert hardreset clkdm usecounting
  ARM: DRA7: hwmod_data: Fix hwmod data for pcie
  ARM: omap2+: omap_hwmod: Set unique lock_class_key per hwmod
This commit is contained in:
Arnd Bergmann 2015-03-11 15:35:28 +01:00
commit 0397da78a1
20 changed files with 191 additions and 132 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
arch/arm/boot/dts/am335x-bone-common.dtsi
View File

@ -301,3 +301,11 @@
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
};
&aes {
status = "okay";
};
&sham {
status = "okay";
};

8
arch/arm/boot/dts/am335x-bone.dts
View File

@ -24,11 +24,3 @@
&mmc1 {
vmmc-supply = <&ldo3_reg>;
};
&sham {
status = "okay";
};
&aes {
status = "okay";
};

4
arch/arm/boot/dts/am335x-lxm.dts
View File

@ -328,6 +328,10 @@
dual_emac_res_vlan = <3>;
};
&phy_sel {
rmii-clock-ext;
};
&mac {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;

6
arch/arm/boot/dts/am33xx-clocks.dtsi
View File

@ -99,7 +99,7 @@
ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
clocks = <&l4ls_gclk>;
ti,bit-shift = <0>;
reg = <0x0664>;
};
@ -107,7 +107,7 @@
ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
clocks = <&l4ls_gclk>;
ti,bit-shift = <1>;
reg = <0x0664>;
};
@ -115,7 +115,7 @@
ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
clocks = <&l4ls_gclk>;
ti,bit-shift = <2>;
reg = <0x0664>;
};

12
arch/arm/boot/dts/am43xx-clocks.dtsi
View File

@ -107,7 +107,7 @@
ehrpwm0_tbclk: ehrpwm0_tbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
clocks = <&l4ls_gclk>;
ti,bit-shift = <0>;
reg = <0x0664>;
};
@ -115,7 +115,7 @@
ehrpwm1_tbclk: ehrpwm1_tbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
clocks = <&l4ls_gclk>;
ti,bit-shift = <1>;
reg = <0x0664>;
};
@ -123,7 +123,7 @@
ehrpwm2_tbclk: ehrpwm2_tbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
clocks = <&l4ls_gclk>;
ti,bit-shift = <2>;
reg = <0x0664>;
};
@ -131,7 +131,7 @@
ehrpwm3_tbclk: ehrpwm3_tbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
clocks = <&l4ls_gclk>;
ti,bit-shift = <4>;
reg = <0x0664>;
};
@ -139,7 +139,7 @@
ehrpwm4_tbclk: ehrpwm4_tbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
clocks = <&l4ls_gclk>;
ti,bit-shift = <5>;
reg = <0x0664>;
};
@ -147,7 +147,7 @@
ehrpwm5_tbclk: ehrpwm5_tbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
clocks = <&l4ls_gclk>;
ti,bit-shift = <6>;
reg = <0x0664>;
};

10
arch/arm/boot/dts/dra7-evm.dts
View File

@ -263,17 +263,15 @@
dcan1_pins_default: dcan1_pins_default {
pinctrl-single,pins = <
0x3d0 (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */
0x3d4 (MUX_MODE15) /* dcan1_rx.off */
0x418 (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */
0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
>;
};
dcan1_pins_sleep: dcan1_pins_sleep {
pinctrl-single,pins = <
0x3d0 (MUX_MODE15) /* dcan1_tx.off */
0x3d4 (MUX_MODE15) /* dcan1_rx.off */
0x418 (MUX_MODE15) /* wakeup0.off */
0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
>;
};
};

10
arch/arm/boot/dts/dra72-evm.dts
View File

@ -119,17 +119,15 @@
dcan1_pins_default: dcan1_pins_default {
pinctrl-single,pins = <
0x3d0 (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */
0x3d4 (MUX_MODE15) /* dcan1_rx.off */
0x418 (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */
0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
>;
};
dcan1_pins_sleep: dcan1_pins_sleep {
pinctrl-single,pins = <
0x3d0 (MUX_MODE15) /* dcan1_tx.off */
0x3d4 (MUX_MODE15) /* dcan1_rx.off */
0x418 (MUX_MODE15) /* wakeup0.off */
0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
>;
};

90
arch/arm/boot/dts/dra7xx-clocks.dtsi
View File

@ -243,10 +243,18 @@
ti,invert-autoidle-bit;
};
dpll_core_byp_mux: dpll_core_byp_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x012c>;
};
dpll_core_ck: dpll_core_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-core-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
};
@ -309,10 +317,18 @@
clock-div = <1>;
};
dpll_dsp_byp_mux: dpll_dsp_byp_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x0240>;
};
dpll_dsp_ck: dpll_dsp_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
};
@ -335,10 +351,18 @@
clock-div = <1>;
};
dpll_iva_byp_mux: dpll_iva_byp_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x01ac>;
};
dpll_iva_ck: dpll_iva_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
};
@ -361,10 +385,18 @@
clock-div = <1>;
};
dpll_gpu_byp_mux: dpll_gpu_byp_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x02e4>;
};
dpll_gpu_ck: dpll_gpu_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
};
@ -398,10 +430,18 @@
clock-div = <1>;
};
dpll_ddr_byp_mux: dpll_ddr_byp_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x021c>;
};
dpll_ddr_ck: dpll_ddr_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
};
@ -416,10 +456,18 @@
ti,invert-autoidle-bit;
};
dpll_gmac_byp_mux: dpll_gmac_byp_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x02b4>;
};
dpll_gmac_ck: dpll_gmac_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
};
@ -482,10 +530,18 @@
clock-div = <1>;
};
dpll_eve_byp_mux: dpll_eve_byp_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x0290>;
};
dpll_eve_ck: dpll_eve_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
};
@ -1249,10 +1305,18 @@
clock-div = <1>;
};
dpll_per_byp_mux: dpll_per_byp_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x014c>;
};
dpll_per_ck: dpll_per_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
};
@ -1275,10 +1339,18 @@
clock-div = <1>;
};
dpll_usb_byp_mux: dpll_usb_byp_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x018c>;
};
dpll_usb_ck: dpll_usb_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-j-type-clock";
clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
};

2
arch/arm/boot/dts/omap5-core-thermal.dtsi
View File

@ -13,7 +13,7 @@
core_thermal: core_thermal {
polling-delay-passive = <250>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
polling-delay = <500>; /* milliseconds */
/* sensor ID */
thermal-sensors = <&bandgap 2>;

2
arch/arm/boot/dts/omap5-gpu-thermal.dtsi
View File

@ -13,7 +13,7 @@
gpu_thermal: gpu_thermal {
polling-delay-passive = <250>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
polling-delay = <500>; /* milliseconds */
/* sensor ID */
thermal-sensors = <&bandgap 1>;

4
arch/arm/boot/dts/omap5.dtsi
View File

@ -1079,4 +1079,8 @@
};
};
&cpu_thermal {
polling-delay = <500>; /* milliseconds */
};
/include/ "omap54xx-clocks.dtsi"

41
arch/arm/boot/dts/omap54xx-clocks.dtsi
View File

@ -167,10 +167,18 @@
ti,index-starts-at-one;
};
dpll_core_byp_mux: dpll_core_byp_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x012c>;
};
dpll_core_ck: dpll_core_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-core-clock";
clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
clocks = <&sys_clkin>, <&dpll_core_byp_mux>;
reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
};
@ -294,10 +302,18 @@
clock-div = <1>;
};
dpll_iva_byp_mux: dpll_iva_byp_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x01ac>;
};
dpll_iva_ck: dpll_iva_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
clocks = <&sys_clkin>, <&dpll_iva_byp_mux>;
reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
};
@ -599,10 +615,19 @@
};
};
&cm_core_clocks {
dpll_per_byp_mux: dpll_per_byp_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x014c>;
};
dpll_per_ck: dpll_per_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
clocks = <&sys_clkin>, <&dpll_per_byp_mux>;
reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
};
@ -714,10 +739,18 @@
ti,index-starts-at-one;
};
dpll_usb_byp_mux: dpll_usb_byp_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x018c>;
};
dpll_usb_ck: dpll_usb_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-j-type-clock";
clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
clocks = <&sys_clkin>, <&dpll_usb_byp_mux>;
reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
};

1
arch/arm/configs/omap2plus_defconfig
View File

@ -377,6 +377,7 @@ CONFIG_PWM_TWL=m
CONFIG_PWM_TWL_LED=m
CONFIG_OMAP_USB2=m
CONFIG_TI_PIPE3=y
CONFIG_TWL4030_USB=m
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_FS_XATTR is not set

10
arch/arm/mach-omap2/omap_hwmod.c
View File

@ -1692,16 +1692,15 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
if (ret == -EBUSY)
pr_warn("omap_hwmod: %s: failed to hardreset\n", oh->name);
if (!ret) {
if (oh->clkdm) {
/*
* Set the clockdomain to HW_AUTO, assuming that the
* previous state was HW_AUTO.
*/
if (oh->clkdm && hwsup)
if (hwsup)
clkdm_allow_idle(oh->clkdm);
} else {
if (oh->clkdm)
clkdm_hwmod_disable(oh->clkdm, oh);
clkdm_hwmod_disable(oh->clkdm, oh);
}
return ret;
@ -2698,6 +2697,7 @@ static int __init _register(struct omap_hwmod *oh)
INIT_LIST_HEAD(&oh->master_ports);
INIT_LIST_HEAD(&oh->slave_ports);
spin_lock_init(&oh->_lock);
lockdep_set_class(&oh->_lock, &oh->hwmod_key);
oh->_state = _HWMOD_STATE_REGISTERED;

1
arch/arm/mach-omap2/omap_hwmod.h
View File

@ -674,6 +674,7 @@ struct omap_hwmod {
u32 _sysc_cache;
void __iomem *_mpu_rt_va;
spinlock_t _lock;
struct lock_class_key hwmod_key; /* unique lock class */
struct list_head node;
struct omap_hwmod_ocp_if *_mpu_port;
unsigned int (*xlate_irq)(unsigned int);

103
arch/arm/mach-omap2/omap_hwmod_7xx_data.c
View File

@ -1466,53 +1466,16 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
*
*/
static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
.name = "pcie",
};
/* pcie1 */
static struct omap_hwmod dra7xx_pcie1_hwmod = {
static struct omap_hwmod dra7xx_pciess1_hwmod = {
.name = "pcie1",
.class = &dra7xx_pcie_hwmod_class,
.class = &dra7xx_pciess_hwmod_class,
.clkdm_name = "pcie_clkdm",
.main_clk = "l4_root_clk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* pcie2 */
static struct omap_hwmod dra7xx_pcie2_hwmod = {
.name = "pcie2",
.class = &dra7xx_pcie_hwmod_class,
.clkdm_name = "pcie_clkdm",
.main_clk = "l4_root_clk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'PCIE PHY' class
*
*/
static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
.name = "pcie-phy",
};
/* pcie1 phy */
static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
.name = "pcie1-phy",
.class = &dra7xx_pcie_phy_hwmod_class,
.clkdm_name = "l3init_clkdm",
.main_clk = "l4_root_clk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
@ -1522,11 +1485,11 @@ static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
},
};
/* pcie2 phy */
static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {
.name = "pcie2-phy",
.class = &dra7xx_pcie_phy_hwmod_class,
.clkdm_name = "l3init_clkdm",
/* pcie2 */
static struct omap_hwmod dra7xx_pciess2_hwmod = {
.name = "pcie2",
.class = &dra7xx_pciess_hwmod_class,
.clkdm_name = "pcie_clkdm",
.main_clk = "l4_root_clk_div",
.prcm = {
.omap4 = {
@ -2877,50 +2840,34 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_1 -> pcie1 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = {
/* l3_main_1 -> pciess1 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
.master = &dra7xx_l3_main_1_hwmod,
.slave = &dra7xx_pcie1_hwmod,
.slave = &dra7xx_pciess1_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> pcie1 */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
/* l4_cfg -> pciess1 */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
.master = &dra7xx_l4_cfg_hwmod,
.slave = &dra7xx_pcie1_hwmod,
.slave = &dra7xx_pciess1_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_1 -> pcie2 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = {
/* l3_main_1 -> pciess2 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
.master = &dra7xx_l3_main_1_hwmod,
.slave = &dra7xx_pcie2_hwmod,
.slave = &dra7xx_pciess2_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> pcie2 */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
/* l4_cfg -> pciess2 */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
.master = &dra7xx_l4_cfg_hwmod,
.slave = &dra7xx_pcie2_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> pcie1 phy */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
.master = &dra7xx_l4_cfg_hwmod,
.slave = &dra7xx_pcie1_phy_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> pcie2 phy */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
.master = &dra7xx_l4_cfg_hwmod,
.slave = &dra7xx_pcie2_phy_hwmod,
.slave = &dra7xx_pciess2_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@ -3327,12 +3274,10 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_cfg__mpu,
&dra7xx_l4_cfg__ocp2scp1,
&dra7xx_l4_cfg__ocp2scp3,
&dra7xx_l3_main_1__pcie1,
&dra7xx_l4_cfg__pcie1,
&dra7xx_l3_main_1__pcie2,
&dra7xx_l4_cfg__pcie2,
&dra7xx_l4_cfg__pcie1_phy,
&dra7xx_l4_cfg__pcie2_phy,
&dra7xx_l3_main_1__pciess1,
&dra7xx_l4_cfg__pciess1,
&dra7xx_l3_main_1__pciess2,
&dra7xx_l4_cfg__pciess2,
&dra7xx_l3_main_1__qspi,
&dra7xx_l4_per3__rtcss,
&dra7xx_l4_cfg__sata,

1
arch/arm/mach-omap2/pdata-quirks.c
View File

@ -173,6 +173,7 @@ static void __init omap3_igep0030_rev_g_legacy_init(void)
static void __init omap3_evm_legacy_init(void)
{
hsmmc2_internal_input_clk();
legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 149);
}

4
arch/arm/mach-omap2/prm44xx.c
View File

@ -252,10 +252,10 @@ static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
{
saved_mask[0] =
omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
OMAP4_PRM_IRQENABLE_MPU_OFFSET);
saved_mask[1] =
omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET);
OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST,
OMAP4_PRM_IRQENABLE_MPU_OFFSET);

3
include/dt-bindings/pinctrl/am33xx.h
View File

@ -13,7 +13,8 @@
#define PULL_DISABLE (1 << 3)
#define INPUT_EN (1 << 5)
#define SLEWCTRL_FAST (1 << 6)
#define SLEWCTRL_SLOW (1 << 6)
#define SLEWCTRL_FAST 0
/* update macro depending on INPUT_EN and PULL_ENA */
#undef PIN_OUTPUT

3
include/dt-bindings/pinctrl/am43xx.h
View File

@ -18,7 +18,8 @@
#define PULL_DISABLE (1 << 16)
#define PULL_UP (1 << 17)
#define INPUT_EN (1 << 18)
#define SLEWCTRL_FAST (1 << 19)
#define SLEWCTRL_SLOW (1 << 19)
#define SLEWCTRL_FAST 0
#define DS0_PULL_UP_DOWN_EN (1 << 27)
#define PIN_OUTPUT (PULL_DISABLE)