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Staging: vme: Add ca91cx42 rmw support
Add support for Master Read-Modify-Write cycles on the ca91cx42. Signed-off-by: Martyn Welch <martyn.welch@ge.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Martyn Welch
Greg Kroah-Hartman
parent
21e0cf6d2e
commit
04e10e15f9
@ -56,7 +56,6 @@ Tempe (tsi148)
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Universe II (ca91c142)
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----------------------
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- RMW transactions unsupported.
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- Mailboxes unsupported.
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- Error Detection.
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- Control of prefetch size, threshold.
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@ -904,6 +904,60 @@ ssize_t ca91cx42_master_write(struct vme_master_resource *image, void *buf,
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return retval;
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}
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unsigned int ca91cx42_master_rmw(struct vme_master_resource *image,
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unsigned int mask, unsigned int compare, unsigned int swap,
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loff_t offset)
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{
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u32 pci_addr, result;
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int i;
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struct ca91cx42_driver *bridge;
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struct device *dev;
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bridge = image->parent->driver_priv;
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dev = image->parent->parent;
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/* Find the PCI address that maps to the desired VME address */
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i = image->number;
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/* Locking as we can only do one of these at a time */
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mutex_lock(&(bridge->vme_rmw));
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/* Lock image */
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spin_lock(&(image->lock));
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pci_addr = (u32)image->kern_base + offset;
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/* Address must be 4-byte aligned */
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if (pci_addr & 0x3) {
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dev_err(dev, "RMW Address not 4-byte aligned\n");
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return -EINVAL;
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}
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/* Ensure RMW Disabled whilst configuring */
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iowrite32(0, bridge->base + SCYC_CTL);
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/* Configure registers */
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iowrite32(mask, bridge->base + SCYC_EN);
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iowrite32(compare, bridge->base + SCYC_CMP);
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iowrite32(swap, bridge->base + SCYC_SWP);
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iowrite32(pci_addr, bridge->base + SCYC_ADDR);
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/* Enable RMW */
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iowrite32(CA91CX42_SCYC_CTL_CYC_RMW, bridge->base + SCYC_CTL);
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/* Kick process off with a read to the required address. */
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result = ioread32(image->kern_base + offset);
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/* Disable RMW */
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iowrite32(0, bridge->base + SCYC_CTL);
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spin_unlock(&(image->lock));
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mutex_unlock(&(bridge->vme_rmw));
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return result;
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}
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int ca91cx42_dma_list_add(struct vme_dma_list *list, struct vme_dma_attr *src,
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struct vme_dma_attr *dest, size_t count)
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{
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@ -1640,9 +1694,7 @@ static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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ca91cx42_bridge->master_set = ca91cx42_master_set;
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ca91cx42_bridge->master_read = ca91cx42_master_read;
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ca91cx42_bridge->master_write = ca91cx42_master_write;
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#if 0
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ca91cx42_bridge->master_rmw = ca91cx42_master_rmw;
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#endif
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ca91cx42_bridge->dma_list_add = ca91cx42_dma_list_add;
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ca91cx42_bridge->dma_list_exec = ca91cx42_dma_list_exec;
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ca91cx42_bridge->dma_list_empty = ca91cx42_dma_list_empty;
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@ -1832,88 +1884,6 @@ module_exit(ca91cx42_exit);
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#if 0
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int ca91cx42_master_rmw(vmeRmwCfg_t *vmeRmw)
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{
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int temp_ctl = 0;
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int tempBS = 0;
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int tempBD = 0;
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int tempTO = 0;
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int vmeBS = 0;
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int vmeBD = 0;
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int *rmw_pci_data_ptr = NULL;
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int *vaDataPtr = NULL;
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int i;
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vmeOutWindowCfg_t vmeOut;
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if (vmeRmw->maxAttempts < 1) {
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return -EINVAL;
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}
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if (vmeRmw->targetAddrU) {
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return -EINVAL;
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}
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/* Find the PCI address that maps to the desired VME address */
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for (i = 0; i < 8; i++) {
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temp_ctl = ioread32(bridge->base +
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CA91CX42_LSI_CTL[i]);
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if ((temp_ctl & 0x80000000) == 0) {
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continue;
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}
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memset(&vmeOut, 0, sizeof(vmeOut));
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vmeOut.windowNbr = i;
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ca91cx42_get_out_bound(&vmeOut);
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if (vmeOut.addrSpace != vmeRmw->addrSpace) {
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continue;
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}
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tempBS = ioread32(bridge->base + CA91CX42_LSI_BS[i]);
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tempBD = ioread32(bridge->base + CA91CX42_LSI_BD[i]);
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tempTO = ioread32(bridge->base + CA91CX42_LSI_TO[i]);
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vmeBS = tempBS + tempTO;
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vmeBD = tempBD + tempTO;
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if ((vmeRmw->targetAddr >= vmeBS) &&
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(vmeRmw->targetAddr < vmeBD)) {
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rmw_pci_data_ptr =
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(int *)(tempBS + (vmeRmw->targetAddr - vmeBS));
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vaDataPtr =
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(int *)(out_image_va[i] +
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(vmeRmw->targetAddr - vmeBS));
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break;
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}
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}
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/* If no window - fail. */
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if (rmw_pci_data_ptr == NULL) {
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return -EINVAL;
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}
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/* Setup the RMW registers. */
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iowrite32(0, bridge->base + SCYC_CTL);
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iowrite32(SWIZZLE(vmeRmw->enableMask), bridge->base + SCYC_EN);
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iowrite32(SWIZZLE(vmeRmw->compareData), bridge->base +
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SCYC_CMP);
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iowrite32(SWIZZLE(vmeRmw->swapData), bridge->base + SCYC_SWP);
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iowrite32((int)rmw_pci_data_ptr, bridge->base + SCYC_ADDR);
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iowrite32(1, bridge->base + SCYC_CTL);
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/* Run the RMW cycle until either success or max attempts. */
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vmeRmw->numAttempts = 1;
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while (vmeRmw->numAttempts <= vmeRmw->maxAttempts) {
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if ((ioread32(vaDataPtr) & vmeRmw->enableMask) ==
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(vmeRmw->swapData & vmeRmw->enableMask)) {
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iowrite32(0, bridge->base + SCYC_CTL);
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break;
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}
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vmeRmw->numAttempts++;
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}
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/* If no success, set num Attempts to be greater than max attempts */
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if (vmeRmw->numAttempts > vmeRmw->maxAttempts) {
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vmeRmw->numAttempts = vmeRmw->maxAttempts + 1;
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}
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return 0;
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}
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int ca91cx42_set_arbiter(vmeArbiterCfg_t *vmeArb)
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{
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int temp_ctl = 0;
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@ -316,6 +316,16 @@ static const int CA91CX42_VSI_TO[] = { VSI0_TO, VSI1_TO, VSI2_TO, VSI3_TO,
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#define CA91CX42_LSI_CTL_VCT_MBLT (1<<8)
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#define CA91CX42_LSI_CTL_LAS (1<<0)
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/*
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* SCYC_CTL Register
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* offset 178
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*/
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#define CA91CX42_SCYC_CTL_LAS_PCIMEM 0
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#define CA91CX42_SCYC_CTL_LAS_PCIIO (1<<2)
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#define CA91CX42_SCYC_CTL_CYC_M (3<<0)
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#define CA91CX42_SCYC_CTL_CYC_RMW (1<<0)
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#define CA91CX42_SCYC_CTL_CYC_ADOH (1<<1)
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/*
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* LMISC Register
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