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[ARM] 5489/1: ARM errata: Data written to the L2 cache can be overwritten with stale data

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This patch is a workaround for the 460075 Cortex-A8 (r2p0) erratum. It
configures the L2 cache auxiliary control register so that the Write
Allocate mode for the L2 cache is disabled.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Catalin Marinas 2009-04-30 17:06:20 +01:00 committed by Russell King
parent 855c551f5b
commit 0516e4643c
2 changed files with 17 additions and 0 deletions
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12
arch/arm/Kconfig
View File

@ -778,6 +778,18 @@ config ARM_ERRATA_458693
in the ACTLR register. Note that setting specific bits in the ACTLR in the ACTLR register. Note that setting specific bits in the ACTLR
register may not be available in non-secure mode. register may not be available in non-secure mode.
config ARM_ERRATA_460075
bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
depends on CPU_V7
help
This option enables the workaround for the 460075 Cortex-A8 (r2p0)
erratum. Any asynchronous access to the L2 cache may encounter a
situation in which recent store transactions to the L2 cache are lost
and overwritten with stale memory contents from external memory. The
workaround disables the write-allocate mode for the L2 cache via the
ACTLR register. Note that setting specific bits in the ACTLR register
may not be available in non-secure mode.
endmenu endmenu
source "arch/arm/common/Kconfig" source "arch/arm/common/Kconfig"

5
arch/arm/mm/proc-v7.S
View File

@ -193,6 +193,11 @@ __v7_setup:
orr r10, r10, #(1 << 5) @ set L1NEON to 1 orr r10, r10, #(1 << 5) @ set L1NEON to 1
orr r10, r10, #(1 << 9) @ set PLDNOP to 1 orr r10, r10, #(1 << 9) @ set PLDNOP to 1
mcr p15, 0, r10, c1, c0, 1 @ write aux control register mcr p15, 0, r10, c1, c0, 1 @ write aux control register
#endif
#ifdef CONFIG_ARM_ERRATA_460075
mrc p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
orr r10, r10, #(1 << 22) @ set the Write Allocate disable bit
mcr p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
#endif #endif
mov r10, #0 mov r10, #0
#ifdef HARVARD_CACHE #ifdef HARVARD_CACHE