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davinci: INTC: add support for TI cp_intc
Add support for Texas Instuments Common Platform Interrupt Controller (cp_intc) used on DA830/OMAP-L137. Signed-off-by: Steve Chen <schen@mvista.com> Signed-off-by: Mark Greer <mgreer@mvista.com> Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This commit is contained in:
Sergei Shtylyov
Kevin Hilman
parent
27428e39da
commit
0521444d49
@ -1,5 +1,8 @@
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if ARCH_DAVINCI
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config CP_INTC
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bool
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menu "TI DaVinci Implementations"
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comment "DaVinci Core Type"
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@ -8,6 +8,7 @@ obj-y := time.o irq.o clock.o serial.o io.o id.o psc.o \
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gpio.o devices.o dma.o usb.o
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obj-$(CONFIG_DAVINCI_MUX) += mux.o
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obj-$(CONFIG_CP_INTC) += cp_intc.o
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# Chip specific
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obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o
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161
arch/arm/mach-davinci/cp_intc.c
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161
arch/arm/mach-davinci/cp_intc.c
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@ -0,0 +1,161 @@
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/*
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* TI Common Platform Interrupt Controller (cp_intc) driver
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*
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* Author: Steve Chen <schen@mvista.com>
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* Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <mach/cp_intc.h>
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static void __iomem *cp_intc_base;
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static inline unsigned int cp_intc_read(unsigned offset)
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{
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return __raw_readl(cp_intc_base + offset);
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}
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static inline void cp_intc_write(unsigned long value, unsigned offset)
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{
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__raw_writel(value, cp_intc_base + offset);
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}
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static void cp_intc_ack_irq(unsigned int irq)
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{
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cp_intc_write(irq, CP_INTC_SYS_STAT_IDX_CLR);
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}
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/* Disable interrupt */
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static void cp_intc_mask_irq(unsigned int irq)
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{
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/* XXX don't know why we need to disable nIRQ here... */
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cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR);
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cp_intc_write(irq, CP_INTC_SYS_ENABLE_IDX_CLR);
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cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
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}
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/* Enable interrupt */
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static void cp_intc_unmask_irq(unsigned int irq)
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{
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cp_intc_write(irq, CP_INTC_SYS_ENABLE_IDX_SET);
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}
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static int cp_intc_set_irq_type(unsigned int irq, unsigned int flow_type)
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{
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unsigned reg = BIT_WORD(irq);
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unsigned mask = BIT_MASK(irq);
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unsigned polarity = cp_intc_read(CP_INTC_SYS_POLARITY(reg));
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unsigned type = cp_intc_read(CP_INTC_SYS_TYPE(reg));
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switch (flow_type) {
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case IRQ_TYPE_EDGE_RISING:
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polarity |= mask;
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type |= mask;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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polarity &= ~mask;
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type |= mask;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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polarity |= mask;
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type &= ~mask;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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polarity &= ~mask;
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type &= ~mask;
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break;
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default:
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return -EINVAL;
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}
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cp_intc_write(polarity, CP_INTC_SYS_POLARITY(reg));
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cp_intc_write(type, CP_INTC_SYS_TYPE(reg));
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return 0;
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}
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static struct irq_chip cp_intc_irq_chip = {
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.name = "cp_intc",
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.ack = cp_intc_ack_irq,
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.mask = cp_intc_mask_irq,
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.unmask = cp_intc_unmask_irq,
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.set_type = cp_intc_set_irq_type,
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};
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void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
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u8 *irq_prio)
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{
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unsigned num_reg = BITS_TO_LONGS(num_irq);
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int i;
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cp_intc_base = base;
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cp_intc_write(0, CP_INTC_GLOBAL_ENABLE);
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/* Disable all host interrupts */
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cp_intc_write(0, CP_INTC_HOST_ENABLE(0));
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/* Disable system interrupts */
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for (i = 0; i < num_reg; i++)
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cp_intc_write(~0, CP_INTC_SYS_ENABLE_CLR(i));
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/* Set to normal mode, no nesting, no priority hold */
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cp_intc_write(0, CP_INTC_CTRL);
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cp_intc_write(0, CP_INTC_HOST_CTRL);
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/* Clear system interrupt status */
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for (i = 0; i < num_reg; i++)
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cp_intc_write(~0, CP_INTC_SYS_STAT_CLR(i));
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/* Enable nIRQ (what about nFIQ?) */
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cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
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/*
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* Priority is determined by host channel: lower channel number has
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* higher priority i.e. channel 0 has highest priority and channel 31
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* had the lowest priority.
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*/
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num_reg = (num_irq + 3) >> 2; /* 4 channels per register */
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if (irq_prio) {
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unsigned j, k;
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u32 val;
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for (k = i = 0; i < num_reg; i++) {
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for (val = j = 0; j < 4; j++, k++) {
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val >>= 8;
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if (k < num_irq)
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val |= irq_prio[k] << 24;
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}
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cp_intc_write(val, CP_INTC_CHAN_MAP(i));
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}
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} else {
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/*
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* Default everything to channel 15 if priority not specified.
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* Note that channel 0-1 are mapped to nFIQ and channels 2-31
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* are mapped to nIRQ.
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*/
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for (i = 0; i < num_reg; i++)
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cp_intc_write(0x0f0f0f0f, CP_INTC_CHAN_MAP(i));
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}
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/* Set up genirq dispatching for cp_intc */
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for (i = 0; i < num_irq; i++) {
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set_irq_chip(i, &cp_intc_irq_chip);
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set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
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set_irq_handler(i, handle_edge_irq);
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}
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/* Enable global interrupt */
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cp_intc_write(1, CP_INTC_GLOBAL_ENABLE);
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}
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57
arch/arm/mach-davinci/include/mach/cp_intc.h
Normal file
57
arch/arm/mach-davinci/include/mach/cp_intc.h
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@ -0,0 +1,57 @@
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/*
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* TI Common Platform Interrupt Controller (cp_intc) definitions
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*
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* Author: Steve Chen <schen@mvista.com>
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* Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#ifndef __ASM_HARDWARE_CP_INTC_H
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#define __ASM_HARDWARE_CP_INTC_H
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#define CP_INTC_REV 0x00
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#define CP_INTC_CTRL 0x04
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#define CP_INTC_HOST_CTRL 0x0C
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#define CP_INTC_GLOBAL_ENABLE 0x10
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#define CP_INTC_GLOBAL_NESTING_LEVEL 0x1C
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#define CP_INTC_SYS_STAT_IDX_SET 0x20
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#define CP_INTC_SYS_STAT_IDX_CLR 0x24
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#define CP_INTC_SYS_ENABLE_IDX_SET 0x28
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#define CP_INTC_SYS_ENABLE_IDX_CLR 0x2C
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#define CP_INTC_GLOBAL_WAKEUP_ENABLE 0x30
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#define CP_INTC_HOST_ENABLE_IDX_SET 0x34
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#define CP_INTC_HOST_ENABLE_IDX_CLR 0x38
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#define CP_INTC_PACING_PRESCALE 0x40
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#define CP_INTC_VECTOR_BASE 0x50
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#define CP_INTC_VECTOR_SIZE 0x54
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#define CP_INTC_VECTOR_NULL 0x58
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#define CP_INTC_PRIO_IDX 0x80
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#define CP_INTC_PRIO_VECTOR 0x84
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#define CP_INTC_SECURE_ENABLE 0x90
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#define CP_INTC_SECURE_PRIO_IDX 0x94
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#define CP_INTC_PACING_PARAM(n) (0x0100 + (n << 4))
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#define CP_INTC_PACING_DEC(n) (0x0104 + (n << 4))
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#define CP_INTC_PACING_MAP(n) (0x0108 + (n << 4))
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#define CP_INTC_SYS_RAW_STAT(n) (0x0200 + (n << 2))
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#define CP_INTC_SYS_STAT_CLR(n) (0x0280 + (n << 2))
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#define CP_INTC_SYS_ENABLE_SET(n) (0x0300 + (n << 2))
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#define CP_INTC_SYS_ENABLE_CLR(n) (0x0380 + (n << 2))
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#define CP_INTC_CHAN_MAP(n) (0x0400 + (n << 2))
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#define CP_INTC_HOST_MAP(n) (0x0800 + (n << 2))
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#define CP_INTC_HOST_PRIO_IDX(n) (0x0900 + (n << 2))
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#define CP_INTC_SYS_POLARITY(n) (0x0D00 + (n << 2))
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#define CP_INTC_SYS_TYPE(n) (0x0D80 + (n << 2))
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#define CP_INTC_WAKEUP_ENABLE(n) (0x0E00 + (n << 2))
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#define CP_INTC_DEBUG_SELECT(n) (0x0F00 + (n << 2))
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#define CP_INTC_SYS_SECURE_ENABLE(n) (0x1000 + (n << 2))
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#define CP_INTC_HOST_NESTING_LEVEL(n) (0x1100 + (n << 2))
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#define CP_INTC_HOST_ENABLE(n) (0x1500 + (n << 2))
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#define CP_INTC_HOST_PRIO_VECTOR(n) (0x1600 + (n << 2))
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#define CP_INTC_VECTOR_ADDR(n) (0x2000 + (n << 2))
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void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
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u8 *irq_prio);
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#endif /* __ASM_HARDWARE_CP_INTC_H */
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