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tools/power turbostat: Baytrail c-state support
The Baytrail SOC, with its Silvermont core, has some unique properties: 1. a hardware CC1 residency counter 2. a module-c6 residency counter 3. a package-c6 counter at traditional package-c7 counter address. The SOC does not support c3, pc3, c7 or pc7 counters. Signed-off-by: Len Brown <len.brown@intel.com>
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Len Brown
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419c9e986e
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0539ba118f
@ -147,6 +147,7 @@
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/* C-state Residency Counters */
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#define MSR_PKG_C3_RESIDENCY 0x000003f8
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#define MSR_PKG_C6_RESIDENCY 0x000003f9
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#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa
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#define MSR_PKG_C7_RESIDENCY 0x000003fa
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#define MSR_CORE_C3_RESIDENCY 0x000003fc
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#define MSR_CORE_C6_RESIDENCY 0x000003fd
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@ -203,6 +204,7 @@
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#define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
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#define MSR_CORE_C1_RES 0x00000660
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#define MSR_MODULE_C6_RES_MS 0x00000664
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#define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668
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#define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669
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@ -167,6 +167,7 @@ struct core_data {
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unsigned long long c3;
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unsigned long long c6;
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unsigned long long c7;
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unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */
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unsigned int core_temp_c;
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unsigned int core_id;
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unsigned long long counter[MAX_ADDED_COUNTERS];
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@ -375,6 +376,7 @@ struct msr_counter bic[] = {
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{ 0x0, "RAM_J" },
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{ 0x0, "Core" },
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{ 0x0, "CPU" },
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{ 0x0, "Mod%c6" },
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};
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#define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter))
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@ -412,6 +414,7 @@ struct msr_counter bic[] = {
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#define BIC_RAM_J (1ULL << 31)
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#define BIC_Core (1ULL << 32)
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#define BIC_CPU (1ULL << 33)
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#define BIC_Mod_c6 (1ULL << 34)
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unsigned long long bic_enabled = 0xFFFFFFFFFFFFFFFFULL;
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unsigned long long bic_present;
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@ -504,6 +507,8 @@ void print_header(void)
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if (DO_BIC(BIC_CPU_c7))
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outp += sprintf(outp, "\tCPU%%c7");
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if (DO_BIC(BIC_Mod_c6))
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outp += sprintf(outp, "\tMod%%c6");
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if (DO_BIC(BIC_CoreTmp))
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outp += sprintf(outp, "\tCoreTmp");
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@ -629,6 +634,7 @@ int dump_counters(struct thread_data *t, struct core_data *c,
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outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n",
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i, mp->msr_num, c->counter[i]);
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}
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outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us);
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}
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if (p) {
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@ -774,6 +780,10 @@ int format_counters(struct thread_data *t, struct core_data *c,
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if (DO_BIC(BIC_CPU_c7))
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outp += sprintf(outp, "\t%.2f", 100.0 * c->c7/t->tsc);
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/* Mod%c6 */
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if (DO_BIC(BIC_Mod_c6))
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outp += sprintf(outp, "\t%.2f", 100.0 * c->mc6_us / t->tsc);
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if (DO_BIC(BIC_CoreTmp))
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outp += sprintf(outp, "\t%d", c->core_temp_c);
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@ -988,6 +998,7 @@ delta_core(struct core_data *new, struct core_data *old)
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old->c6 = new->c6 - old->c6;
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old->c7 = new->c7 - old->c7;
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old->core_temp_c = new->core_temp_c;
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old->mc6_us = new->mc6_us - old->mc6_us;
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for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
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if (mp->format == FORMAT_RAW)
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@ -1109,6 +1120,7 @@ void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data
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c->c3 = 0;
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c->c6 = 0;
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c->c7 = 0;
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c->mc6_us = 0;
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c->core_temp_c = 0;
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p->pkg_wtd_core_c0 = 0;
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@ -1173,6 +1185,7 @@ int sum_counters(struct thread_data *t, struct core_data *c,
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average.cores.c3 += c->c3;
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average.cores.c6 += c->c6;
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average.cores.c7 += c->c7;
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average.cores.mc6_us += c->mc6_us;
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average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c);
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@ -1246,6 +1259,7 @@ void compute_average(struct thread_data *t, struct core_data *c,
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average.cores.c3 /= topo.num_cores;
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average.cores.c6 /= topo.num_cores;
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average.cores.c7 /= topo.num_cores;
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average.cores.mc6_us /= topo.num_cores;
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if (do_skl_residency) {
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average.packages.pkg_wtd_core_c0 /= topo.num_packages;
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@ -1376,8 +1390,7 @@ retry:
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return -5;
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t->smi_count = msr & 0xFFFFFFFF;
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}
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if (use_c1_residency_msr) {
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if (DO_BIC(BIC_CPU_c1) && use_c1_residency_msr) {
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if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1))
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return -6;
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}
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@ -1409,6 +1422,10 @@ retry:
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if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7))
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return -8;
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if (DO_BIC(BIC_Mod_c6))
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if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us))
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return -8;
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if (DO_BIC(BIC_CoreTmp)) {
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if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
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return -9;
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@ -1437,9 +1454,16 @@ retry:
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if (do_pc3)
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if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3))
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return -9;
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if (do_pc6)
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if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6))
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return -10;
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if (do_pc6) {
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if (do_slm_cstates) {
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if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6))
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return -10;
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} else {
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if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6))
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return -10;
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}
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}
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if (do_pc2)
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if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2))
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return -11;
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@ -1533,7 +1557,7 @@ char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2",
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int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
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int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
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int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
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int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
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int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7};
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int amt_pkg_cstate_limits[16] = {PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
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int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
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int bxt_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
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@ -3336,8 +3360,6 @@ int has_skl_msrs(unsigned int family, unsigned int model)
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return 0;
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}
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int is_slm(unsigned int family, unsigned int model)
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{
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if (!genuine_intel)
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@ -3731,6 +3753,12 @@ void process_cpuid()
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do_pc3 = (pkg_cstate_limit >= PCL__3);
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do_pc6 = (pkg_cstate_limit >= PCL__6);
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do_pc7 = do_snb_cstates && (pkg_cstate_limit >= PCL__7);
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if (has_slv_msrs(family, model)) {
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do_pc2 = do_pc3 = do_pc7 = 0;
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do_pc6 = 1;
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BIC_PRESENT(BIC_Mod_c6);
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use_c1_residency_msr = 1;
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}
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do_c8_c9_c10 = has_hsw_msrs(family, model);
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do_irtl_hsw = has_hsw_msrs(family, model);
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do_skl_residency = has_skl_msrs(family, model);
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@ -4112,7 +4140,7 @@ int get_and_dump_counters(void)
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}
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void print_version() {
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fprintf(outf, "turbostat version 4.17 1 Jan 2017"
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fprintf(outf, "turbostat version 4.17 10 Jan 2017"
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" - Len Brown <lenb@kernel.org>\n");
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}
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