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drm/radeon/kms/DCE6.1: ss is not supported on the internal pplls

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It's handled via external clock. It should already be protected
by the external ss flag, but add an explicit check just in case.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher 2012-03-20 17:18:34 -04:00 committed by Dave Airlie
parent 641998701b
commit 0671bdd798
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/radeon/atombios_crtc.c
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@ -474,7 +474,7 @@ static void atombios_crtc_program_ss(struct radeon_device *rdev,
return;
}
args.v3.ucEnable = enable;
if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK))
if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE61(rdev))
args.v3.ucEnable = ATOM_DISABLE;
} else if (ASIC_IS_DCE4(rdev)) {
args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);