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net: usb: sr9700: Use 'SR_' prefix for the common register macros
The commone register macors (e.g. RSR) is too commont to drivers, it may
be conflict with the architectures (e.g. xtensa, sh).
The related warnings (with allmodconfig under xtensa):
CC [M] drivers/net/usb/sr9700.o
In file included from drivers/net/usb/sr9700.c:24:0:
drivers/net/usb/sr9700.h:65:0: warning: "RSR" redefined
#define RSR 0x06
^
In file included from ./arch/xtensa/include/asm/bitops.h:22:0,
from include/linux/bitops.h:36,
from include/linux/kernel.h:10,
from include/linux/list.h:8,
from include/linux/module.h:9,
from drivers/net/usb/sr9700.c:13:
./arch/xtensa/include/asm/processor.h:190:0: note: this is the location of the previous definition
#define RSR(v,sr) __asm__ __volatile__ ("rsr %0,"__stringify(sr) : "=a"(v));
^
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Chen Gang
David S. Miller
parent
4c122f4cbf
commit
06b19b1b17
@ -77,7 +77,7 @@ static int wait_phy_eeprom_ready(struct usbnet *dev, int phy)
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int ret;
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udelay(1);
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ret = sr_read_reg(dev, EPCR, &tmp);
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ret = sr_read_reg(dev, SR_EPCR, &tmp);
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if (ret < 0)
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return ret;
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@ -98,15 +98,15 @@ static int sr_share_read_word(struct usbnet *dev, int phy, u8 reg,
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mutex_lock(&dev->phy_mutex);
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sr_write_reg(dev, EPAR, phy ? (reg | EPAR_PHY_ADR) : reg);
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sr_write_reg(dev, EPCR, phy ? (EPCR_EPOS | EPCR_ERPRR) : EPCR_ERPRR);
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sr_write_reg(dev, SR_EPAR, phy ? (reg | EPAR_PHY_ADR) : reg);
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sr_write_reg(dev, SR_EPCR, phy ? (EPCR_EPOS | EPCR_ERPRR) : EPCR_ERPRR);
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ret = wait_phy_eeprom_ready(dev, phy);
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if (ret < 0)
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goto out_unlock;
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sr_write_reg(dev, EPCR, 0x0);
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ret = sr_read(dev, EPDR, 2, value);
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sr_write_reg(dev, SR_EPCR, 0x0);
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ret = sr_read(dev, SR_EPDR, 2, value);
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netdev_dbg(dev->net, "read shared %d 0x%02x returned 0x%04x, %d\n",
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phy, reg, *value, ret);
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@ -123,19 +123,19 @@ static int sr_share_write_word(struct usbnet *dev, int phy, u8 reg,
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mutex_lock(&dev->phy_mutex);
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ret = sr_write(dev, EPDR, 2, &value);
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ret = sr_write(dev, SR_EPDR, 2, &value);
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if (ret < 0)
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goto out_unlock;
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sr_write_reg(dev, EPAR, phy ? (reg | EPAR_PHY_ADR) : reg);
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sr_write_reg(dev, EPCR, phy ? (EPCR_WEP | EPCR_EPOS | EPCR_ERPRW) :
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sr_write_reg(dev, SR_EPAR, phy ? (reg | EPAR_PHY_ADR) : reg);
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sr_write_reg(dev, SR_EPCR, phy ? (EPCR_WEP | EPCR_EPOS | EPCR_ERPRW) :
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(EPCR_WEP | EPCR_ERPRW));
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ret = wait_phy_eeprom_ready(dev, phy);
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if (ret < 0)
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goto out_unlock;
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sr_write_reg(dev, EPCR, 0x0);
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sr_write_reg(dev, SR_EPCR, 0x0);
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out_unlock:
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mutex_unlock(&dev->phy_mutex);
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@ -188,7 +188,7 @@ static int sr_mdio_read(struct net_device *netdev, int phy_id, int loc)
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if (loc == MII_BMSR) {
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u8 value;
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sr_read_reg(dev, NSR, &value);
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sr_read_reg(dev, SR_NSR, &value);
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if (value & NSR_LINKST)
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rc = 1;
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}
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@ -228,7 +228,7 @@ static u32 sr9700_get_link(struct net_device *netdev)
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int rc = 0;
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/* Get the Link Status directly */
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sr_read_reg(dev, NSR, &value);
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sr_read_reg(dev, SR_NSR, &value);
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if (value & NSR_LINKST)
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rc = 1;
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@ -281,8 +281,8 @@ static void sr9700_set_multicast(struct net_device *netdev)
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}
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}
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sr_write_async(dev, MAR, SR_MCAST_SIZE, hashes);
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sr_write_reg_async(dev, RCR, rx_ctl);
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sr_write_async(dev, SR_MAR, SR_MCAST_SIZE, hashes);
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sr_write_reg_async(dev, SR_RCR, rx_ctl);
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}
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static int sr9700_set_mac_address(struct net_device *netdev, void *p)
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@ -297,7 +297,7 @@ static int sr9700_set_mac_address(struct net_device *netdev, void *p)
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}
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memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
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sr_write_async(dev, PAR, 6, netdev->dev_addr);
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sr_write_async(dev, SR_PAR, 6, netdev->dev_addr);
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return 0;
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}
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@ -340,7 +340,7 @@ static int sr9700_bind(struct usbnet *dev, struct usb_interface *intf)
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mii->phy_id_mask = 0x1f;
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mii->reg_num_mask = 0x1f;
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sr_write_reg(dev, NCR, NCR_RST);
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sr_write_reg(dev, SR_NCR, NCR_RST);
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udelay(20);
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/* read MAC
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@ -348,17 +348,17 @@ static int sr9700_bind(struct usbnet *dev, struct usb_interface *intf)
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* EEPROM automatically to PAR. In case there is no EEPROM externally,
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* a default MAC address is stored in PAR for making chip work properly.
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*/
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if (sr_read(dev, PAR, ETH_ALEN, netdev->dev_addr) < 0) {
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if (sr_read(dev, SR_PAR, ETH_ALEN, netdev->dev_addr) < 0) {
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netdev_err(netdev, "Error reading MAC address\n");
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ret = -ENODEV;
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goto out;
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}
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/* power up and reset phy */
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sr_write_reg(dev, PRR, PRR_PHY_RST);
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sr_write_reg(dev, SR_PRR, PRR_PHY_RST);
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/* at least 10ms, here 20ms for safe */
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mdelay(20);
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sr_write_reg(dev, PRR, 0);
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sr_write_reg(dev, SR_PRR, 0);
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/* at least 1ms, here 2ms for reading right register */
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udelay(2 * 1000);
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@ -14,13 +14,13 @@
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/* sr9700 spec. register table on Linux platform */
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/* Network Control Reg */
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#define NCR 0x00
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#define SR_NCR 0x00
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#define NCR_RST (1 << 0)
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#define NCR_LBK (3 << 1)
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#define NCR_FDX (1 << 3)
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#define NCR_WAKEEN (1 << 6)
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/* Network Status Reg */
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#define NSR 0x01
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#define SR_NSR 0x01
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#define NSR_RXRDY (1 << 0)
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#define NSR_RXOV (1 << 1)
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#define NSR_TX1END (1 << 2)
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@ -30,7 +30,7 @@
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#define NSR_LINKST (1 << 6)
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#define NSR_SPEED (1 << 7)
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/* Tx Control Reg */
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#define TCR 0x02
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#define SR_TCR 0x02
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#define TCR_CRC_DIS (1 << 1)
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#define TCR_PAD_DIS (1 << 2)
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#define TCR_LC_CARE (1 << 3)
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@ -38,7 +38,7 @@
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#define TCR_EXCECM (1 << 5)
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#define TCR_LF_EN (1 << 6)
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/* Tx Status Reg for Packet Index 1 */
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#define TSR1 0x03
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#define SR_TSR1 0x03
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#define TSR1_EC (1 << 2)
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#define TSR1_COL (1 << 3)
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#define TSR1_LC (1 << 4)
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@ -46,7 +46,7 @@
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#define TSR1_LOC (1 << 6)
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#define TSR1_TLF (1 << 7)
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/* Tx Status Reg for Packet Index 2 */
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#define TSR2 0x04
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#define SR_TSR2 0x04
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#define TSR2_EC (1 << 2)
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#define TSR2_COL (1 << 3)
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#define TSR2_LC (1 << 4)
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@ -54,7 +54,7 @@
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#define TSR2_LOC (1 << 6)
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#define TSR2_TLF (1 << 7)
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/* Rx Control Reg*/
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#define RCR 0x05
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#define SR_RCR 0x05
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#define RCR_RXEN (1 << 0)
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#define RCR_PRMSC (1 << 1)
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#define RCR_RUNT (1 << 2)
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@ -62,87 +62,87 @@
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#define RCR_DIS_CRC (1 << 4)
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#define RCR_DIS_LONG (1 << 5)
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/* Rx Status Reg */
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#define RSR 0x06
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#define SR_RSR 0x06
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#define RSR_AE (1 << 2)
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#define RSR_MF (1 << 6)
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#define RSR_RF (1 << 7)
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/* Rx Overflow Counter Reg */
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#define ROCR 0x07
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#define SR_ROCR 0x07
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#define ROCR_ROC (0x7F << 0)
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#define ROCR_RXFU (1 << 7)
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/* Back Pressure Threshold Reg */
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#define BPTR 0x08
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#define SR_BPTR 0x08
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#define BPTR_JPT (0x0F << 0)
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#define BPTR_BPHW (0x0F << 4)
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/* Flow Control Threshold Reg */
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#define FCTR 0x09
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#define SR_FCTR 0x09
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#define FCTR_LWOT (0x0F << 0)
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#define FCTR_HWOT (0x0F << 4)
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/* rx/tx Flow Control Reg */
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#define FCR 0x0A
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#define SR_FCR 0x0A
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#define FCR_FLCE (1 << 0)
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#define FCR_BKPA (1 << 4)
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#define FCR_TXPEN (1 << 5)
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#define FCR_TXPF (1 << 6)
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#define FCR_TXP0 (1 << 7)
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/* Eeprom & Phy Control Reg */
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#define EPCR 0x0B
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#define SR_EPCR 0x0B
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#define EPCR_ERRE (1 << 0)
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#define EPCR_ERPRW (1 << 1)
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#define EPCR_ERPRR (1 << 2)
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#define EPCR_EPOS (1 << 3)
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#define EPCR_WEP (1 << 4)
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/* Eeprom & Phy Address Reg */
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#define EPAR 0x0C
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#define SR_EPAR 0x0C
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#define EPAR_EROA (0x3F << 0)
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#define EPAR_PHY_ADR_MASK (0x03 << 6)
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#define EPAR_PHY_ADR (0x01 << 6)
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/* Eeprom & Phy Data Reg */
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#define EPDR 0x0D /* 0x0D ~ 0x0E for Data Reg Low & High */
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#define SR_EPDR 0x0D /* 0x0D ~ 0x0E for Data Reg Low & High */
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/* Wakeup Control Reg */
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#define WCR 0x0F
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#define SR_WCR 0x0F
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#define WCR_MAGICST (1 << 0)
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#define WCR_LINKST (1 << 2)
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#define WCR_MAGICEN (1 << 3)
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#define WCR_LINKEN (1 << 5)
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/* Physical Address Reg */
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#define PAR 0x10 /* 0x10 ~ 0x15 6 bytes for PAR */
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#define SR_PAR 0x10 /* 0x10 ~ 0x15 6 bytes for PAR */
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/* Multicast Address Reg */
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#define MAR 0x16 /* 0x16 ~ 0x1D 8 bytes for MAR */
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#define SR_MAR 0x16 /* 0x16 ~ 0x1D 8 bytes for MAR */
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/* 0x1e unused */
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/* Phy Reset Reg */
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#define PRR 0x1F
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#define SR_PRR 0x1F
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#define PRR_PHY_RST (1 << 0)
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/* Tx sdram Write Pointer Address Low */
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#define TWPAL 0x20
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#define SR_TWPAL 0x20
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/* Tx sdram Write Pointer Address High */
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#define TWPAH 0x21
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#define SR_TWPAH 0x21
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/* Tx sdram Read Pointer Address Low */
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#define TRPAL 0x22
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#define SR_TRPAL 0x22
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/* Tx sdram Read Pointer Address High */
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#define TRPAH 0x23
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#define SR_TRPAH 0x23
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/* Rx sdram Write Pointer Address Low */
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#define RWPAL 0x24
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#define SR_RWPAL 0x24
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/* Rx sdram Write Pointer Address High */
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#define RWPAH 0x25
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#define SR_RWPAH 0x25
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/* Rx sdram Read Pointer Address Low */
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#define RRPAL 0x26
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#define SR_RRPAL 0x26
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/* Rx sdram Read Pointer Address High */
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#define RRPAH 0x27
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#define SR_RRPAH 0x27
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/* Vendor ID register */
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#define VID 0x28 /* 0x28 ~ 0x29 2 bytes for VID */
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#define SR_VID 0x28 /* 0x28 ~ 0x29 2 bytes for VID */
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/* Product ID register */
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#define PID 0x2A /* 0x2A ~ 0x2B 2 bytes for PID */
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#define SR_PID 0x2A /* 0x2A ~ 0x2B 2 bytes for PID */
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/* CHIP Revision register */
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#define CHIPR 0x2C
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#define SR_CHIPR 0x2C
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/* 0x2D --> 0xEF unused */
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/* USB Device Address */
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#define USBDA 0xF0
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#define SR_USBDA 0xF0
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#define USBDA_USBFA (0x7F << 0)
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/* RX packet Counter Reg */
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#define RXC 0xF1
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#define SR_RXC 0xF1
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/* Tx packet Counter & USB Status Reg */
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#define TXC_USBS 0xF2
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#define SR_TXC_USBS 0xF2
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#define TXC_USBS_TXC0 (1 << 0)
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#define TXC_USBS_TXC1 (1 << 1)
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#define TXC_USBS_TXC2 (1 << 2)
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@ -150,7 +150,7 @@
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#define TXC_USBS_SUSFLAG (1 << 6)
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#define TXC_USBS_RXFAULT (1 << 7)
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/* USB Control register */
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#define USBC 0xF4
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#define SR_USBC 0xF4
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#define USBC_EP3NAK (1 << 4)
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#define USBC_EP3ACK (1 << 5)
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