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clk: ti: omap5+: dpll: implement errata i810
Errata i810 states that DPLL controller can get stuck while transitioning to a power saving state, while its M/N ratio is being re-programmed. As a workaround, before re-programming the M/N ratio, SW has to ensure the DPLL cannot start an idle state transition. SW can disable DPLL idling by setting the DPLL AUTO_DPLL_MODE=0 or keeping a clock request active by setting a dependent clock domain in SW_WKUP. This errata impacts OMAP5 and DRA7 chips, so enable the errata for these. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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@ -225,5 +225,9 @@ void __init ti_clk_init_features(void)
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if (omap_rev() == OMAP3430_REV_ES1_0)
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features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM;
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/* Errata I810 for omap5 / dra7 */
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if (soc_is_omap54xx() || soc_is_dra7xx())
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features.flags |= TI_CLK_ERRATA_I810;
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ti_clk_setup_features(&features);
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}
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@ -305,8 +305,9 @@ static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n)
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static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
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{
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struct dpll_data *dd = clk->dpll_data;
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u8 dco, sd_div;
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u8 dco, sd_div, ai = 0;
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u32 v;
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bool errata_i810;
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/* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
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_omap3_noncore_dpll_bypass(clk);
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@ -350,6 +351,25 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
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v |= sd_div << __ffs(dd->sddiv_mask);
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}
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/*
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* Errata i810 - DPLL controller can get stuck while transitioning
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* to a power saving state. Software must ensure the DPLL can not
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* transition to a low power state while changing M/N values.
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* Easiest way to accomplish this is to prevent DPLL autoidle
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* before doing the M/N re-program.
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*/
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errata_i810 = ti_clk_get_features()->flags & TI_CLK_ERRATA_I810;
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if (errata_i810) {
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ai = omap3_dpll_autoidle_read(clk);
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if (ai) {
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omap3_dpll_deny_idle(clk);
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/* OCP barrier */
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omap3_dpll_autoidle_read(clk);
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}
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}
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ti_clk_ll_ops->clk_writel(v, dd->mult_div1_reg);
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/* Set 4X multiplier and low-power mode */
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@ -379,6 +399,9 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
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_omap3_noncore_dpll_lock(clk);
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if (errata_i810 && ai)
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omap3_dpll_allow_idle(clk);
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return 0;
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}
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@ -286,6 +286,7 @@ struct ti_clk_features {
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#define TI_CLK_DPLL_HAS_FREQSEL BIT(0)
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#define TI_CLK_DPLL4_DENY_REPROGRAM BIT(1)
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#define TI_CLK_DISABLE_CLKDM_CONTROL BIT(2)
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#define TI_CLK_ERRATA_I810 BIT(3)
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void ti_clk_setup_features(struct ti_clk_features *features);
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const struct ti_clk_features *ti_clk_get_features(void);
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