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powerpc: Remove oprofile RS64 support
We no longer support these cpus, so we don't need oprofile support for them either. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Michael Ellerman
Benjamin Herrenschmidt
parent
c3993f1007
commit
086dddc15f
@ -61,7 +61,6 @@ struct op_powerpc_model {
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};
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extern struct op_powerpc_model op_model_fsl_emb;
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extern struct op_powerpc_model op_model_rs64;
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extern struct op_powerpc_model op_model_power4;
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extern struct op_powerpc_model op_model_7450;
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extern struct op_powerpc_model op_model_cell;
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@ -14,6 +14,6 @@ oprofile-y := $(DRIVER_OBJS) common.o backtrace.o
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oprofile-$(CONFIG_OPROFILE_CELL) += op_model_cell.o \
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cell/spu_profiler.o cell/vma_map.o \
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cell/spu_task_sync.o
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oprofile-$(CONFIG_PPC_BOOK3S_64) += op_model_rs64.o op_model_power4.o op_model_pa6t.o
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oprofile-$(CONFIG_PPC_BOOK3S_64) += op_model_power4.o op_model_pa6t.o
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oprofile-$(CONFIG_FSL_EMB_PERFMON) += op_model_fsl_emb.o
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oprofile-$(CONFIG_6xx) += op_model_7450.o
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@ -205,9 +205,6 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
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ops->sync_stop = model->sync_stop;
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break;
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#endif
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case PPC_OPROFILE_RS64:
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model = &op_model_rs64;
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break;
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case PPC_OPROFILE_POWER4:
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model = &op_model_power4;
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break;
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@ -1,222 +0,0 @@
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/*
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* Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/oprofile.h>
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#include <linux/smp.h>
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#include <asm/ptrace.h>
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#include <asm/processor.h>
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#include <asm/cputable.h>
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#include <asm/oprofile_impl.h>
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#define dbg(args...)
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static void ctrl_write(unsigned int i, unsigned int val)
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{
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unsigned int tmp = 0;
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unsigned long shift = 0, mask = 0;
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dbg("ctrl_write %d %x\n", i, val);
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switch(i) {
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case 0:
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tmp = mfspr(SPRN_MMCR0);
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shift = 6;
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mask = 0x7F;
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break;
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case 1:
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tmp = mfspr(SPRN_MMCR0);
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shift = 0;
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mask = 0x3F;
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break;
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case 2:
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tmp = mfspr(SPRN_MMCR1);
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shift = 31 - 4;
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mask = 0x1F;
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break;
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case 3:
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tmp = mfspr(SPRN_MMCR1);
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shift = 31 - 9;
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mask = 0x1F;
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break;
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case 4:
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tmp = mfspr(SPRN_MMCR1);
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shift = 31 - 14;
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mask = 0x1F;
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break;
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case 5:
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tmp = mfspr(SPRN_MMCR1);
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shift = 31 - 19;
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mask = 0x1F;
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break;
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case 6:
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tmp = mfspr(SPRN_MMCR1);
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shift = 31 - 24;
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mask = 0x1F;
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break;
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case 7:
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tmp = mfspr(SPRN_MMCR1);
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shift = 31 - 28;
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mask = 0xF;
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break;
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}
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tmp = tmp & ~(mask << shift);
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tmp |= val << shift;
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switch(i) {
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case 0:
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case 1:
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mtspr(SPRN_MMCR0, tmp);
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break;
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default:
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mtspr(SPRN_MMCR1, tmp);
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}
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dbg("ctrl_write mmcr0 %lx mmcr1 %lx\n", mfspr(SPRN_MMCR0),
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mfspr(SPRN_MMCR1));
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}
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static unsigned long reset_value[OP_MAX_COUNTER];
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static int num_counters;
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static int rs64_reg_setup(struct op_counter_config *ctr,
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struct op_system_config *sys,
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int num_ctrs)
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{
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int i;
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num_counters = num_ctrs;
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for (i = 0; i < num_counters; ++i)
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reset_value[i] = 0x80000000UL - ctr[i].count;
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/* XXX setup user and kernel profiling */
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return 0;
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}
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static int rs64_cpu_setup(struct op_counter_config *ctr)
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{
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unsigned int mmcr0;
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/* reset MMCR0 and set the freeze bit */
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mmcr0 = MMCR0_FC;
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mtspr(SPRN_MMCR0, mmcr0);
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/* reset MMCR1, MMCRA */
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mtspr(SPRN_MMCR1, 0);
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if (cpu_has_feature(CPU_FTR_MMCRA))
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mtspr(SPRN_MMCRA, 0);
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mmcr0 |= MMCR0_FCM1|MMCR0_PMXE|MMCR0_FCECE;
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/* Only applies to POWER3, but should be safe on RS64 */
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mmcr0 |= MMCR0_PMC1CE|MMCR0_PMCjCE;
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mtspr(SPRN_MMCR0, mmcr0);
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dbg("setup on cpu %d, mmcr0 %lx\n", smp_processor_id(),
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mfspr(SPRN_MMCR0));
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dbg("setup on cpu %d, mmcr1 %lx\n", smp_processor_id(),
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mfspr(SPRN_MMCR1));
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return 0;
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}
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static int rs64_start(struct op_counter_config *ctr)
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{
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int i;
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unsigned int mmcr0;
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/* set the PMM bit (see comment below) */
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mtmsrd(mfmsr() | MSR_PMM);
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for (i = 0; i < num_counters; ++i) {
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if (ctr[i].enabled) {
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classic_ctr_write(i, reset_value[i]);
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ctrl_write(i, ctr[i].event);
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} else {
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classic_ctr_write(i, 0);
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}
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}
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mmcr0 = mfspr(SPRN_MMCR0);
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/*
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* now clear the freeze bit, counting will not start until we
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* rfid from this excetion, because only at that point will
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* the PMM bit be cleared
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*/
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mmcr0 &= ~MMCR0_FC;
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mtspr(SPRN_MMCR0, mmcr0);
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dbg("start on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
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return 0;
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}
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static void rs64_stop(void)
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{
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unsigned int mmcr0;
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/* freeze counters */
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mmcr0 = mfspr(SPRN_MMCR0);
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mmcr0 |= MMCR0_FC;
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mtspr(SPRN_MMCR0, mmcr0);
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dbg("stop on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
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mb();
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}
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static void rs64_handle_interrupt(struct pt_regs *regs,
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struct op_counter_config *ctr)
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{
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unsigned int mmcr0;
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int is_kernel;
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int val;
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int i;
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unsigned long pc = mfspr(SPRN_SIAR);
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is_kernel = is_kernel_addr(pc);
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/* set the PMM bit (see comment below) */
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mtmsrd(mfmsr() | MSR_PMM);
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for (i = 0; i < num_counters; ++i) {
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val = classic_ctr_read(i);
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if (val < 0) {
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if (ctr[i].enabled) {
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oprofile_add_ext_sample(pc, regs, i, is_kernel);
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classic_ctr_write(i, reset_value[i]);
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} else {
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classic_ctr_write(i, 0);
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}
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}
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}
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mmcr0 = mfspr(SPRN_MMCR0);
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/* reset the perfmon trigger */
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mmcr0 |= MMCR0_PMXE;
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/*
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* now clear the freeze bit, counting will not start until we
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* rfid from this exception, because only at that point will
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* the PMM bit be cleared
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*/
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mmcr0 &= ~MMCR0_FC;
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mtspr(SPRN_MMCR0, mmcr0);
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}
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struct op_powerpc_model op_model_rs64 = {
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.reg_setup = rs64_reg_setup,
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.cpu_setup = rs64_cpu_setup,
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.start = rs64_start,
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.stop = rs64_stop,
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.handle_interrupt = rs64_handle_interrupt,
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};
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