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staging: ccree: fix wrong whitespace usage
Some of the register definition files had none kernel coding style usage of tabs vs. spaces in macro definitions. This patch fixes them. Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Gilad Ben-Yossef
Greg Kroah-Hartman
parent
ee15d16946
commit
087fabd1cd
@ -20,161 +20,161 @@
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// --------------------------------------
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// BLOCK: DSCRPTR
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// --------------------------------------
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#define DX_DSCRPTR_COMPLETION_COUNTER_REG_OFFSET 0xE00UL
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#define DX_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SHIFT 0x0UL
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#define DX_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SIZE 0x6UL
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#define DX_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SHIFT 0x6UL
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#define DX_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_SW_RESET_REG_OFFSET 0xE40UL
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#define DX_DSCRPTR_SW_RESET_VALUE_BIT_SHIFT 0x0UL
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#define DX_DSCRPTR_SW_RESET_VALUE_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_SRAM_SIZE_REG_OFFSET 0xE60UL
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#define DX_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SHIFT 0x0UL
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#define DX_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SIZE 0xAUL
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#define DX_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SHIFT 0xAUL
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#define DX_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SIZE 0xCUL
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#define DX_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SHIFT 0x16UL
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#define DX_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SIZE 0x3UL
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#define DX_DSCRPTR_SINGLE_ADDR_EN_REG_OFFSET 0xE64UL
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#define DX_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SHIFT 0x0UL
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#define DX_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_MEASURE_CNTR_REG_OFFSET 0xE68UL
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#define DX_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SHIFT 0x0UL
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#define DX_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SIZE 0x20UL
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#define DX_DSCRPTR_QUEUE_WORD0_REG_OFFSET 0xE80UL
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#define DX_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SHIFT 0x0UL
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#define DX_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SIZE 0x20UL
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#define DX_DSCRPTR_QUEUE_WORD1_REG_OFFSET 0xE84UL
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#define DX_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SHIFT 0x0UL
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#define DX_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SIZE 0x2UL
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#define DX_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SHIFT 0x2UL
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#define DX_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SIZE 0x18UL
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#define DX_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SHIFT 0x1AUL
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#define DX_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SHIFT 0x1BUL
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#define DX_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SHIFT 0x1CUL
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#define DX_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SHIFT 0x1DUL
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#define DX_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SHIFT 0x1EUL
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#define DX_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SIZE 0x2UL
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#define DX_DSCRPTR_QUEUE_WORD2_REG_OFFSET 0xE88UL
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#define DX_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SHIFT 0x0UL
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#define DX_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SIZE 0x20UL
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#define DX_DSCRPTR_QUEUE_WORD3_REG_OFFSET 0xE8CUL
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#define DX_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SHIFT 0x0UL
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#define DX_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SIZE 0x2UL
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#define DX_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SHIFT 0x2UL
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#define DX_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SIZE 0x18UL
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#define DX_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SHIFT 0x1AUL
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#define DX_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SHIFT 0x1BUL
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#define DX_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SHIFT 0x1DUL
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#define DX_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SHIFT 0x1EUL
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#define DX_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SHIFT 0x1FUL
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#define DX_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD4_REG_OFFSET 0xE90UL
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#define DX_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SHIFT 0x0UL
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#define DX_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SIZE 0x6UL
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#define DX_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SHIFT 0x6UL
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#define DX_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SHIFT 0x7UL
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#define DX_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SHIFT 0x8UL
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#define DX_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SIZE 0x2UL
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#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_MODE_BIT_SHIFT 0xAUL
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#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_MODE_BIT_SIZE 0x4UL
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#define DX_DSCRPTR_QUEUE_WORD4_CMAC_SIZE0_BIT_SHIFT 0xEUL
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#define DX_DSCRPTR_QUEUE_WORD4_CMAC_SIZE0_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_DO_BIT_SHIFT 0xFUL
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#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_DO_BIT_SIZE 0x2UL
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#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF0_BIT_SHIFT 0x11UL
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#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF0_BIT_SIZE 0x2UL
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#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF1_BIT_SHIFT 0x13UL
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#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF1_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF2_BIT_SHIFT 0x14UL
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#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF2_BIT_SIZE 0x2UL
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#define DX_DSCRPTR_QUEUE_WORD4_KEY_SIZE_BIT_SHIFT 0x16UL
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#define DX_DSCRPTR_QUEUE_WORD4_KEY_SIZE_BIT_SIZE 0x2UL
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#define DX_DSCRPTR_QUEUE_WORD4_SETUP_OPERATION_BIT_SHIFT 0x18UL
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#define DX_DSCRPTR_QUEUE_WORD4_SETUP_OPERATION_BIT_SIZE 0x4UL
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#define DX_DSCRPTR_QUEUE_WORD4_DIN_SRAM_ENDIANNESS_BIT_SHIFT 0x1CUL
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#define DX_DSCRPTR_QUEUE_WORD4_DIN_SRAM_ENDIANNESS_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD4_DOUT_SRAM_ENDIANNESS_BIT_SHIFT 0x1DUL
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#define DX_DSCRPTR_QUEUE_WORD4_DOUT_SRAM_ENDIANNESS_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SHIFT 0x1EUL
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#define DX_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SHIFT 0x1FUL
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#define DX_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD5_REG_OFFSET 0xE94UL
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#define DX_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SHIFT 0x0UL
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#define DX_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SIZE 0x10UL
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#define DX_DSCRPTR_QUEUE_WORD5_DOUT_ADDR_HIGH_BIT_SHIFT 0x10UL
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#define DX_DSCRPTR_QUEUE_WORD5_DOUT_ADDR_HIGH_BIT_SIZE 0x10UL
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#define DX_DSCRPTR_QUEUE_WATERMARK_REG_OFFSET 0xE98UL
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#define DX_DSCRPTR_QUEUE_WATERMARK_VALUE_BIT_SHIFT 0x0UL
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#define DX_DSCRPTR_QUEUE_WATERMARK_VALUE_BIT_SIZE 0xAUL
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#define DX_DSCRPTR_QUEUE_CONTENT_REG_OFFSET 0xE9CUL
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#define DX_DSCRPTR_QUEUE_CONTENT_VALUE_BIT_SHIFT 0x0UL
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#define DX_DSCRPTR_QUEUE_CONTENT_VALUE_BIT_SIZE 0xAUL
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#define DX_DSCRPTR_COMPLETION_COUNTER_REG_OFFSET 0xE00UL
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#define DX_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SHIFT 0x0UL
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#define DX_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SIZE 0x6UL
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#define DX_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SHIFT 0x6UL
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#define DX_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_SW_RESET_REG_OFFSET 0xE40UL
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#define DX_DSCRPTR_SW_RESET_VALUE_BIT_SHIFT 0x0UL
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#define DX_DSCRPTR_SW_RESET_VALUE_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_SRAM_SIZE_REG_OFFSET 0xE60UL
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#define DX_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SHIFT 0x0UL
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#define DX_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SIZE 0xAUL
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#define DX_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SHIFT 0xAUL
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#define DX_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SIZE 0xCUL
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#define DX_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SHIFT 0x16UL
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#define DX_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SIZE 0x3UL
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#define DX_DSCRPTR_SINGLE_ADDR_EN_REG_OFFSET 0xE64UL
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#define DX_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SHIFT 0x0UL
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#define DX_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_MEASURE_CNTR_REG_OFFSET 0xE68UL
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#define DX_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SHIFT 0x0UL
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#define DX_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SIZE 0x20UL
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#define DX_DSCRPTR_QUEUE_WORD0_REG_OFFSET 0xE80UL
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#define DX_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SHIFT 0x0UL
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#define DX_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SIZE 0x20UL
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#define DX_DSCRPTR_QUEUE_WORD1_REG_OFFSET 0xE84UL
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#define DX_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SHIFT 0x0UL
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#define DX_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SIZE 0x2UL
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#define DX_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SHIFT 0x2UL
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#define DX_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SIZE 0x18UL
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#define DX_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SHIFT 0x1AUL
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#define DX_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SHIFT 0x1BUL
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#define DX_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SHIFT 0x1CUL
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#define DX_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SHIFT 0x1DUL
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#define DX_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SHIFT 0x1EUL
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#define DX_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SIZE 0x2UL
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#define DX_DSCRPTR_QUEUE_WORD2_REG_OFFSET 0xE88UL
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#define DX_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SHIFT 0x0UL
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#define DX_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SIZE 0x20UL
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#define DX_DSCRPTR_QUEUE_WORD3_REG_OFFSET 0xE8CUL
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#define DX_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SHIFT 0x0UL
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#define DX_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SIZE 0x2UL
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#define DX_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SHIFT 0x2UL
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#define DX_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SIZE 0x18UL
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#define DX_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SHIFT 0x1AUL
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#define DX_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SHIFT 0x1BUL
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#define DX_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SHIFT 0x1DUL
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#define DX_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SHIFT 0x1EUL
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#define DX_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SHIFT 0x1FUL
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#define DX_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD4_REG_OFFSET 0xE90UL
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#define DX_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SHIFT 0x0UL
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#define DX_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SIZE 0x6UL
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#define DX_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SHIFT 0x6UL
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#define DX_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SHIFT 0x7UL
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#define DX_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SHIFT 0x8UL
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#define DX_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SIZE 0x2UL
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#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_MODE_BIT_SHIFT 0xAUL
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#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_MODE_BIT_SIZE 0x4UL
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#define DX_DSCRPTR_QUEUE_WORD4_CMAC_SIZE0_BIT_SHIFT 0xEUL
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#define DX_DSCRPTR_QUEUE_WORD4_CMAC_SIZE0_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_DO_BIT_SHIFT 0xFUL
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#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_DO_BIT_SIZE 0x2UL
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#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF0_BIT_SHIFT 0x11UL
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#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF0_BIT_SIZE 0x2UL
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#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF1_BIT_SHIFT 0x13UL
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#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF1_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF2_BIT_SHIFT 0x14UL
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#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF2_BIT_SIZE 0x2UL
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#define DX_DSCRPTR_QUEUE_WORD4_KEY_SIZE_BIT_SHIFT 0x16UL
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#define DX_DSCRPTR_QUEUE_WORD4_KEY_SIZE_BIT_SIZE 0x2UL
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#define DX_DSCRPTR_QUEUE_WORD4_SETUP_OPERATION_BIT_SHIFT 0x18UL
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#define DX_DSCRPTR_QUEUE_WORD4_SETUP_OPERATION_BIT_SIZE 0x4UL
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#define DX_DSCRPTR_QUEUE_WORD4_DIN_SRAM_ENDIANNESS_BIT_SHIFT 0x1CUL
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#define DX_DSCRPTR_QUEUE_WORD4_DIN_SRAM_ENDIANNESS_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD4_DOUT_SRAM_ENDIANNESS_BIT_SHIFT 0x1DUL
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#define DX_DSCRPTR_QUEUE_WORD4_DOUT_SRAM_ENDIANNESS_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SHIFT 0x1EUL
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#define DX_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SHIFT 0x1FUL
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#define DX_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SIZE 0x1UL
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#define DX_DSCRPTR_QUEUE_WORD5_REG_OFFSET 0xE94UL
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#define DX_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SHIFT 0x0UL
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#define DX_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SIZE 0x10UL
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#define DX_DSCRPTR_QUEUE_WORD5_DOUT_ADDR_HIGH_BIT_SHIFT 0x10UL
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#define DX_DSCRPTR_QUEUE_WORD5_DOUT_ADDR_HIGH_BIT_SIZE 0x10UL
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#define DX_DSCRPTR_QUEUE_WATERMARK_REG_OFFSET 0xE98UL
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#define DX_DSCRPTR_QUEUE_WATERMARK_VALUE_BIT_SHIFT 0x0UL
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#define DX_DSCRPTR_QUEUE_WATERMARK_VALUE_BIT_SIZE 0xAUL
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#define DX_DSCRPTR_QUEUE_CONTENT_REG_OFFSET 0xE9CUL
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#define DX_DSCRPTR_QUEUE_CONTENT_VALUE_BIT_SHIFT 0x0UL
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#define DX_DSCRPTR_QUEUE_CONTENT_VALUE_BIT_SIZE 0xAUL
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// --------------------------------------
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// BLOCK: AXI_P
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// --------------------------------------
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#define DX_AXIM_MON_INFLIGHT_REG_OFFSET 0xB00UL
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#define DX_AXIM_MON_INFLIGHT_VALUE_BIT_SHIFT 0x0UL
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#define DX_AXIM_MON_INFLIGHT_VALUE_BIT_SIZE 0x8UL
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#define DX_AXIM_MON_INFLIGHTLAST_REG_OFFSET 0xB40UL
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#define DX_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SHIFT 0x0UL
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#define DX_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SIZE 0x8UL
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#define DX_AXIM_MON_COMP_REG_OFFSET 0xB80UL
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#define DX_AXIM_MON_COMP_VALUE_BIT_SHIFT 0x0UL
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#define DX_AXIM_MON_COMP_VALUE_BIT_SIZE 0x10UL
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#define DX_AXIM_MON_ERR_REG_OFFSET 0xBC4UL
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#define DX_AXIM_MON_ERR_BRESP_BIT_SHIFT 0x0UL
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#define DX_AXIM_MON_ERR_BRESP_BIT_SIZE 0x2UL
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#define DX_AXIM_MON_ERR_BID_BIT_SHIFT 0x2UL
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#define DX_AXIM_MON_ERR_BID_BIT_SIZE 0x4UL
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#define DX_AXIM_MON_ERR_RRESP_BIT_SHIFT 0x10UL
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#define DX_AXIM_MON_ERR_RRESP_BIT_SIZE 0x2UL
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#define DX_AXIM_MON_ERR_RID_BIT_SHIFT 0x12UL
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#define DX_AXIM_MON_ERR_RID_BIT_SIZE 0x4UL
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#define DX_AXIM_CFG_REG_OFFSET 0xBE8UL
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#define DX_AXIM_CFG_BRESPMASK_BIT_SHIFT 0x4UL
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#define DX_AXIM_CFG_BRESPMASK_BIT_SIZE 0x1UL
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#define DX_AXIM_CFG_RRESPMASK_BIT_SHIFT 0x5UL
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#define DX_AXIM_CFG_RRESPMASK_BIT_SIZE 0x1UL
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#define DX_AXIM_CFG_INFLTMASK_BIT_SHIFT 0x6UL
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||||
#define DX_AXIM_CFG_INFLTMASK_BIT_SIZE 0x1UL
|
||||
#define DX_AXIM_CFG_COMPMASK_BIT_SHIFT 0x7UL
|
||||
#define DX_AXIM_CFG_COMPMASK_BIT_SIZE 0x1UL
|
||||
#define DX_AXIM_ACE_CONST_REG_OFFSET 0xBECUL
|
||||
#define DX_AXIM_ACE_CONST_ARDOMAIN_BIT_SHIFT 0x0UL
|
||||
#define DX_AXIM_ACE_CONST_ARDOMAIN_BIT_SIZE 0x2UL
|
||||
#define DX_AXIM_ACE_CONST_AWDOMAIN_BIT_SHIFT 0x2UL
|
||||
#define DX_AXIM_ACE_CONST_AWDOMAIN_BIT_SIZE 0x2UL
|
||||
#define DX_AXIM_ACE_CONST_ARBAR_BIT_SHIFT 0x4UL
|
||||
#define DX_AXIM_ACE_CONST_ARBAR_BIT_SIZE 0x2UL
|
||||
#define DX_AXIM_ACE_CONST_AWBAR_BIT_SHIFT 0x6UL
|
||||
#define DX_AXIM_ACE_CONST_AWBAR_BIT_SIZE 0x2UL
|
||||
#define DX_AXIM_ACE_CONST_ARSNOOP_BIT_SHIFT 0x8UL
|
||||
#define DX_AXIM_ACE_CONST_ARSNOOP_BIT_SIZE 0x4UL
|
||||
#define DX_AXIM_ACE_CONST_AWSNOOP_NOT_ALIGNED_BIT_SHIFT 0xCUL
|
||||
#define DX_AXIM_ACE_CONST_AWSNOOP_NOT_ALIGNED_BIT_SIZE 0x3UL
|
||||
#define DX_AXIM_ACE_CONST_AWSNOOP_ALIGNED_BIT_SHIFT 0xFUL
|
||||
#define DX_AXIM_ACE_CONST_AWSNOOP_ALIGNED_BIT_SIZE 0x3UL
|
||||
#define DX_AXIM_ACE_CONST_AWADDR_NOT_MASKED_BIT_SHIFT 0x12UL
|
||||
#define DX_AXIM_ACE_CONST_AWADDR_NOT_MASKED_BIT_SIZE 0x7UL
|
||||
#define DX_AXIM_ACE_CONST_AWLEN_VAL_BIT_SHIFT 0x19UL
|
||||
#define DX_AXIM_ACE_CONST_AWLEN_VAL_BIT_SIZE 0x4UL
|
||||
#define DX_AXIM_CACHE_PARAMS_REG_OFFSET 0xBF0UL
|
||||
#define DX_AXIM_CACHE_PARAMS_AWCACHE_LAST_BIT_SHIFT 0x0UL
|
||||
#define DX_AXIM_CACHE_PARAMS_AWCACHE_LAST_BIT_SIZE 0x4UL
|
||||
#define DX_AXIM_CACHE_PARAMS_AWCACHE_BIT_SHIFT 0x4UL
|
||||
#define DX_AXIM_CACHE_PARAMS_AWCACHE_BIT_SIZE 0x4UL
|
||||
#define DX_AXIM_CACHE_PARAMS_ARCACHE_BIT_SHIFT 0x8UL
|
||||
#define DX_AXIM_CACHE_PARAMS_ARCACHE_BIT_SIZE 0x4UL
|
||||
#define DX_AXIM_MON_INFLIGHT_REG_OFFSET 0xB00UL
|
||||
#define DX_AXIM_MON_INFLIGHT_VALUE_BIT_SHIFT 0x0UL
|
||||
#define DX_AXIM_MON_INFLIGHT_VALUE_BIT_SIZE 0x8UL
|
||||
#define DX_AXIM_MON_INFLIGHTLAST_REG_OFFSET 0xB40UL
|
||||
#define DX_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SHIFT 0x0UL
|
||||
#define DX_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SIZE 0x8UL
|
||||
#define DX_AXIM_MON_COMP_REG_OFFSET 0xB80UL
|
||||
#define DX_AXIM_MON_COMP_VALUE_BIT_SHIFT 0x0UL
|
||||
#define DX_AXIM_MON_COMP_VALUE_BIT_SIZE 0x10UL
|
||||
#define DX_AXIM_MON_ERR_REG_OFFSET 0xBC4UL
|
||||
#define DX_AXIM_MON_ERR_BRESP_BIT_SHIFT 0x0UL
|
||||
#define DX_AXIM_MON_ERR_BRESP_BIT_SIZE 0x2UL
|
||||
#define DX_AXIM_MON_ERR_BID_BIT_SHIFT 0x2UL
|
||||
#define DX_AXIM_MON_ERR_BID_BIT_SIZE 0x4UL
|
||||
#define DX_AXIM_MON_ERR_RRESP_BIT_SHIFT 0x10UL
|
||||
#define DX_AXIM_MON_ERR_RRESP_BIT_SIZE 0x2UL
|
||||
#define DX_AXIM_MON_ERR_RID_BIT_SHIFT 0x12UL
|
||||
#define DX_AXIM_MON_ERR_RID_BIT_SIZE 0x4UL
|
||||
#define DX_AXIM_CFG_REG_OFFSET 0xBE8UL
|
||||
#define DX_AXIM_CFG_BRESPMASK_BIT_SHIFT 0x4UL
|
||||
#define DX_AXIM_CFG_BRESPMASK_BIT_SIZE 0x1UL
|
||||
#define DX_AXIM_CFG_RRESPMASK_BIT_SHIFT 0x5UL
|
||||
#define DX_AXIM_CFG_RRESPMASK_BIT_SIZE 0x1UL
|
||||
#define DX_AXIM_CFG_INFLTMASK_BIT_SHIFT 0x6UL
|
||||
#define DX_AXIM_CFG_INFLTMASK_BIT_SIZE 0x1UL
|
||||
#define DX_AXIM_CFG_COMPMASK_BIT_SHIFT 0x7UL
|
||||
#define DX_AXIM_CFG_COMPMASK_BIT_SIZE 0x1UL
|
||||
#define DX_AXIM_ACE_CONST_REG_OFFSET 0xBECUL
|
||||
#define DX_AXIM_ACE_CONST_ARDOMAIN_BIT_SHIFT 0x0UL
|
||||
#define DX_AXIM_ACE_CONST_ARDOMAIN_BIT_SIZE 0x2UL
|
||||
#define DX_AXIM_ACE_CONST_AWDOMAIN_BIT_SHIFT 0x2UL
|
||||
#define DX_AXIM_ACE_CONST_AWDOMAIN_BIT_SIZE 0x2UL
|
||||
#define DX_AXIM_ACE_CONST_ARBAR_BIT_SHIFT 0x4UL
|
||||
#define DX_AXIM_ACE_CONST_ARBAR_BIT_SIZE 0x2UL
|
||||
#define DX_AXIM_ACE_CONST_AWBAR_BIT_SHIFT 0x6UL
|
||||
#define DX_AXIM_ACE_CONST_AWBAR_BIT_SIZE 0x2UL
|
||||
#define DX_AXIM_ACE_CONST_ARSNOOP_BIT_SHIFT 0x8UL
|
||||
#define DX_AXIM_ACE_CONST_ARSNOOP_BIT_SIZE 0x4UL
|
||||
#define DX_AXIM_ACE_CONST_AWSNOOP_NOT_ALIGNED_BIT_SHIFT 0xCUL
|
||||
#define DX_AXIM_ACE_CONST_AWSNOOP_NOT_ALIGNED_BIT_SIZE 0x3UL
|
||||
#define DX_AXIM_ACE_CONST_AWSNOOP_ALIGNED_BIT_SHIFT 0xFUL
|
||||
#define DX_AXIM_ACE_CONST_AWSNOOP_ALIGNED_BIT_SIZE 0x3UL
|
||||
#define DX_AXIM_ACE_CONST_AWADDR_NOT_MASKED_BIT_SHIFT 0x12UL
|
||||
#define DX_AXIM_ACE_CONST_AWADDR_NOT_MASKED_BIT_SIZE 0x7UL
|
||||
#define DX_AXIM_ACE_CONST_AWLEN_VAL_BIT_SHIFT 0x19UL
|
||||
#define DX_AXIM_ACE_CONST_AWLEN_VAL_BIT_SIZE 0x4UL
|
||||
#define DX_AXIM_CACHE_PARAMS_REG_OFFSET 0xBF0UL
|
||||
#define DX_AXIM_CACHE_PARAMS_AWCACHE_LAST_BIT_SHIFT 0x0UL
|
||||
#define DX_AXIM_CACHE_PARAMS_AWCACHE_LAST_BIT_SIZE 0x4UL
|
||||
#define DX_AXIM_CACHE_PARAMS_AWCACHE_BIT_SHIFT 0x4UL
|
||||
#define DX_AXIM_CACHE_PARAMS_AWCACHE_BIT_SIZE 0x4UL
|
||||
#define DX_AXIM_CACHE_PARAMS_ARCACHE_BIT_SHIFT 0x8UL
|
||||
#define DX_AXIM_CACHE_PARAMS_ARCACHE_BIT_SIZE 0x4UL
|
||||
#endif // __DX_CRYS_KERNEL_H__
|
||||
|
||||
@ -20,136 +20,136 @@
|
||||
// --------------------------------------
|
||||
// BLOCK: HOST_P
|
||||
// --------------------------------------
|
||||
#define DX_HOST_IRR_REG_OFFSET 0xA00UL
|
||||
#define DX_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SHIFT 0x2UL
|
||||
#define DX_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_IRR_AXI_ERR_INT_BIT_SHIFT 0x8UL
|
||||
#define DX_HOST_IRR_AXI_ERR_INT_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_IRR_GPR0_BIT_SHIFT 0xBUL
|
||||
#define DX_HOST_IRR_GPR0_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SHIFT 0x13UL
|
||||
#define DX_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT 0x17UL
|
||||
#define DX_HOST_IRR_AXIM_COMP_INT_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_IMR_REG_OFFSET 0xA04UL
|
||||
#define DX_HOST_IMR_NOT_USED_MASK_BIT_SHIFT 0x1UL
|
||||
#define DX_HOST_IMR_NOT_USED_MASK_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SHIFT 0x2UL
|
||||
#define DX_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_IMR_AXI_ERR_MASK_BIT_SHIFT 0x8UL
|
||||
#define DX_HOST_IMR_AXI_ERR_MASK_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_IMR_GPR0_BIT_SHIFT 0xBUL
|
||||
#define DX_HOST_IMR_GPR0_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SHIFT 0x13UL
|
||||
#define DX_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SHIFT 0x17UL
|
||||
#define DX_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_ICR_REG_OFFSET 0xA08UL
|
||||
#define DX_HOST_ICR_DSCRPTR_COMPLETION_BIT_SHIFT 0x2UL
|
||||
#define DX_HOST_ICR_DSCRPTR_COMPLETION_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_ICR_AXI_ERR_CLEAR_BIT_SHIFT 0x8UL
|
||||
#define DX_HOST_ICR_AXI_ERR_CLEAR_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_ICR_GPR_INT_CLEAR_BIT_SHIFT 0xBUL
|
||||
#define DX_HOST_ICR_GPR_INT_CLEAR_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SHIFT 0x13UL
|
||||
#define DX_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SHIFT 0x17UL
|
||||
#define DX_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_SIGNATURE_REG_OFFSET 0xA24UL
|
||||
#define DX_HOST_SIGNATURE_VALUE_BIT_SHIFT 0x0UL
|
||||
#define DX_HOST_SIGNATURE_VALUE_BIT_SIZE 0x20UL
|
||||
#define DX_HOST_BOOT_REG_OFFSET 0xA28UL
|
||||
#define DX_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SHIFT 0x0UL
|
||||
#define DX_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SHIFT 0x1UL
|
||||
#define DX_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SHIFT 0x2UL
|
||||
#define DX_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SHIFT 0x3UL
|
||||
#define DX_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SHIFT 0x5UL
|
||||
#define DX_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SHIFT 0x6UL
|
||||
#define DX_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SIZE 0x3UL
|
||||
#define DX_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SHIFT 0x9UL
|
||||
#define DX_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SHIFT 0xAUL
|
||||
#define DX_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SHIFT 0xBUL
|
||||
#define DX_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SHIFT 0xCUL
|
||||
#define DX_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SHIFT 0xDUL
|
||||
#define DX_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SHIFT 0xEUL
|
||||
#define DX_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SHIFT 0xFUL
|
||||
#define DX_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SHIFT 0x10UL
|
||||
#define DX_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SHIFT 0x11UL
|
||||
#define DX_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SHIFT 0x12UL
|
||||
#define DX_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SHIFT 0x13UL
|
||||
#define DX_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SHIFT 0x14UL
|
||||
#define DX_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SHIFT 0x15UL
|
||||
#define DX_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SHIFT 0x16UL
|
||||
#define DX_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SHIFT 0x17UL
|
||||
#define DX_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SHIFT 0x18UL
|
||||
#define DX_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SHIFT 0x19UL
|
||||
#define DX_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SHIFT 0x1AUL
|
||||
#define DX_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SHIFT 0x1BUL
|
||||
#define DX_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SHIFT 0x1CUL
|
||||
#define DX_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SHIFT 0x1DUL
|
||||
#define DX_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SHIFT 0x1EUL
|
||||
#define DX_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_VERSION_REG_OFFSET 0xA40UL
|
||||
#define DX_HOST_VERSION_VALUE_BIT_SHIFT 0x0UL
|
||||
#define DX_HOST_VERSION_VALUE_BIT_SIZE 0x20UL
|
||||
#define DX_HOST_KFDE0_VALID_REG_OFFSET 0xA60UL
|
||||
#define DX_HOST_KFDE0_VALID_VALUE_BIT_SHIFT 0x0UL
|
||||
#define DX_HOST_KFDE0_VALID_VALUE_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_KFDE1_VALID_REG_OFFSET 0xA64UL
|
||||
#define DX_HOST_KFDE1_VALID_VALUE_BIT_SHIFT 0x0UL
|
||||
#define DX_HOST_KFDE1_VALID_VALUE_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_KFDE2_VALID_REG_OFFSET 0xA68UL
|
||||
#define DX_HOST_KFDE2_VALID_VALUE_BIT_SHIFT 0x0UL
|
||||
#define DX_HOST_KFDE2_VALID_VALUE_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_KFDE3_VALID_REG_OFFSET 0xA6CUL
|
||||
#define DX_HOST_KFDE3_VALID_VALUE_BIT_SHIFT 0x0UL
|
||||
#define DX_HOST_KFDE3_VALID_VALUE_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_GPR0_REG_OFFSET 0xA70UL
|
||||
#define DX_HOST_GPR0_VALUE_BIT_SHIFT 0x0UL
|
||||
#define DX_HOST_GPR0_VALUE_BIT_SIZE 0x20UL
|
||||
#define DX_GPR_HOST_REG_OFFSET 0xA74UL
|
||||
#define DX_GPR_HOST_VALUE_BIT_SHIFT 0x0UL
|
||||
#define DX_GPR_HOST_VALUE_BIT_SIZE 0x20UL
|
||||
#define DX_HOST_POWER_DOWN_EN_REG_OFFSET 0xA78UL
|
||||
#define DX_HOST_POWER_DOWN_EN_VALUE_BIT_SHIFT 0x0UL
|
||||
#define DX_HOST_POWER_DOWN_EN_VALUE_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_IRR_REG_OFFSET 0xA00UL
|
||||
#define DX_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SHIFT 0x2UL
|
||||
#define DX_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_IRR_AXI_ERR_INT_BIT_SHIFT 0x8UL
|
||||
#define DX_HOST_IRR_AXI_ERR_INT_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_IRR_GPR0_BIT_SHIFT 0xBUL
|
||||
#define DX_HOST_IRR_GPR0_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SHIFT 0x13UL
|
||||
#define DX_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT 0x17UL
|
||||
#define DX_HOST_IRR_AXIM_COMP_INT_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_IMR_REG_OFFSET 0xA04UL
|
||||
#define DX_HOST_IMR_NOT_USED_MASK_BIT_SHIFT 0x1UL
|
||||
#define DX_HOST_IMR_NOT_USED_MASK_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SHIFT 0x2UL
|
||||
#define DX_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_IMR_AXI_ERR_MASK_BIT_SHIFT 0x8UL
|
||||
#define DX_HOST_IMR_AXI_ERR_MASK_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_IMR_GPR0_BIT_SHIFT 0xBUL
|
||||
#define DX_HOST_IMR_GPR0_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SHIFT 0x13UL
|
||||
#define DX_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SHIFT 0x17UL
|
||||
#define DX_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_ICR_REG_OFFSET 0xA08UL
|
||||
#define DX_HOST_ICR_DSCRPTR_COMPLETION_BIT_SHIFT 0x2UL
|
||||
#define DX_HOST_ICR_DSCRPTR_COMPLETION_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_ICR_AXI_ERR_CLEAR_BIT_SHIFT 0x8UL
|
||||
#define DX_HOST_ICR_AXI_ERR_CLEAR_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_ICR_GPR_INT_CLEAR_BIT_SHIFT 0xBUL
|
||||
#define DX_HOST_ICR_GPR_INT_CLEAR_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SHIFT 0x13UL
|
||||
#define DX_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SHIFT 0x17UL
|
||||
#define DX_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_SIGNATURE_REG_OFFSET 0xA24UL
|
||||
#define DX_HOST_SIGNATURE_VALUE_BIT_SHIFT 0x0UL
|
||||
#define DX_HOST_SIGNATURE_VALUE_BIT_SIZE 0x20UL
|
||||
#define DX_HOST_BOOT_REG_OFFSET 0xA28UL
|
||||
#define DX_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SHIFT 0x0UL
|
||||
#define DX_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SHIFT 0x1UL
|
||||
#define DX_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SHIFT 0x2UL
|
||||
#define DX_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SHIFT 0x3UL
|
||||
#define DX_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SHIFT 0x5UL
|
||||
#define DX_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SHIFT 0x6UL
|
||||
#define DX_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SIZE 0x3UL
|
||||
#define DX_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SHIFT 0x9UL
|
||||
#define DX_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SHIFT 0xAUL
|
||||
#define DX_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SHIFT 0xBUL
|
||||
#define DX_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SHIFT 0xCUL
|
||||
#define DX_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SHIFT 0xDUL
|
||||
#define DX_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SHIFT 0xEUL
|
||||
#define DX_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SHIFT 0xFUL
|
||||
#define DX_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SHIFT 0x10UL
|
||||
#define DX_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SHIFT 0x11UL
|
||||
#define DX_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SHIFT 0x12UL
|
||||
#define DX_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SHIFT 0x13UL
|
||||
#define DX_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SHIFT 0x14UL
|
||||
#define DX_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SHIFT 0x15UL
|
||||
#define DX_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SHIFT 0x16UL
|
||||
#define DX_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SHIFT 0x17UL
|
||||
#define DX_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SHIFT 0x18UL
|
||||
#define DX_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SHIFT 0x19UL
|
||||
#define DX_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SHIFT 0x1AUL
|
||||
#define DX_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SHIFT 0x1BUL
|
||||
#define DX_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SHIFT 0x1CUL
|
||||
#define DX_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SHIFT 0x1DUL
|
||||
#define DX_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SHIFT 0x1EUL
|
||||
#define DX_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_VERSION_REG_OFFSET 0xA40UL
|
||||
#define DX_HOST_VERSION_VALUE_BIT_SHIFT 0x0UL
|
||||
#define DX_HOST_VERSION_VALUE_BIT_SIZE 0x20UL
|
||||
#define DX_HOST_KFDE0_VALID_REG_OFFSET 0xA60UL
|
||||
#define DX_HOST_KFDE0_VALID_VALUE_BIT_SHIFT 0x0UL
|
||||
#define DX_HOST_KFDE0_VALID_VALUE_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_KFDE1_VALID_REG_OFFSET 0xA64UL
|
||||
#define DX_HOST_KFDE1_VALID_VALUE_BIT_SHIFT 0x0UL
|
||||
#define DX_HOST_KFDE1_VALID_VALUE_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_KFDE2_VALID_REG_OFFSET 0xA68UL
|
||||
#define DX_HOST_KFDE2_VALID_VALUE_BIT_SHIFT 0x0UL
|
||||
#define DX_HOST_KFDE2_VALID_VALUE_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_KFDE3_VALID_REG_OFFSET 0xA6CUL
|
||||
#define DX_HOST_KFDE3_VALID_VALUE_BIT_SHIFT 0x0UL
|
||||
#define DX_HOST_KFDE3_VALID_VALUE_BIT_SIZE 0x1UL
|
||||
#define DX_HOST_GPR0_REG_OFFSET 0xA70UL
|
||||
#define DX_HOST_GPR0_VALUE_BIT_SHIFT 0x0UL
|
||||
#define DX_HOST_GPR0_VALUE_BIT_SIZE 0x20UL
|
||||
#define DX_GPR_HOST_REG_OFFSET 0xA74UL
|
||||
#define DX_GPR_HOST_VALUE_BIT_SHIFT 0x0UL
|
||||
#define DX_GPR_HOST_VALUE_BIT_SIZE 0x20UL
|
||||
#define DX_HOST_POWER_DOWN_EN_REG_OFFSET 0xA78UL
|
||||
#define DX_HOST_POWER_DOWN_EN_VALUE_BIT_SHIFT 0x0UL
|
||||
#define DX_HOST_POWER_DOWN_EN_VALUE_BIT_SIZE 0x1UL
|
||||
// --------------------------------------
|
||||
// BLOCK: HOST_SRAM
|
||||
// --------------------------------------
|
||||
#define DX_SRAM_DATA_REG_OFFSET 0xF00UL
|
||||
#define DX_SRAM_DATA_VALUE_BIT_SHIFT 0x0UL
|
||||
#define DX_SRAM_DATA_VALUE_BIT_SIZE 0x20UL
|
||||
#define DX_SRAM_ADDR_REG_OFFSET 0xF04UL
|
||||
#define DX_SRAM_ADDR_VALUE_BIT_SHIFT 0x0UL
|
||||
#define DX_SRAM_ADDR_VALUE_BIT_SIZE 0xFUL
|
||||
#define DX_SRAM_DATA_READY_REG_OFFSET 0xF08UL
|
||||
#define DX_SRAM_DATA_READY_VALUE_BIT_SHIFT 0x0UL
|
||||
#define DX_SRAM_DATA_READY_VALUE_BIT_SIZE 0x1UL
|
||||
#define DX_SRAM_DATA_REG_OFFSET 0xF00UL
|
||||
#define DX_SRAM_DATA_VALUE_BIT_SHIFT 0x0UL
|
||||
#define DX_SRAM_DATA_VALUE_BIT_SIZE 0x20UL
|
||||
#define DX_SRAM_ADDR_REG_OFFSET 0xF04UL
|
||||
#define DX_SRAM_ADDR_VALUE_BIT_SHIFT 0x0UL
|
||||
#define DX_SRAM_ADDR_VALUE_BIT_SIZE 0xFUL
|
||||
#define DX_SRAM_DATA_READY_REG_OFFSET 0xF08UL
|
||||
#define DX_SRAM_DATA_READY_VALUE_BIT_SHIFT 0x0UL
|
||||
#define DX_SRAM_DATA_READY_VALUE_BIT_SIZE 0x1UL
|
||||
|
||||
#endif //__DX_HOST_H__
|
||||
|
||||
Loading…
Reference in New Issue
Block a user