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[TG3]: Add mailbox read method
This patch adds the mailbox read method and also adds an inline function tw32_mailbox_f() for mailbox writes that require read flush. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -366,6 +366,12 @@ static void _tw32_flush(struct tg3 *tp, u32 off, u32 val)
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}
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}
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static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
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{
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tp->write32_mbox(tp, off, val);
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tp->read32_mbox(tp, off);
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}
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static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
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{
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void __iomem *mbox = tp->regs + off;
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@ -387,8 +393,10 @@ static u32 tg3_read32(struct tg3 *tp, u32 off)
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}
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#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
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#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
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#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
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#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
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#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
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#define tw32(reg,val) tp->write32(tp, reg, val)
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#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val))
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@ -420,8 +428,7 @@ static void tg3_disable_ints(struct tg3 *tp)
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{
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tw32(TG3PCI_MISC_HOST_CTRL,
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(tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
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tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
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tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
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tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
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}
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static inline void tg3_cond_int(struct tg3 *tp)
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@ -437,9 +444,8 @@ static void tg3_enable_ints(struct tg3 *tp)
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tw32(TG3PCI_MISC_HOST_CTRL,
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(tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
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tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
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(tp->last_tag << 24));
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tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
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tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
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(tp->last_tag << 24));
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tg3_cond_int(tp);
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}
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@ -3276,9 +3282,8 @@ static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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/* No work, shared interrupt perhaps? re-enable
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* interrupts, and flush that PCI write
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*/
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tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
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tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
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0x00000000);
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tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
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}
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} else { /* shared interrupt */
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handled = 0;
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@ -3321,9 +3326,8 @@ static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id, struct pt_regs *r
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/* no work, shared interrupt perhaps? re-enable
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* interrupts, and flush that PCI write
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*/
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tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
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tp->last_tag << 24);
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tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
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tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
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tp->last_tag << 24);
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}
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} else { /* shared interrupt */
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handled = 0;
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@ -5800,8 +5804,7 @@ static int tg3_reset_hw(struct tg3 *tp)
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tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
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udelay(100);
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tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
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tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
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tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
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tp->last_tag = 0;
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if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
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@ -6190,7 +6193,8 @@ static int tg3_test_interrupt(struct tg3 *tp)
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HOSTCC_MODE_NOW);
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for (i = 0; i < 5; i++) {
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int_mbox = tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
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int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
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TG3_64BIT_REG_LOW);
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if (int_mbox != 0)
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break;
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msleep(10);
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@ -6590,10 +6594,10 @@ static int tg3_open(struct net_device *dev)
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/* Mailboxes */
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printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
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tr32(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
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tr32(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
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tr32(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
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tr32(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
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tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
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tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
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tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
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tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
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/* NIC side send descriptors. */
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for (i = 0; i < 6; i++) {
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@ -7893,7 +7897,7 @@ static int tg3_test_loopback(struct tg3 *tp)
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num_pkts++;
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tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, send_idx);
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tr32(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
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tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
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udelay(10);
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@ -9320,6 +9324,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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/* Default fast path register access methods */
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tp->read32 = tg3_read32;
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tp->write32 = tg3_write32;
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tp->read32_mbox = tg3_read32;
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tp->write32_mbox = tg3_write32;
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tp->write32_tx_mbox = tg3_write32;
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tp->write32_rx_mbox = tg3_write32;
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@ -2051,6 +2051,7 @@ struct tg3 {
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u32 (*read32) (struct tg3 *, u32);
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void (*write32) (struct tg3 *, u32, u32);
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u32 (*read32_mbox) (struct tg3 *, u32);
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void (*write32_mbox) (struct tg3 *, u32,
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u32);
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void __iomem *regs;
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