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ARM: orion5x: use fixed PCI i/o mapping

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Move orion5x PCI to fixed i/o mapping and remove io.h.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Lennert Buytenhek <kernel@wantstofly.org>
Acked-by: Nicolas Pitre <nico@linaro.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Rob Herring 2012-07-06 10:59:30 -05:00
parent 2bb080851a
commit 0a4b8c6546
5 changed files with 27 additions and 82 deletions
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1
arch/arm/Kconfig
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@ -585,7 +585,6 @@ config ARCH_ORION5X
select PCI select PCI
select ARCH_REQUIRE_GPIOLIB select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select NEED_MACH_IO_H
select PLAT_ORION select PLAT_ORION
help help
Support for the following Marvell Orion 5x series SoCs: Support for the following Marvell Orion 5x series SoCs:

10
arch/arm/mach-orion5x/common.c
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@ -46,16 +46,6 @@ static struct map_desc orion5x_io_desc[] __initdata = {
.pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
.length = ORION5X_REGS_SIZE, .length = ORION5X_REGS_SIZE,
.type = MT_DEVICE, .type = MT_DEVICE,
}, {
.virtual = ORION5X_PCIE_IO_VIRT_BASE,
.pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
.length = ORION5X_PCIE_IO_SIZE,
.type = MT_DEVICE,
}, {
.virtual = ORION5X_PCI_IO_VIRT_BASE,
.pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
.length = ORION5X_PCI_IO_SIZE,
.type = MT_DEVICE,
}, { }, {
.virtual = ORION5X_PCIE_WA_VIRT_BASE, .virtual = ORION5X_PCIE_WA_VIRT_BASE,
.pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),

22
arch/arm/mach-orion5x/include/mach/io.h
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@ -1,22 +0,0 @@
/*
* arch/arm/mach-orion5x/include/mach/io.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_IO_H
#define __ASM_ARCH_IO_H
#include <mach/orion5x.h>
#include <asm/sizes.h>
#define IO_SPACE_LIMIT SZ_2M
static inline void __iomem *__io(unsigned long addr)
{
return (void __iomem *)(addr + ORION5X_PCIE_IO_VIRT_BASE);
}
#define __io(a) __io(a)
#endif

20
arch/arm/mach-orion5x/include/mach/orion5x.h
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@ -31,31 +31,29 @@
* fc000000 device bus mappings (cs0/cs1) * fc000000 device bus mappings (cs0/cs1)
* *
* virt phys size * virt phys size
* fdd00000 f1000000 1M on-chip peripheral registers * fe000000 f1000000 1M on-chip peripheral registers
* fde00000 f2000000 1M PCIe I/O space * fee00000 f2000000 64K PCIe I/O space
* fdf00000 f2100000 1M PCI I/O space * fee10000 f2100000 64K PCI I/O space
* fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) * fd000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only)
****************************************************************************/ ****************************************************************************/
#define ORION5X_REGS_PHYS_BASE 0xf1000000 #define ORION5X_REGS_PHYS_BASE 0xf1000000
#define ORION5X_REGS_VIRT_BASE 0xfdd00000 #define ORION5X_REGS_VIRT_BASE 0xfe000000
#define ORION5X_REGS_SIZE SZ_1M #define ORION5X_REGS_SIZE SZ_1M
#define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000 #define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000
#define ORION5X_PCIE_IO_VIRT_BASE 0xfde00000
#define ORION5X_PCIE_IO_BUS_BASE 0x00000000 #define ORION5X_PCIE_IO_BUS_BASE 0x00000000
#define ORION5X_PCIE_IO_SIZE SZ_1M #define ORION5X_PCIE_IO_SIZE SZ_64K
#define ORION5X_PCI_IO_PHYS_BASE 0xf2100000 #define ORION5X_PCI_IO_PHYS_BASE 0xf2100000
#define ORION5X_PCI_IO_VIRT_BASE 0xfdf00000 #define ORION5X_PCI_IO_BUS_BASE 0x00010000
#define ORION5X_PCI_IO_BUS_BASE 0x00100000 #define ORION5X_PCI_IO_SIZE SZ_64K
#define ORION5X_PCI_IO_SIZE SZ_1M
#define ORION5X_SRAM_PHYS_BASE (0xf2200000) #define ORION5X_SRAM_PHYS_BASE (0xf2200000)
#define ORION5X_SRAM_SIZE SZ_8K #define ORION5X_SRAM_SIZE SZ_8K
/* Relevant only for Orion-1/Orion-NAS */ /* Relevant only for Orion-1/Orion-NAS */
#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 #define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
#define ORION5X_PCIE_WA_VIRT_BASE 0xfe000000 #define ORION5X_PCIE_WA_VIRT_BASE 0xfd000000
#define ORION5X_PCIE_WA_SIZE SZ_16M #define ORION5X_PCIE_WA_SIZE SZ_16M
#define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000 #define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000

56
arch/arm/mach-orion5x/pci.c
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@ -162,35 +162,25 @@ static int __init pcie_setup(struct pci_sys_data *sys)
pcie_ops.read = pcie_rd_conf_wa; pcie_ops.read = pcie_rd_conf_wa;
} }
pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCIE_IO_PHYS_BASE);
/* /*
* Request resources. * Request resources.
*/ */
res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); res = kzalloc(sizeof(struct resource), GFP_KERNEL);
if (!res) if (!res)
panic("pcie_setup unable to alloc resources"); panic("pcie_setup unable to alloc resources");
/*
* IORESOURCE_IO
*/
sys->io_offset = 0;
res[0].name = "PCIe I/O Space";
res[0].flags = IORESOURCE_IO;
res[0].start = ORION5X_PCIE_IO_BUS_BASE;
res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1;
if (request_resource(&ioport_resource, &res[0]))
panic("Request PCIe IO resource failed\n");
pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
/* /*
* IORESOURCE_MEM * IORESOURCE_MEM
*/ */
res[1].name = "PCIe Memory Space"; res->name = "PCIe Memory Space";
res[1].flags = IORESOURCE_MEM; res->flags = IORESOURCE_MEM;
res[1].start = ORION5X_PCIE_MEM_PHYS_BASE; res->start = ORION5X_PCIE_MEM_PHYS_BASE;
res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1; res->end = res->start + ORION5X_PCIE_MEM_SIZE - 1;
if (request_resource(&iomem_resource, &res[1])) if (request_resource(&iomem_resource, res))
panic("Request PCIe Memory resource failed\n"); panic("Request PCIe Memory resource failed\n");
pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
return 1; return 1;
} }
@ -489,35 +479,25 @@ static int __init pci_setup(struct pci_sys_data *sys)
*/ */
orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCI_IO_PHYS_BASE);
/* /*
* Request resources * Request resources
*/ */
res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); res = kzalloc(sizeof(struct resource), GFP_KERNEL);
if (!res) if (!res)
panic("pci_setup unable to alloc resources"); panic("pci_setup unable to alloc resources");
/*
* IORESOURCE_IO
*/
sys->io_offset = 0;
res[0].name = "PCI I/O Space";
res[0].flags = IORESOURCE_IO;
res[0].start = ORION5X_PCI_IO_BUS_BASE;
res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1;
if (request_resource(&ioport_resource, &res[0]))
panic("Request PCI IO resource failed\n");
pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
/* /*
* IORESOURCE_MEM * IORESOURCE_MEM
*/ */
res[1].name = "PCI Memory Space"; res->name = "PCI Memory Space";
res[1].flags = IORESOURCE_MEM; res->flags = IORESOURCE_MEM;
res[1].start = ORION5X_PCI_MEM_PHYS_BASE; res->start = ORION5X_PCI_MEM_PHYS_BASE;
res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1; res->end = res->start + ORION5X_PCI_MEM_SIZE - 1;
if (request_resource(&iomem_resource, &res[1])) if (request_resource(&iomem_resource, res))
panic("Request PCI Memory resource failed\n"); panic("Request PCI Memory resource failed\n");
pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
return 1; return 1;
} }