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Merge branch 'r8169-add-and-use-helper-rtl_is_8168evl_up'
Heiner Kallweit says: ==================== r8169: add and use helper rtl_is_8168evl_up Few registers have been added or changed its purpose with version RTL8168e-vl, so create a helper for identifying chip versions from RTL8168e-vl. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
0b55b63035
@ -724,6 +724,12 @@ static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
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PCI_EXP_DEVCTL_READRQ, force);
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}
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static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
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{
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return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
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tp->mac_version != RTL_GIGA_MAC_VER_39;
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}
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struct rtl_cond {
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bool (*check)(struct rtl8169_private *);
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const char *msg;
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@ -1389,9 +1395,7 @@ static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
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rtl_unlock_config_regs(tp);
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switch (tp->mac_version) {
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case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
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case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
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if (rtl_is_8168evl_up(tp)) {
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tmp = ARRAY_SIZE(cfg) - 1;
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if (wolopts & WAKE_MAGIC)
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rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
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@ -1399,10 +1403,8 @@ static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
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else
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rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
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MagicPacket_v2);
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break;
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default:
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} else {
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tmp = ARRAY_SIZE(cfg);
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break;
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}
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for (i = 0; i < tmp; i++) {
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@ -4101,8 +4103,7 @@ static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
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u32 val = TX_DMA_BURST << TxDMAShift |
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InterFrameGap << TxInterFrameGapShift;
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if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
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tp->mac_version != RTL_GIGA_MAC_VER_39)
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if (rtl_is_8168evl_up(tp))
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val |= TXCFG_AUTO_FIFO;
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RTL_W32(tp, TxConfig, val);
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@ -4330,8 +4331,6 @@ static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
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{
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rtl_hw_start_8168bb(tp);
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RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
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RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
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}
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@ -4383,8 +4382,6 @@ static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
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/* Magic. */
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RTL_W8(tp, DBG_REG, 0x20);
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RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
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if (tp->dev->mtu <= ETH_DATA_LEN)
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rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
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}
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@ -4438,8 +4435,6 @@ static void rtl_hw_start_8168d(struct rtl8169_private *tp)
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rtl_disable_clock_request(tp);
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RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
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if (tp->dev->mtu <= ETH_DATA_LEN)
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rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
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}
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@ -4451,8 +4446,6 @@ static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
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if (tp->dev->mtu <= ETH_DATA_LEN)
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rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
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RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
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rtl_disable_clock_request(tp);
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}
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@ -4468,8 +4461,6 @@ static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
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rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
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RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
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rtl_ephy_init(tp, e_info_8168d_4);
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rtl_enable_clock_request(tp);
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@ -4500,8 +4491,6 @@ static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
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if (tp->dev->mtu <= ETH_DATA_LEN)
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rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
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RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
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rtl_disable_clock_request(tp);
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/* Reset tx FIFO pointer */
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@ -4533,8 +4522,6 @@ static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
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rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
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rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
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RTL_W8(tp, MaxTxPacketSize, EarlySize);
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rtl_disable_clock_request(tp);
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RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
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@ -4563,8 +4550,6 @@ static void rtl_hw_start_8168f(struct rtl8169_private *tp)
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rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
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rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
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RTL_W8(tp, MaxTxPacketSize, EarlySize);
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rtl_disable_clock_request(tp);
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RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
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@ -4621,7 +4606,6 @@ static void rtl_hw_start_8168g(struct rtl8169_private *tp)
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rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
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RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
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RTL_W8(tp, MaxTxPacketSize, EarlySize);
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rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
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rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
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@ -4719,7 +4703,6 @@ static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
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rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
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RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
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RTL_W8(tp, MaxTxPacketSize, EarlySize);
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rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
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rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
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@ -4795,7 +4778,6 @@ static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
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rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
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RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
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RTL_W8(tp, MaxTxPacketSize, EarlySize);
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rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
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rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
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@ -5067,7 +5049,10 @@ static void rtl_hw_start_8168(struct rtl8169_private *tp)
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pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
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PCI_EXP_DEVCTL_NOSNOOP_EN);
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RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
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if (rtl_is_8168evl_up(tp))
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RTL_W8(tp, MaxTxPacketSize, EarlySize);
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else
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RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
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rtl_hw_config(tp);
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}
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@ -6483,13 +6468,10 @@ static int rtl_alloc_irq(struct rtl8169_private *tp)
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static void rtl_read_mac_address(struct rtl8169_private *tp,
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u8 mac_addr[ETH_ALEN])
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{
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u32 value;
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/* Get MAC address */
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switch (tp->mac_version) {
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case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
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case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
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value = rtl_eri_read(tp, 0xe0);
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if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
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u32 value = rtl_eri_read(tp, 0xe0);
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mac_addr[0] = (value >> 0) & 0xff;
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mac_addr[1] = (value >> 8) & 0xff;
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mac_addr[2] = (value >> 16) & 0xff;
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@ -6498,9 +6480,6 @@ static void rtl_read_mac_address(struct rtl8169_private *tp,
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value = rtl_eri_read(tp, 0xe4);
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mac_addr[4] = (value >> 0) & 0xff;
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mac_addr[5] = (value >> 8) & 0xff;
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break;
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default:
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break;
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}
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}
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