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ASoC: Add a few more mpc5200 PSC defines
Add a few more mpc5200 PSC defines. More bit fields defines for mpc5200 PSC registers. Signed-off-by: Jon Smirl <jonsmirl@gmail.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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@ -28,6 +28,10 @@
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#define MPC52xx_PSC_MAXNUM 6
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/* Programmable Serial Controller (PSC) status register bits */
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#define MPC52xx_PSC_SR_UNEX_RX 0x0001
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#define MPC52xx_PSC_SR_DATA_VAL 0x0002
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#define MPC52xx_PSC_SR_DATA_OVR 0x0004
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#define MPC52xx_PSC_SR_CMDSEND 0x0008
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#define MPC52xx_PSC_SR_CDE 0x0080
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#define MPC52xx_PSC_SR_RXRDY 0x0100
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#define MPC52xx_PSC_SR_RXFULL 0x0200
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@ -61,6 +65,12 @@
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#define MPC52xx_PSC_RXTX_FIFO_EMPTY 0x0001
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/* PSC interrupt status/mask bits */
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#define MPC52xx_PSC_IMR_UNEX_RX_SLOT 0x0001
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#define MPC52xx_PSC_IMR_DATA_VALID 0x0002
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#define MPC52xx_PSC_IMR_DATA_OVR 0x0004
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#define MPC52xx_PSC_IMR_CMD_SEND 0x0008
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#define MPC52xx_PSC_IMR_ERROR 0x0040
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#define MPC52xx_PSC_IMR_DEOF 0x0080
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#define MPC52xx_PSC_IMR_TXRDY 0x0100
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#define MPC52xx_PSC_IMR_RXRDY 0x0200
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#define MPC52xx_PSC_IMR_DB 0x0400
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@ -117,6 +127,7 @@
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#define MPC52xx_PSC_SICR_SIM_FIR (0x6 << 24)
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#define MPC52xx_PSC_SICR_SIM_CODEC_24 (0x7 << 24)
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#define MPC52xx_PSC_SICR_SIM_CODEC_32 (0xf << 24)
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#define MPC52xx_PSC_SICR_AWR (1 << 30)
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#define MPC52xx_PSC_SICR_GENCLK (1 << 23)
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#define MPC52xx_PSC_SICR_I2S (1 << 22)
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#define MPC52xx_PSC_SICR_CLKPOL (1 << 21)
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