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drm/radeon: add dpm UVD handling for TN asics (v2)
v2: fix typo noticed by Dan Carpenter Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
06793dfba2
commit
0c4aaeae44
@ -77,6 +77,7 @@ typedef uint8_t PPSMC_Result;
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#define PPSMC_MSG_PG_SIMD_Config ((uint32_t) 0x108)
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#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint32_t) 0x11d)
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#define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint32_t) 0x11e)
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#define PPSMC_MSG_UVD_DPM_Config ((uint32_t) 0x124)
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typedef uint16_t PPSMC_Msg;
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@ -866,6 +866,117 @@ static void trinity_program_bootup_state(struct radeon_device *rdev)
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trinity_power_level_enable_disable(rdev, i, false);
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}
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static void trinity_setup_uvd_clock_table(struct radeon_device *rdev,
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struct radeon_ps *rps)
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{
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struct trinity_ps *ps = trinity_get_ps(rps);
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u32 uvdstates = (ps->vclk_low_divider |
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ps->vclk_high_divider << 8 |
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ps->dclk_low_divider << 16 |
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ps->dclk_high_divider << 24);
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WREG32_SMC(SMU_UVD_DPM_STATES, uvdstates);
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}
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static void trinity_setup_uvd_dpm_interval(struct radeon_device *rdev,
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u32 interval)
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{
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u32 p, u;
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u32 tp = RREG32_SMC(PM_TP);
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u32 val;
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u32 xclk = sumo_get_xclk(rdev);
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r600_calculate_u_and_p(interval, xclk, 16, &p, &u);
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val = (p + tp - 1) / tp;
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WREG32_SMC(SMU_UVD_DPM_CNTL, val);
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}
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static bool trinity_uvd_clocks_zero(struct radeon_ps *rps)
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{
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if ((rps->vclk == 0) && (rps->dclk == 0))
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return true;
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else
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return false;
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}
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static bool trinity_uvd_clocks_equal(struct radeon_ps *rps1,
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struct radeon_ps *rps2)
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{
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struct trinity_ps *ps1 = trinity_get_ps(rps1);
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struct trinity_ps *ps2 = trinity_get_ps(rps2);
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if ((rps1->vclk == rps2->vclk) &&
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(rps1->dclk == rps2->dclk) &&
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(ps1->vclk_low_divider == ps2->vclk_low_divider) &&
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(ps1->vclk_high_divider == ps2->vclk_high_divider) &&
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(ps1->dclk_low_divider == ps2->dclk_low_divider) &&
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(ps1->dclk_high_divider == ps2->dclk_high_divider))
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return true;
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else
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return false;
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}
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static void trinity_setup_uvd_clocks(struct radeon_device *rdev,
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struct radeon_ps *current_rps,
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struct radeon_ps *new_rps)
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{
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struct trinity_power_info *pi = trinity_get_pi(rdev);
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if (pi->uvd_dpm) {
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if (trinity_uvd_clocks_zero(new_rps) &&
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!trinity_uvd_clocks_zero(current_rps)) {
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trinity_setup_uvd_dpm_interval(rdev, 0);
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} else if (!trinity_uvd_clocks_zero(new_rps)) {
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trinity_setup_uvd_clock_table(rdev, new_rps);
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if (trinity_uvd_clocks_zero(current_rps)) {
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u32 tmp = RREG32(CG_MISC_REG);
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tmp &= 0xfffffffd;
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WREG32(CG_MISC_REG, tmp);
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radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
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trinity_setup_uvd_dpm_interval(rdev, 3000);
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}
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}
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trinity_uvd_dpm_config(rdev);
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} else {
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if (trinity_uvd_clocks_zero(new_rps) ||
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trinity_uvd_clocks_equal(new_rps, current_rps))
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return;
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radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
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}
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}
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static void trinity_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev)
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{
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struct trinity_ps *new_ps = trinity_get_ps(rdev->pm.dpm.requested_ps);
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struct trinity_ps *current_ps = trinity_get_ps(rdev->pm.dpm.current_ps);
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if (new_ps->levels[new_ps->num_levels - 1].sclk >=
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current_ps->levels[current_ps->num_levels - 1].sclk)
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return;
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trinity_setup_uvd_clocks(rdev, rdev->pm.dpm.current_ps,
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rdev->pm.dpm.requested_ps);
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}
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static void trinity_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev)
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{
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struct trinity_ps *new_ps = trinity_get_ps(rdev->pm.dpm.requested_ps);
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struct trinity_ps *current_ps = trinity_get_ps(rdev->pm.dpm.current_ps);
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if (new_ps->levels[new_ps->num_levels - 1].sclk <
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current_ps->levels[current_ps->num_levels - 1].sclk)
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return;
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trinity_setup_uvd_clocks(rdev, rdev->pm.dpm.current_ps,
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rdev->pm.dpm.requested_ps);
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}
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static void trinity_program_ttt(struct radeon_device *rdev)
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{
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struct trinity_power_info *pi = trinity_get_pi(rdev);
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@ -1017,6 +1128,7 @@ int trinity_dpm_set_power_state(struct radeon_device *rdev)
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trinity_acquire_mutex(rdev);
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if (pi->enable_dpm) {
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trinity_set_uvd_clock_before_set_eng_clock(rdev);
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trinity_enable_power_level_0(rdev);
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trinity_force_level_0(rdev);
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trinity_wait_for_level_0(rdev);
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@ -1024,6 +1136,7 @@ int trinity_dpm_set_power_state(struct radeon_device *rdev)
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trinity_program_power_levels_0_to_n(rdev);
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trinity_force_level_0(rdev);
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trinity_unforce_levels(rdev);
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trinity_set_uvd_clock_after_set_eng_clock(rdev);
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}
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trinity_release_mutex(rdev);
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@ -1198,6 +1311,61 @@ static u8 trinity_calculate_display_wm(struct radeon_device *rdev,
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}
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}
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static u32 trinity_get_uvd_clock_index(struct radeon_device *rdev,
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struct radeon_ps *rps)
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{
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struct trinity_power_info *pi = trinity_get_pi(rdev);
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u32 i = 0;
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for (i = 0; i < 4; i++) {
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if ((rps->vclk == pi->sys_info.uvd_clock_table_entries[i].vclk) &&
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(rps->dclk == pi->sys_info.uvd_clock_table_entries[i].dclk))
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break;
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}
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if (i >= 4) {
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DRM_ERROR("UVD clock index not found!\n");
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i = 3;
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}
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return i;
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}
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static void trinity_adjust_uvd_state(struct radeon_device *rdev,
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struct radeon_ps *rps)
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{
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struct trinity_ps *ps = trinity_get_ps(rps);
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struct trinity_power_info *pi = trinity_get_pi(rdev);
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u32 high_index = 0;
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u32 low_index = 0;
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if (pi->uvd_dpm && r600_is_uvd_state(rps->class, rps->class2)) {
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high_index = trinity_get_uvd_clock_index(rdev, rps);
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switch(high_index) {
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case 3:
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case 2:
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low_index = 1;
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break;
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case 1:
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case 0:
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default:
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low_index = 0;
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break;
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}
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ps->vclk_low_divider =
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pi->sys_info.uvd_clock_table_entries[high_index].vclk_did;
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ps->dclk_low_divider =
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pi->sys_info.uvd_clock_table_entries[high_index].dclk_did;
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ps->vclk_high_divider =
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pi->sys_info.uvd_clock_table_entries[low_index].vclk_did;
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ps->dclk_high_divider =
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pi->sys_info.uvd_clock_table_entries[low_index].dclk_did;
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}
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}
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static void trinity_apply_state_adjust_rules(struct radeon_device *rdev)
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{
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struct radeon_ps *rps = rdev->pm.dpm.requested_ps;
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@ -1214,6 +1382,8 @@ static void trinity_apply_state_adjust_rules(struct radeon_device *rdev)
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if (rps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
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return trinity_patch_thermal_state(rdev, ps, current_ps);
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trinity_adjust_uvd_state(rdev, rps);
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for (i = 0; i < ps->num_levels; i++) {
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if (ps->levels[i].vddc_index < min_voltage)
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ps->levels[i].vddc_index = min_voltage;
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@ -1454,6 +1624,25 @@ union igp_info {
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struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
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};
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static u32 trinity_convert_did_to_freq(struct radeon_device *rdev, u8 did)
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{
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struct trinity_power_info *pi = trinity_get_pi(rdev);
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u32 divider;
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if (did >= 8 && did <= 0x3f)
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divider = did * 25;
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else if (did > 0x3f && did <= 0x5f)
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divider = (did - 64) * 50 + 1600;
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else if (did > 0x5f && did <= 0x7e)
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divider = (did - 96) * 100 + 3200;
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else if (did == 0x7f)
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divider = 128 * 100;
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else
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return 10000;
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return ((pi->sys_info.dentist_vco_freq * 100) + (divider - 1)) / divider;
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}
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static int trinity_parse_sys_info_table(struct radeon_device *rdev)
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{
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struct trinity_power_info *pi = trinity_get_pi(rdev);
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@ -1476,6 +1665,7 @@ static int trinity_parse_sys_info_table(struct radeon_device *rdev)
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pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_7.ulBootUpEngineClock);
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pi->sys_info.min_sclk = le32_to_cpu(igp_info->info_7.ulMinEngineClock);
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pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_7.ulBootUpUMAClock);
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pi->sys_info.dentist_vco_freq = le32_to_cpu(igp_info->info_7.ulDentistVCOFreq);
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pi->sys_info.bootup_nb_voltage_index =
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le16_to_cpu(igp_info->info_7.usBootUpNBVoltage);
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if (igp_info->info_7.ucHtcTmpLmt == 0)
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@ -1521,6 +1711,35 @@ static int trinity_parse_sys_info_table(struct radeon_device *rdev)
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sumo_construct_vid_mapping_table(rdev, &pi->sys_info.vid_mapping_table,
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igp_info->info_7.sAvail_SCLK);
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pi->sys_info.uvd_clock_table_entries[0].vclk_did =
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igp_info->info_7.ucDPMState0VclkFid;
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pi->sys_info.uvd_clock_table_entries[1].vclk_did =
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igp_info->info_7.ucDPMState1VclkFid;
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pi->sys_info.uvd_clock_table_entries[2].vclk_did =
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igp_info->info_7.ucDPMState2VclkFid;
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pi->sys_info.uvd_clock_table_entries[3].vclk_did =
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igp_info->info_7.ucDPMState3VclkFid;
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pi->sys_info.uvd_clock_table_entries[0].dclk_did =
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igp_info->info_7.ucDPMState0DclkFid;
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pi->sys_info.uvd_clock_table_entries[1].dclk_did =
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igp_info->info_7.ucDPMState1DclkFid;
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pi->sys_info.uvd_clock_table_entries[2].dclk_did =
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igp_info->info_7.ucDPMState2DclkFid;
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pi->sys_info.uvd_clock_table_entries[3].dclk_did =
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igp_info->info_7.ucDPMState3DclkFid;
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for (i = 0; i < 4; i++) {
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pi->sys_info.uvd_clock_table_entries[i].vclk =
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trinity_convert_did_to_freq(rdev,
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pi->sys_info.uvd_clock_table_entries[i].vclk_did);
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pi->sys_info.uvd_clock_table_entries[i].dclk =
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trinity_convert_did_to_freq(rdev,
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pi->sys_info.uvd_clock_table_entries[i].dclk_did);
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}
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}
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return 0;
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}
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@ -1547,6 +1766,7 @@ int trinity_dpm_init(struct radeon_device *rdev)
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pi->override_dynamic_mgpg = true;
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pi->enable_auto_thermal_throttling = true;
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pi->voltage_drop_in_dce = false; /* need to restructure dpm/modeset interaction */
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pi->uvd_dpm = true; /* ??? */
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ret = trinity_parse_sys_info_table(rdev);
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if (ret)
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@ -55,14 +55,29 @@ struct trinity_ps {
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u8 Dpm0PgNbPsHi;
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u8 DpmXNbPsLo;
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u8 DpmXNbPsHi;
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u32 vclk_low_divider;
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u32 vclk_high_divider;
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u32 dclk_low_divider;
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u32 dclk_high_divider;
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};
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#define TRINITY_NUM_NBPSTATES 4
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struct trinity_uvd_clock_table_entry
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{
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u32 vclk;
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u32 dclk;
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u8 vclk_did;
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u8 dclk_did;
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u8 rsv[2];
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};
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struct trinity_sys_info {
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u32 bootup_uma_clk;
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u32 bootup_sclk;
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u32 min_sclk;
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u32 dentist_vco_freq;
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u32 nb_dpm_enable;
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u32 nbp_mclk[TRINITY_NUM_NBPSTATES];
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u32 nbp_nclk[TRINITY_NUM_NBPSTATES];
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@ -73,6 +88,7 @@ struct trinity_sys_info {
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struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table;
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struct sumo_vid_mapping_table vid_mapping_table;
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u32 uma_channel_number;
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struct trinity_uvd_clock_table_entry uvd_clock_table_entries[4];
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};
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struct trinity_power_info {
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@ -93,12 +109,14 @@ struct trinity_power_info {
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bool enable_auto_thermal_throttling;
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bool enable_dpm;
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bool enable_sclk_ds;
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bool uvd_dpm;
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};
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#define TRINITY_AT_DFLT 30
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/* trinity_smc.c */
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int trinity_dpm_config(struct radeon_device *rdev, bool enable);
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int trinity_uvd_dpm_config(struct radeon_device *rdev);
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int trinity_dpm_force_state(struct radeon_device *rdev, u32 n);
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int trinity_dpm_no_forced_level(struct radeon_device *rdev);
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int trinity_dce_enable_voltage_adjustment(struct radeon_device *rdev,
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@ -73,6 +73,11 @@ int trinity_dpm_force_state(struct radeon_device *rdev, u32 n)
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return trinity_notify_message_to_smu(rdev, PPSMC_MSG_DPM_ForceState);
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}
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int trinity_uvd_dpm_config(struct radeon_device *rdev)
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{
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return trinity_notify_message_to_smu(rdev, PPSMC_MSG_UVD_DPM_Config);
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}
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int trinity_dpm_no_forced_level(struct radeon_device *rdev)
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{
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return trinity_notify_message_to_smu(rdev, PPSMC_MSG_NoForcedLevel);
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@ -100,6 +100,9 @@
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# define HT_MASK (0xffff << 16)
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# define HT_SHIFT 16
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#define SMU_UVD_DPM_STATES 0x1f1a0
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#define SMU_UVD_DPM_CNTL 0x1f1a4
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#define SMU_S_PG_CNTL 0x1f118
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# define DS_PG_EN(x) ((x) << 16)
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# define DS_PG_EN_MASK (0xff << 16)
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@ -198,6 +201,8 @@
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# define SU_MASK (0xffff << 16)
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# define SU_SHIFT 16
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#define CG_MISC_REG 0x708
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#define CG_THERMAL_INT_CTRL 0x738
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# define DIG_THERM_INTH(x) ((x) << 0)
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# define DIG_THERM_INTH_MASK (0xff << 0)
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