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ARM: SoC non-urgent fixes for v4.5
As usual, we queue up a few fixes that don't seem urgent enough to go in
through -rc.
- MAINTAINERS updates to add a list for brcmstb and fix a typo
- A handful of fixes for OMAP 81xx, a recently resurrected platform so these
can't be considered real regressions and thus got queued.
- A couple of other small fixes for scoop, sa1100 and davinci
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Merge tag 'armsoc-fixes-nc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull non-urgent ARM SoC fixes from Olof Johansson:
"As usual, we queue up a few fixes that don't seem urgent enough to go
in through -rc.
- MAINTAINERS updates to add a list for brcmstb and fix a typo
- A handful of fixes for OMAP 81xx, a recently resurrected platform
so these can't be considered real regressions and thus got queued.
- A couple of other small fixes for scoop, sa1100 and davinci"
* tag 'armsoc-fixes-nc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: OMAP2+: Fix randconfig build warning for dm814_pllss_data
ARM: sa1100/simpad: Be sure to clamp return value
ARM: scoop: Be sure to clamp return value
ARM: davinci: fix a problematic usage of WARN()
ARM: davinci: only select WT cache if cache is enabled
ARM: OMAP2+: Remove useless check for legacy booting for dm814x
ARM: OMAP2+: Enable GPIO for dm814x
ARM: dts: Fix dm814x pinctrl address and mask
ARM: dts: Fix dm8148 control modules ranges
ARM: OMAP2+: Fix timer entries for dm814x
ARM: dts: Fix some mux and divider clocks to get dm814x-evm booting
ARM: OMAP2+: Add DPPLS clock manager for dm814x
clk: ti: Add few dm814x clock aliases
ARM: dts: Fix dm814x entries for pllss and prcm
MAINTAINERS: gpio-brcmstb: Remove stray '>'
MAINTAINERS: brcmstb: Include Broadcom internal mailing-list
This commit is contained in:
Linus Torvalds
commit
0c582826a1
@ -2377,6 +2377,7 @@ M: Brian Norris <computersforpeace@gmail.com>
|
||||
M: Gregory Fong <gregory.0xf0@gmail.com>
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M: Florian Fainelli <f.fainelli@gmail.com>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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L: bcm-kernel-feedback-list@broadcom.com
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T: git git://github.com/broadcom/stblinux.git
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S: Maintained
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F: arch/arm/mach-bcm/*brcmstb*
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@ -2450,7 +2451,7 @@ N: bcm88312
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BROADCOM BRCMSTB GPIO DRIVER
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M: Gregory Fong <gregory.0xf0@gmail.com>
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L: bcm-kernel-feedback-list@broadcom.com>
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L: bcm-kernel-feedback-list@broadcom.com
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S: Supported
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F: drivers/gpio/gpio-brcmstb.c
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F: Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt
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@ -4,18 +4,41 @@
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* published by the Free Software Foundation.
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*/
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&scm_clocks {
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tclkin_ck: tclkin_ck {
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&pllss_clocks {
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timer1_fck: timer1_fck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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compatible = "ti,mux-clock";
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clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
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&aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
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ti,bit-shift = <3>;
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reg = <0x2e0>;
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};
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timer2_fck: timer2_fck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
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&aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
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ti,bit-shift = <6>;
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reg = <0x2e0>;
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};
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sysclk18_ck: sysclk18_ck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&rtcosc_ck>, <&rtcdivider_ck>;
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ti,bit-shift = <0>;
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reg = <0x02f0>;
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};
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};
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&scm_clocks {
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devosc_ck: devosc_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <20000000>;
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compatible = "ti,mux-clock";
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clocks = <&virt_20000000_ck>, <&virt_19200000_ck>;
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ti,bit-shift = <21>;
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reg = <0x0040>;
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};
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/* Optional auxosc, 20 - 30 MHz range, assume 27 MHz by default */
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@ -25,6 +48,32 @@
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clock-frequency = <27000000>;
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};
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/* Optional 32768Hz crystal or clock on RTCOSC pins */
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rtcosc_ck: rtcosc_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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/* Optional external clock on TCLKIN pin, set rate in baord dts file */
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tclkin_ck: tclkin_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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virt_20000000_ck: virt_20000000_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <20000000>;
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};
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virt_19200000_ck: virt_19200000_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <19200000>;
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};
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mpu_ck: mpu_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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@ -49,12 +98,6 @@
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clock-frequency = <48000000>;
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};
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sysclk18_ck: sysclk18_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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cpsw_125mhz_gclk: cpsw_125mhz_gclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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@ -69,7 +112,31 @@
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};
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&pllss_clocks {
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&prcm_clocks {
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osc_src_ck: osc_src_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&devosc_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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mpu_clksrc_ck: mpu_clksrc_ck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&devosc_ck>, <&rtcdivider_ck>;
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ti,bit-shift = <0>;
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reg = <0x0040>;
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};
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/* Fixed divider clock 0.0016384 * devosc */
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rtcdivider_ck: rtcdivider_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&devosc_ck>;
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clock-mult = <128>;
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clock-div = <78125>;
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};
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aud_clkin0_ck: aud_clkin0_ck {
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#clock-cells = <0>;
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@ -88,22 +155,4 @@
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compatible = "fixed-clock";
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clock-frequency = <20000000>;
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};
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timer1_mux_ck: timer1_mux_ck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
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&aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
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ti,bit-shift = <3>;
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reg = <0x2e0>;
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};
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timer2_mux_ck: timer2_mux_ck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
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&aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
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ti,bit-shift = <6>;
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reg = <0x2e0>;
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};
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};
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@ -58,8 +58,10 @@
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ti,hwmods = "l3_main";
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/*
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* See TRM "Table 1-317. L4LS Instance Summary", just deduct
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* 0x1000 from the 1-317 addresses to get the device address
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* See TRM "Table 1-317. L4LS Instance Summary" for hints.
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* It shows the module target agent registers though, so the
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* actual device is typically 0x1000 before the target agent
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* except in cases where the module is larger than 0x1000.
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*/
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l4ls: l4ls@48000000 {
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compatible = "ti,dm814-l4ls", "simple-bus";
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@ -183,10 +185,10 @@
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control: control@140000 {
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compatible = "ti,dm814-scm", "simple-bus";
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reg = <0x140000 0x16d000>;
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reg = <0x140000 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x160000 0x16d000>;
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ranges = <0 0x140000 0x20000>;
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scm_conf: scm_conf@0 {
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compatible = "syscon";
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@ -203,19 +205,30 @@
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};
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};
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/*
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* Note that silicon revision 2.1 and older
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* require input enabled (bit 18 set) for all
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* 3.3V I/Os to avoid cumulative hardware damage.
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* For more info, see errata advisory 2.1.87.
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* We leave bit 18 out of function-mask and rely
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* on the bootloader for it.
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*/
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pincntl: pinmux@800 {
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compatible = "pinctrl-single";
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reg = <0x800 0xc38>;
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reg = <0x800 0x438>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x300ff>;
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pinctrl-single,function-mask = <0x307ff>;
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};
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};
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prcm: prcm@180000 {
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compatible = "ti,dm814-prcm", "simple-bus";
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reg = <0x180000 0x4000>;
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reg = <0x180000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x180000 0x2000>;
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prcm_clocks: clocks {
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#address-cells = <1>;
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@ -226,9 +239,13 @@
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};
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};
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/* See TRM PLL_SUBSYS_BASE and "PLLSS Registers" */
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pllss: pllss@1c5000 {
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compatible = "ti,dm814-pllss", "simple-bus";
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reg = <0x1c5000 0x2000>;
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reg = <0x1c5000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x1c5000 0x1000>;
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pllss_clocks: clocks {
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#address-cells = <1>;
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@ -84,7 +84,7 @@ static int scoop_gpio_get(struct gpio_chip *chip, unsigned offset)
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struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio);
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/* XXX: I'm unsure, but it seems so */
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return ioread16(sdev->base + SCOOP_GPRR) & (1 << (offset + 1));
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return !!(ioread16(sdev->base + SCOOP_GPRR) & (1 << (offset + 1)));
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}
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static int scoop_gpio_direction_input(struct gpio_chip *chip,
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@ -34,7 +34,8 @@ config ARCH_DAVINCI_DA830
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bool "DA830/OMAP-L137/AM17x based system"
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depends on !ARCH_DAVINCI_DMx || AUTO_ZRELADDR
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select ARCH_DAVINCI_DA8XX
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select CPU_DCACHE_WRITETHROUGH # needed on silicon revs 1.0, 1.1
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# needed on silicon revs 1.0, 1.1:
|
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select CPU_DCACHE_WRITETHROUGH if !CPU_DCACHE_DISABLE
|
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select CP_INTC
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config ARCH_DAVINCI_DA850
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@ -384,9 +384,7 @@ static __init void dm355_evm_init(void)
|
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dm355evm_dm9000_rsrc[2].start = gpio_to_irq(1);
|
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|
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aemif = clk_get(&dm355evm_dm9000.dev, "aemif");
|
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if (IS_ERR(aemif))
|
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WARN("%s: unable to get AEMIF clock\n", __func__);
|
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else
|
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if (!WARN(IS_ERR(aemif), "unable to get AEMIF clock\n"))
|
||||
clk_prepare_enable(aemif);
|
||||
|
||||
platform_add_devices(davinci_evm_devices,
|
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|
||||
@ -242,9 +242,7 @@ static __init void dm355_leopard_init(void)
|
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dm355leopard_dm9000_rsrc[2].start = gpio_to_irq(9);
|
||||
|
||||
aemif = clk_get(&dm355leopard_dm9000.dev, "aemif");
|
||||
if (IS_ERR(aemif))
|
||||
WARN("%s: unable to get AEMIF clock\n", __func__);
|
||||
else
|
||||
if (!WARN(IS_ERR(aemif), "unable to get AEMIF clock\n"))
|
||||
clk_prepare_enable(aemif);
|
||||
|
||||
platform_add_devices(davinci_leopard_devices,
|
||||
|
||||
@ -612,8 +612,7 @@ void __init ti814x_init_early(void)
|
||||
ti814x_clockdomains_init();
|
||||
dm814x_hwmod_init();
|
||||
omap_hwmod_init_postsetup();
|
||||
if (of_have_populated_dt())
|
||||
omap_clk_soc_init = dm814x_dt_clk_init;
|
||||
omap_clk_soc_init = dm814x_dt_clk_init;
|
||||
}
|
||||
|
||||
void __init ti816x_init_early(void)
|
||||
|
||||
@ -599,7 +599,7 @@ static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
|
||||
static struct omap_hwmod dm814x_timer1_hwmod = {
|
||||
.name = "timer1",
|
||||
.clkdm_name = "alwon_l3s_clkdm",
|
||||
.main_clk = "timer_sys_ck",
|
||||
.main_clk = "timer1_fck",
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.class = &dm816x_timer_hwmod_class,
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
@ -608,7 +608,7 @@ static struct omap_hwmod dm814x_timer1_hwmod = {
|
||||
static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = {
|
||||
.master = &dm81xx_l4_ls_hwmod,
|
||||
.slave = &dm814x_timer1_hwmod,
|
||||
.clk = "timer_sys_ck",
|
||||
.clk = "timer1_fck",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
@ -636,7 +636,7 @@ static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = {
|
||||
static struct omap_hwmod dm814x_timer2_hwmod = {
|
||||
.name = "timer2",
|
||||
.clkdm_name = "alwon_l3s_clkdm",
|
||||
.main_clk = "timer_sys_ck",
|
||||
.main_clk = "timer2_fck",
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.class = &dm816x_timer_hwmod_class,
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
@ -645,7 +645,7 @@ static struct omap_hwmod dm814x_timer2_hwmod = {
|
||||
static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = {
|
||||
.master = &dm81xx_l4_ls_hwmod,
|
||||
.slave = &dm814x_timer2_hwmod,
|
||||
.clk = "timer_sys_ck",
|
||||
.clk = "timer2_fck",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
@ -1230,8 +1230,6 @@ static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = {
|
||||
|
||||
/*
|
||||
* REVISIT: Test and enable the following once clocks work:
|
||||
* dm81xx_l4_ls__gpio1
|
||||
* dm81xx_l4_ls__gpio2
|
||||
* dm81xx_l4_ls__mailbox
|
||||
* dm81xx_alwon_l3_slow__gpmc
|
||||
* dm81xx_default_l3_slow__usbss
|
||||
@ -1250,6 +1248,8 @@ static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
|
||||
&dm81xx_l4_ls__wd_timer1,
|
||||
&dm81xx_l4_ls__i2c1,
|
||||
&dm81xx_l4_ls__i2c2,
|
||||
&dm81xx_l4_ls__gpio1,
|
||||
&dm81xx_l4_ls__gpio2,
|
||||
&dm81xx_l4_ls__elm,
|
||||
&dm81xx_l4_ls__mcspi1,
|
||||
&dm81xx_alwon_l3_fast__tpcc,
|
||||
|
||||
@ -664,6 +664,13 @@ static struct omap_prcm_init_data am3_prm_data __initdata = {
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_TI81XX
|
||||
static struct omap_prcm_init_data dm814_pllss_data __initdata = {
|
||||
.index = TI_CLKM_PLLSS,
|
||||
.init = am33xx_prm_init,
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP4
|
||||
static struct omap_prcm_init_data omap4_prm_data __initdata = {
|
||||
.index = TI_CLKM_PRM,
|
||||
@ -715,6 +722,7 @@ static const struct of_device_id const omap_prcm_dt_match_table[] __initconst =
|
||||
#endif
|
||||
#ifdef CONFIG_SOC_TI81XX
|
||||
{ .compatible = "ti,dm814-prcm", .data = &am3_prm_data },
|
||||
{ .compatible = "ti,dm814-pllss", .data = &dm814_pllss_data },
|
||||
{ .compatible = "ti,dm816-prcm", .data = &am3_prm_data },
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_OMAP2
|
||||
|
||||
@ -98,8 +98,8 @@ static void cs3_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
||||
static int cs3_gpio_get(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
if (offset > 15)
|
||||
return simpad_get_cs3_ro() & (1 << (offset - 16));
|
||||
return simpad_get_cs3_shadow() & (1 << offset);
|
||||
return !!(simpad_get_cs3_ro() & (1 << (offset - 16)));
|
||||
return !!(simpad_get_cs3_shadow() & (1 << offset));
|
||||
};
|
||||
|
||||
static int cs3_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
|
||||
|
||||
@ -14,10 +14,14 @@ static struct ti_dt_clk dm814_clks[] = {
|
||||
DT_CLK(NULL, "devosc_ck", "devosc_ck"),
|
||||
DT_CLK(NULL, "mpu_ck", "mpu_ck"),
|
||||
DT_CLK(NULL, "sysclk4_ck", "sysclk4_ck"),
|
||||
DT_CLK(NULL, "sysclk5_ck", "sysclk5_ck"),
|
||||
DT_CLK(NULL, "sysclk6_ck", "sysclk6_ck"),
|
||||
DT_CLK(NULL, "sysclk8_ck", "sysclk8_ck"),
|
||||
DT_CLK(NULL, "sysclk10_ck", "sysclk10_ck"),
|
||||
DT_CLK(NULL, "sysclk18_ck", "sysclk18_ck"),
|
||||
DT_CLK(NULL, "timer_sys_ck", "devosc_ck"),
|
||||
DT_CLK(NULL, "timer1_fck", "timer1_fck"),
|
||||
DT_CLK(NULL, "timer2_fck", "timer2_fck"),
|
||||
DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
|
||||
DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
|
||||
{ .node_name = NULL },
|
||||
|
||||
@ -195,6 +195,7 @@ enum {
|
||||
TI_CLKM_PRM,
|
||||
TI_CLKM_SCRM,
|
||||
TI_CLKM_CTRL,
|
||||
TI_CLKM_PLLSS,
|
||||
CLK_MAX_MEMMAPS
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user