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IB/qib: Use pcie_set_mps() and pcie_get_mps() to simplify code

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Refactor qib_tune_pcie_caps().  Use pcie_get_mps(), pcie_set_mps(),
pcie_get_readrq(), and pcie_set_readrq() to simplify the code.  The PCI
core caches the "PCIe Max Payload Size Supported" in pci_dev->pcie_mpss,
so use that instead of pcie_capability_read_word().  Remove the unused
val2fld() and fld2val().

Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mike Marciniszyn <mike.marciniszyn@intel.com>
This commit is contained in:
Yijing Wang 2013-09-09 21:13:06 +08:00 committed by Bjorn Helgaas
parent dcaa73dc34
commit 0ce0e62f1f
1 changed files with 29 additions and 65 deletions
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94
drivers/infiniband/hw/qib/qib_pcie.c
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@ -476,30 +476,6 @@ void qib_pcie_reenable(struct qib_devdata *dd, u16 cmd, u8 iline, u8 cline)
"pci_enable_device failed after reset: %d\n", r); "pci_enable_device failed after reset: %d\n", r);
} }
/* code to adjust PCIe capabilities. */
static int fld2val(int wd, int mask)
{
int lsbmask;
if (!mask)
return 0;
wd &= mask;
lsbmask = mask ^ (mask & (mask - 1));
wd /= lsbmask;
return wd;
}
static int val2fld(int wd, int mask)
{
int lsbmask;
if (!mask)
return 0;
lsbmask = mask ^ (mask & (mask - 1));
wd *= lsbmask;
return wd;
}
static int qib_pcie_coalesce; static int qib_pcie_coalesce;
module_param_named(pcie_coalesce, qib_pcie_coalesce, int, S_IRUGO); module_param_named(pcie_coalesce, qib_pcie_coalesce, int, S_IRUGO);
@ -584,9 +560,8 @@ static int qib_tune_pcie_caps(struct qib_devdata *dd)
{ {
int ret = 1; /* Assume the worst */ int ret = 1; /* Assume the worst */
struct pci_dev *parent; struct pci_dev *parent;
u16 pcaps, pctl, ecaps, ectl; u16 rc_mpss, rc_mps, ep_mpss, ep_mps;
int rc_sup, ep_sup; u16 rc_mrrs, ep_mrrs, max_mrrs;
int rc_cur, ep_cur;
/* Find out supported and configured values for parent (root) */ /* Find out supported and configured values for parent (root) */
parent = dd->pcidev->bus->self; parent = dd->pcidev->bus->self;
@ -597,38 +572,29 @@ static int qib_tune_pcie_caps(struct qib_devdata *dd)
if (!pci_is_pcie(parent) || !pci_is_pcie(dd->pcidev)) if (!pci_is_pcie(parent) || !pci_is_pcie(dd->pcidev))
goto bail; goto bail;
pcie_capability_read_word(parent, PCI_EXP_DEVCAP, &pcaps); rc_mpss = parent->pcie_mpss;
pcie_capability_read_word(parent, PCI_EXP_DEVCTL, &pctl); rc_mps = ffs(pcie_get_mps(parent)) - 8;
/* Find out supported and configured values for endpoint (us) */ /* Find out supported and configured values for endpoint (us) */
pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCAP, &ecaps); ep_mpss = dd->pcidev->pcie_mpss;
pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &ectl); ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8;
ret = 0; ret = 0;
/* Find max payload supported by root, endpoint */ /* Find max payload supported by root, endpoint */
rc_sup = fld2val(pcaps, PCI_EXP_DEVCAP_PAYLOAD); if (rc_mpss > ep_mpss)
ep_sup = fld2val(ecaps, PCI_EXP_DEVCAP_PAYLOAD); rc_mpss = ep_mpss;
if (rc_sup > ep_sup)
rc_sup = ep_sup;
rc_cur = fld2val(pctl, PCI_EXP_DEVCTL_PAYLOAD);
ep_cur = fld2val(ectl, PCI_EXP_DEVCTL_PAYLOAD);
/* If Supported greater than limit in module param, limit it */ /* If Supported greater than limit in module param, limit it */
if (rc_sup > (qib_pcie_caps & 7)) if (rc_mpss > (qib_pcie_caps & 7))
rc_sup = qib_pcie_caps & 7; rc_mpss = qib_pcie_caps & 7;
/* If less than (allowed, supported), bump root payload */ /* If less than (allowed, supported), bump root payload */
if (rc_sup > rc_cur) { if (rc_mpss > rc_mps) {
rc_cur = rc_sup; rc_mps = rc_mpss;
pctl = (pctl & ~PCI_EXP_DEVCTL_PAYLOAD) | pcie_set_mps(parent, 128 << rc_mps);
val2fld(rc_cur, PCI_EXP_DEVCTL_PAYLOAD);
pcie_capability_write_word(parent, PCI_EXP_DEVCTL, pctl);
} }
/* If less than (allowed, supported), bump endpoint payload */ /* If less than (allowed, supported), bump endpoint payload */
if (rc_sup > ep_cur) { if (rc_mpss > ep_mps) {
ep_cur = rc_sup; ep_mps = rc_mpss;
ectl = (ectl & ~PCI_EXP_DEVCTL_PAYLOAD) | pcie_set_mps(dd->pcidev, 128 << ep_mps);
val2fld(ep_cur, PCI_EXP_DEVCTL_PAYLOAD);
pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, ectl);
} }
/* /*
@ -636,23 +602,21 @@ static int qib_tune_pcie_caps(struct qib_devdata *dd)
* No field for max supported, but PCIe spec limits it to 4096, * No field for max supported, but PCIe spec limits it to 4096,
* which is code '5' (log2(4096) - 7) * which is code '5' (log2(4096) - 7)
*/ */
rc_sup = 5; max_mrrs = 5;
if (rc_sup > ((qib_pcie_caps >> 4) & 7)) if (max_mrrs > ((qib_pcie_caps >> 4) & 7))
rc_sup = (qib_pcie_caps >> 4) & 7; max_mrrs = (qib_pcie_caps >> 4) & 7;
rc_cur = fld2val(pctl, PCI_EXP_DEVCTL_READRQ);
ep_cur = fld2val(ectl, PCI_EXP_DEVCTL_READRQ);
if (rc_sup > rc_cur) { max_mrrs = 128 << max_mrrs;
rc_cur = rc_sup; rc_mrrs = pcie_get_readrq(parent);
pctl = (pctl & ~PCI_EXP_DEVCTL_READRQ) | ep_mrrs = pcie_get_readrq(dd->pcidev);
val2fld(rc_cur, PCI_EXP_DEVCTL_READRQ);
pcie_capability_write_word(parent, PCI_EXP_DEVCTL, pctl); if (max_mrrs > rc_mrrs) {
rc_mrrs = max_mrrs;
pcie_set_readrq(parent, rc_mrrs);
} }
if (rc_sup > ep_cur) { if (max_mrrs > ep_mrrs) {
ep_cur = rc_sup; ep_mrrs = max_mrrs;
ectl = (ectl & ~PCI_EXP_DEVCTL_READRQ) | pcie_set_readrq(dd->pcidev, ep_mrrs);
val2fld(ep_cur, PCI_EXP_DEVCTL_READRQ);
pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, ectl);
} }
bail: bail:
return ret; return ret;