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[media] v4l: ti-vpe: support loading of scaler coefficients
The SC block in VPE/VIP contains a SRAM within it. This internal memory requires to be loaded with appropriate scaler coefficients from a contiguous block of memory through VPDMA. The horizontal and vertical scaler each require 2 sets of scaler coefficients for luma and chroma scaling. The horizontal polyphase scaler requires coefficients for a 32 phase and 8 tap filter. Similarly, the vertical scaler requires coefficients for a 5 tap filter. The choice of the scaler coefficients depends on the scaling ratio. Add coefficient tables for different scaling ratios in sc_coeffs.h. In the case of horizontal downscaling, we need to consider the change in ratio caused by decimation performed by the horizontal scaler. In order to load the scaler coefficients via VPDMA, a configuration descriptor is used in block mode. The payload for the descriptor is the scaler coefficients copied to memory. Coefficients for each phase have to be placed in memory in a particular order understood by the scaler hardware. The choice of the scaler coefficients, and the loading of the coefficients from our tables to a contiguous buffer is managed by the functions sc_set_hs_coefficients and sc_set_vs_coefficients. The sc_data handle is now added with some parameters to describe the state of the coefficients loaded in the SC block. 'loaded_coeff_h' and 'loaded_coeff_v' hold the address of the last dma buffer which was used by VPDMA to copy coefficients. This information can be used by a vpe mem-to-mem context to decide whether it should load coefficients or not. 'hs_index' and 'vs_index' provide some optimization by preventing loading of coefficients if the scaling ratio didn't change between 2 contexts. 'load_coeff_h' and 'load_coeff_v' tell the vpe/vip driver whether we need to load the coefficients through VPDMA or not. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
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@ -18,6 +18,7 @@
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#include <linux/slab.h>
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#include "sc.h"
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#include "sc_coeff.h"
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void sc_set_regs_bypass(struct sc_data *sc, u32 *sc_reg0)
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{
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@ -61,6 +62,103 @@ void sc_dump_regs(struct sc_data *sc)
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#undef DUMPREG
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}
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/*
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* set the horizontal scaler coefficients according to the ratio of output to
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* input widths, after accounting for up to two levels of decimation
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*/
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void sc_set_hs_coeffs(struct sc_data *sc, void *addr, unsigned int src_w,
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unsigned int dst_w)
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{
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int sixteenths;
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int idx;
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int i, j;
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u16 *coeff_h = addr;
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const u16 *cp;
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if (dst_w > src_w) {
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idx = HS_UP_SCALE;
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} else {
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if ((dst_w << 1) < src_w)
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dst_w <<= 1; /* first level decimation */
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if ((dst_w << 1) < src_w)
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dst_w <<= 1; /* second level decimation */
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if (dst_w == src_w) {
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idx = HS_LE_16_16_SCALE;
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} else {
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sixteenths = (dst_w << 4) / src_w;
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if (sixteenths < 8)
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sixteenths = 8;
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idx = HS_LT_9_16_SCALE + sixteenths - 8;
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}
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}
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if (idx == sc->hs_index)
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return;
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cp = scaler_hs_coeffs[idx];
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for (i = 0; i < SC_NUM_PHASES * 2; i++) {
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for (j = 0; j < SC_H_NUM_TAPS; j++)
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*coeff_h++ = *cp++;
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/*
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* for each phase, the scaler expects space for 8 coefficients
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* in it's memory. For the horizontal scaler, we copy the first
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* 7 coefficients and skip the last slot to move to the next
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* row to hold coefficients for the next phase
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*/
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coeff_h += SC_NUM_TAPS_MEM_ALIGN - SC_H_NUM_TAPS;
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}
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sc->hs_index = idx;
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sc->load_coeff_h = true;
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}
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/*
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* set the vertical scaler coefficients according to the ratio of output to
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* input heights
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*/
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void sc_set_vs_coeffs(struct sc_data *sc, void *addr, unsigned int src_h,
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unsigned int dst_h)
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{
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int sixteenths;
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int idx;
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int i, j;
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u16 *coeff_v = addr;
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const u16 *cp;
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if (dst_h > src_h) {
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idx = VS_UP_SCALE;
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} else if (dst_h == src_h) {
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idx = VS_1_TO_1_SCALE;
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} else {
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sixteenths = (dst_h << 4) / src_h;
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if (sixteenths < 8)
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sixteenths = 8;
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idx = VS_LT_9_16_SCALE + sixteenths - 8;
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}
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if (idx == sc->vs_index)
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return;
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cp = scaler_vs_coeffs[idx];
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for (i = 0; i < SC_NUM_PHASES * 2; i++) {
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for (j = 0; j < SC_V_NUM_TAPS; j++)
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*coeff_v++ = *cp++;
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/*
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* for the vertical scaler, we copy the first 5 coefficients and
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* skip the last 3 slots to move to the next row to hold
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* coefficients for the next phase
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*/
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coeff_v += SC_NUM_TAPS_MEM_ALIGN - SC_V_NUM_TAPS;
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}
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sc->vs_index = idx;
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sc->load_coeff_v = true;
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}
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struct sc_data *sc_create(struct platform_device *pdev)
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{
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struct sc_data *sc;
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@ -161,15 +161,46 @@
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#define CFG_OFF_W_MASK 0x07ff
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#define CFG_OFF_W_SHIFT 16
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/* number of phases supported by the polyphase scalers */
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#define SC_NUM_PHASES 32
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/* number of taps used by horizontal polyphase scaler */
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#define SC_H_NUM_TAPS 7
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/* number of taps used by vertical polyphase scaler */
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#define SC_V_NUM_TAPS 5
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/* number of taps expected by the scaler in it's coefficient memory */
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#define SC_NUM_TAPS_MEM_ALIGN 8
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/*
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* coefficient memory size in bytes:
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* num phases x num sets(luma and chroma) x num taps(aligned) x coeff size
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*/
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#define SC_COEF_SRAM_SIZE (SC_NUM_PHASES * 2 * SC_NUM_TAPS_MEM_ALIGN * 2)
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struct sc_data {
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void __iomem *base;
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struct resource *res;
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dma_addr_t loaded_coeff_h; /* loaded h coeffs in SC */
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dma_addr_t loaded_coeff_v; /* loaded v coeffs in SC */
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bool load_coeff_h; /* have new h SC coeffs */
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bool load_coeff_v; /* have new v SC coeffs */
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unsigned int hs_index; /* h SC coeffs selector */
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unsigned int vs_index; /* v SC coeffs selector */
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struct platform_device *pdev;
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};
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void sc_set_regs_bypass(struct sc_data *sc, u32 *sc_reg0);
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void sc_dump_regs(struct sc_data *sc);
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void sc_set_hs_coeffs(struct sc_data *sc, void *addr, unsigned int src_w,
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unsigned int dst_w);
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void sc_set_vs_coeffs(struct sc_data *sc, void *addr, unsigned int src_h,
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unsigned int dst_h);
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struct sc_data *sc_create(struct platform_device *pdev);
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#endif
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1342
drivers/media/platform/ti-vpe/sc_coeff.h
Normal file
1342
drivers/media/platform/ti-vpe/sc_coeff.h
Normal file
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