mirror of
https://github.com/FEX-Emu/linux.git
synced 2024-12-17 06:17:35 +00:00
Merge branch 'core-iommu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'core-iommu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86/amd-iommu: Update copyright headers x86/amd-iommu: Reenable AMD IOMMU if it's mysteriously vanished over suspend AGP: Warn when GATT memory cannot be set to UC x86, GART: Disable GART table walk probes x86, GART: Remove superfluous AMD64_GARTEN
This commit is contained in:
commit
1053e6bba0
@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2007-2009 Advanced Micro Devices, Inc.
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* Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
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* Author: Joerg Roedel <joerg.roedel@amd.com>
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* Leo Duran <leo.duran@amd.com>
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*
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2009 Advanced Micro Devices, Inc.
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* Copyright (C) 2009-2010 Advanced Micro Devices, Inc.
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* Author: Joerg Roedel <joerg.roedel@amd.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2007-2009 Advanced Micro Devices, Inc.
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* Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
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* Author: Joerg Roedel <joerg.roedel@amd.com>
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* Leo Duran <leo.duran@amd.com>
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*
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@ -416,13 +416,22 @@ struct amd_iommu {
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struct dma_ops_domain *default_dom;
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/*
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* This array is required to work around a potential BIOS bug.
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* The BIOS may miss to restore parts of the PCI configuration
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* space when the system resumes from S3. The result is that the
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* IOMMU does not execute commands anymore which leads to system
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* failure.
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* We can't rely on the BIOS to restore all values on reinit, so we
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* need to stash them
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*/
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u32 cache_cfg[4];
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/* The iommu BAR */
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u32 stored_addr_lo;
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u32 stored_addr_hi;
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/*
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* Each iommu has 6 l1s, each of which is documented as having 0x12
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* registers
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*/
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u32 stored_l1[6][0x12];
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/* The l2 indirect registers */
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u32 stored_l2[0x83];
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};
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/*
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@ -17,6 +17,7 @@ extern int fix_aperture;
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#define GARTEN (1<<0)
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#define DISGARTCPU (1<<4)
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#define DISGARTIO (1<<5)
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#define DISTLBWALKPRB (1<<6)
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/* GART cache control register bits. */
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#define INVGART (1<<0)
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@ -27,7 +28,6 @@ extern int fix_aperture;
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#define AMD64_GARTAPERTUREBASE 0x94
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#define AMD64_GARTTABLEBASE 0x98
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#define AMD64_GARTCACHECTL 0x9c
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#define AMD64_GARTEN (1<<0)
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#ifdef CONFIG_GART_IOMMU
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extern int gart_iommu_aperture;
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@ -57,6 +57,19 @@ static inline void gart_iommu_hole_init(void)
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extern int agp_amd64_init(void);
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static inline void gart_set_size_and_enable(struct pci_dev *dev, u32 order)
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{
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u32 ctl;
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/*
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* Don't enable translation but enable GART IO and CPU accesses.
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* Also, set DISTLBWALKPRB since GART tables memory is UC.
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*/
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ctl = DISTLBWALKPRB | order << 1;
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pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
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}
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static inline void enable_gart_translation(struct pci_dev *dev, u64 addr)
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{
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u32 tmp, ctl;
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2007-2009 Advanced Micro Devices, Inc.
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* Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
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* Author: Joerg Roedel <joerg.roedel@amd.com>
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* Leo Duran <leo.duran@amd.com>
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*
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2007-2009 Advanced Micro Devices, Inc.
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* Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
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* Author: Joerg Roedel <joerg.roedel@amd.com>
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* Leo Duran <leo.duran@amd.com>
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*
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@ -194,6 +194,39 @@ static inline unsigned long tbl_size(int entry_size)
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return 1UL << shift;
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}
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/* Access to l1 and l2 indexed register spaces */
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static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
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{
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u32 val;
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pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
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pci_read_config_dword(iommu->dev, 0xfc, &val);
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return val;
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}
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static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
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{
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pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
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pci_write_config_dword(iommu->dev, 0xfc, val);
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pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
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}
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static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
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{
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u32 val;
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pci_write_config_dword(iommu->dev, 0xf0, address);
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pci_read_config_dword(iommu->dev, 0xf4, &val);
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return val;
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}
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static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
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{
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pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
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pci_write_config_dword(iommu->dev, 0xf4, val);
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}
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/****************************************************************************
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*
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* AMD IOMMU MMIO register space handling functions
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@ -619,6 +652,7 @@ static void __init init_iommu_from_pci(struct amd_iommu *iommu)
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{
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int cap_ptr = iommu->cap_ptr;
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u32 range, misc;
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int i, j;
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pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
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&iommu->cap);
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@ -633,12 +667,29 @@ static void __init init_iommu_from_pci(struct amd_iommu *iommu)
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MMIO_GET_LD(range));
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iommu->evt_msi_num = MMIO_MSI_NUM(misc);
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if (is_rd890_iommu(iommu->dev)) {
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pci_read_config_dword(iommu->dev, 0xf0, &iommu->cache_cfg[0]);
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pci_read_config_dword(iommu->dev, 0xf4, &iommu->cache_cfg[1]);
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pci_read_config_dword(iommu->dev, 0xf8, &iommu->cache_cfg[2]);
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pci_read_config_dword(iommu->dev, 0xfc, &iommu->cache_cfg[3]);
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}
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if (!is_rd890_iommu(iommu->dev))
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return;
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/*
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* Some rd890 systems may not be fully reconfigured by the BIOS, so
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* it's necessary for us to store this information so it can be
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* reprogrammed on resume
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*/
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pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
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&iommu->stored_addr_lo);
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pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
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&iommu->stored_addr_hi);
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/* Low bit locks writes to configuration space */
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iommu->stored_addr_lo &= ~1;
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for (i = 0; i < 6; i++)
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for (j = 0; j < 0x12; j++)
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iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
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for (i = 0; i < 0x83; i++)
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iommu->stored_l2[i] = iommu_read_l2(iommu, i);
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}
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/*
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@ -1127,14 +1178,53 @@ static void iommu_init_flags(struct amd_iommu *iommu)
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iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
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}
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static void iommu_apply_quirks(struct amd_iommu *iommu)
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static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
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{
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if (is_rd890_iommu(iommu->dev)) {
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pci_write_config_dword(iommu->dev, 0xf0, iommu->cache_cfg[0]);
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pci_write_config_dword(iommu->dev, 0xf4, iommu->cache_cfg[1]);
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pci_write_config_dword(iommu->dev, 0xf8, iommu->cache_cfg[2]);
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pci_write_config_dword(iommu->dev, 0xfc, iommu->cache_cfg[3]);
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}
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int i, j;
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u32 ioc_feature_control;
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struct pci_dev *pdev = NULL;
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/* RD890 BIOSes may not have completely reconfigured the iommu */
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if (!is_rd890_iommu(iommu->dev))
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return;
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/*
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* First, we need to ensure that the iommu is enabled. This is
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* controlled by a register in the northbridge
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*/
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pdev = pci_get_bus_and_slot(iommu->dev->bus->number, PCI_DEVFN(0, 0));
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if (!pdev)
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return;
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/* Select Northbridge indirect register 0x75 and enable writing */
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pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
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pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
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/* Enable the iommu */
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if (!(ioc_feature_control & 0x1))
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pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
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pci_dev_put(pdev);
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/* Restore the iommu BAR */
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pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
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iommu->stored_addr_lo);
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pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
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iommu->stored_addr_hi);
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/* Restore the l1 indirect regs for each of the 6 l1s */
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for (i = 0; i < 6; i++)
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for (j = 0; j < 0x12; j++)
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iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
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/* Restore the l2 indirect regs */
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for (i = 0; i < 0x83; i++)
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iommu_write_l2(iommu, i, iommu->stored_l2[i]);
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/* Lock PCI setup registers */
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pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
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iommu->stored_addr_lo | 1);
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}
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/*
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@ -1147,7 +1237,6 @@ static void enable_iommus(void)
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for_each_iommu(iommu) {
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iommu_disable(iommu);
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iommu_apply_quirks(iommu);
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iommu_init_flags(iommu);
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iommu_set_device_table(iommu);
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iommu_enable_command_buffer(iommu);
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@ -1173,6 +1262,11 @@ static void disable_iommus(void)
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static int amd_iommu_resume(struct sys_device *dev)
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{
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struct amd_iommu *iommu;
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for_each_iommu(iommu)
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iommu_apply_resume_quirks(iommu);
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/* re-load the hardware */
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enable_iommus();
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@ -307,7 +307,7 @@ void __init early_gart_iommu_check(void)
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continue;
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ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
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aper_enabled = ctl & AMD64_GARTEN;
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aper_enabled = ctl & GARTEN;
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aper_order = (ctl >> 1) & 7;
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aper_size = (32 * 1024 * 1024) << aper_order;
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aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
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@ -362,7 +362,7 @@ void __init early_gart_iommu_check(void)
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continue;
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ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
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ctl &= ~AMD64_GARTEN;
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ctl &= ~GARTEN;
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write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
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}
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}
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@ -505,8 +505,13 @@ out:
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/* Fix up the north bridges */
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for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
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int bus;
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int dev_base, dev_limit;
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int bus, dev_base, dev_limit;
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/*
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* Don't enable translation yet but enable GART IO and CPU
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* accesses and set DISTLBWALKPRB since GART table memory is UC.
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*/
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u32 ctl = DISTLBWALKPRB | aper_order << 1;
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bus = bus_dev_ranges[i].bus;
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dev_base = bus_dev_ranges[i].dev_base;
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@ -515,10 +520,7 @@ out:
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if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
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continue;
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/* Don't enable translation yet. That is done later.
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Assume this BIOS didn't initialise the GART so
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just overwrite all previous bits */
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write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, aper_order << 1);
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write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
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write_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE, aper_alloc >> 25);
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}
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}
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@ -601,7 +601,7 @@ static void gart_fixup_northbridges(struct sys_device *dev)
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* Don't enable translations just yet. That is the next
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* step. Restore the pre-suspend aperture settings.
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*/
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pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, aperture_order << 1);
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gart_set_size_and_enable(dev, aperture_order);
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pci_write_config_dword(dev, AMD64_GARTAPERTUREBASE, aperture_alloc >> 25);
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}
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}
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@ -199,7 +199,7 @@ static void amd64_cleanup(void)
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struct pci_dev *dev = k8_northbridges[i];
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/* disable gart translation */
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pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &tmp);
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tmp &= ~AMD64_GARTEN;
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tmp &= ~GARTEN;
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pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, tmp);
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}
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}
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@ -313,7 +313,7 @@ static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
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if (order < 0 || !agp_aperture_valid(aper, (32*1024*1024)<<order))
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return -1;
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pci_write_config_dword(nb, AMD64_GARTAPERTURECTL, order << 1);
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gart_set_size_and_enable(nb, order);
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pci_write_config_dword(nb, AMD64_GARTAPERTUREBASE, aper >> 25);
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return 0;
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@ -984,7 +984,9 @@ int agp_generic_create_gatt_table(struct agp_bridge_data *bridge)
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bridge->driver->cache_flush();
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#ifdef CONFIG_X86
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set_memory_uc((unsigned long)table, 1 << page_order);
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if (set_memory_uc((unsigned long)table, 1 << page_order))
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printk(KERN_WARNING "Could not set GATT table memory to UC!");
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bridge->gatt_table = (void *)table;
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#else
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bridge->gatt_table = ioremap_nocache(virt_to_phys(table),
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