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pinctrl: cherryview: Use raw_spinlock for locking
When running -rt kernel and an interrupt happens on a GPIO line controlled by Intel Cherryview/Braswell pinctrl driver we get: BUG: sleeping function called from invalid context at kernel/locking/rtmutex.c:917 in_atomic(): 1, irqs_disabled(): 1, pid: 0, name: swapper/0 Preemption disabled at:[<ffffffff81092e9f>] cpu_startup_entry+0x17f/0x480 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.1.5-rt5 #16 ... Call Trace: <IRQ> [<ffffffff816283c6>] dump_stack+0x4a/0x61 [<ffffffff81077e17>] ___might_sleep+0xe7/0x170 [<ffffffff8162d6cf>] rt_spin_lock+0x1f/0x50 [<ffffffff812e52ed>] chv_gpio_irq_ack+0x3d/0xa0 [<ffffffff810a72f5>] handle_edge_irq+0x75/0x180 [<ffffffff810a3457>] generic_handle_irq+0x27/0x40 [<ffffffff812e57de>] chv_gpio_irq_handler+0x7e/0x110 [<ffffffff810050aa>] handle_irq+0xaa/0x190 ... This is because desc->lock is raw_spinlock and is held when chv_gpio_irq_ack() is called by the genirq core. chv_gpio_irq_ack() in turn takes pctrl->lock which in -rt is an rt-mutex causing might_sleep() rightfully to complain about sleeping function called from invalid context. In order to keep -rt happy but at the same time make sure that register accesses get serialized, convert the driver to use raw_spinlock instead. Suggested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Mika Westerberg
Linus Walleij
parent
78e1c89693
commit
109fdf1572
@ -174,7 +174,7 @@ struct chv_pinctrl {
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struct pinctrl_dev *pctldev;
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struct gpio_chip chip;
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void __iomem *regs;
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spinlock_t lock;
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raw_spinlock_t lock;
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unsigned intr_lines[16];
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const struct chv_community *community;
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u32 saved_intmask;
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@ -720,13 +720,13 @@ static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
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u32 ctrl0, ctrl1;
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bool locked;
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spin_lock_irqsave(&pctrl->lock, flags);
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
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ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1));
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locked = chv_pad_locked(pctrl, offset);
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spin_unlock_irqrestore(&pctrl->lock, flags);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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if (ctrl0 & CHV_PADCTRL0_GPIOEN) {
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seq_puts(s, "GPIO ");
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@ -789,14 +789,14 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
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grp = &pctrl->community->groups[group];
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spin_lock_irqsave(&pctrl->lock, flags);
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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/* Check first that the pad is not locked */
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for (i = 0; i < grp->npins; i++) {
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if (chv_pad_locked(pctrl, grp->pins[i])) {
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dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n",
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grp->pins[i]);
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spin_unlock_irqrestore(&pctrl->lock, flags);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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return -EBUSY;
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}
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}
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@ -839,7 +839,7 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
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pin, altfunc->mode, altfunc->invert_oe ? "" : "not ");
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}
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spin_unlock_irqrestore(&pctrl->lock, flags);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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return 0;
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}
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@ -853,13 +853,13 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
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void __iomem *reg;
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u32 value;
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spin_lock_irqsave(&pctrl->lock, flags);
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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if (chv_pad_locked(pctrl, offset)) {
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value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
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if (!(value & CHV_PADCTRL0_GPIOEN)) {
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/* Locked so cannot enable */
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spin_unlock_irqrestore(&pctrl->lock, flags);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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return -EBUSY;
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}
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} else {
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@ -899,7 +899,7 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
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chv_writel(value, reg);
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}
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spin_unlock_irqrestore(&pctrl->lock, flags);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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return 0;
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}
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@ -913,13 +913,13 @@ static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
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void __iomem *reg;
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u32 value;
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spin_lock_irqsave(&pctrl->lock, flags);
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
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value = readl(reg) & ~CHV_PADCTRL0_GPIOEN;
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chv_writel(value, reg);
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spin_unlock_irqrestore(&pctrl->lock, flags);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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}
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static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
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@ -931,7 +931,7 @@ static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
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unsigned long flags;
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u32 ctrl0;
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spin_lock_irqsave(&pctrl->lock, flags);
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK;
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if (input)
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@ -940,7 +940,7 @@ static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
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ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
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chv_writel(ctrl0, reg);
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spin_unlock_irqrestore(&pctrl->lock, flags);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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return 0;
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}
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@ -965,10 +965,10 @@ static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin,
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u16 arg = 0;
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u32 term;
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spin_lock_irqsave(&pctrl->lock, flags);
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
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ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
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spin_unlock_irqrestore(&pctrl->lock, flags);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
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@ -1042,7 +1042,7 @@ static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin,
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unsigned long flags;
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u32 ctrl0, pull;
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spin_lock_irqsave(&pctrl->lock, flags);
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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ctrl0 = readl(reg);
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switch (param) {
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@ -1065,7 +1065,7 @@ static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin,
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pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
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break;
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default:
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spin_unlock_irqrestore(&pctrl->lock, flags);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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return -EINVAL;
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}
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@ -1083,7 +1083,7 @@ static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin,
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pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
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break;
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default:
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spin_unlock_irqrestore(&pctrl->lock, flags);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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return -EINVAL;
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}
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@ -1091,12 +1091,12 @@ static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin,
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break;
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default:
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spin_unlock_irqrestore(&pctrl->lock, flags);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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return -EINVAL;
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}
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chv_writel(ctrl0, reg);
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spin_unlock_irqrestore(&pctrl->lock, flags);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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return 0;
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}
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@ -1172,9 +1172,9 @@ static int chv_gpio_get(struct gpio_chip *chip, unsigned offset)
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unsigned long flags;
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u32 ctrl0, cfg;
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spin_lock_irqsave(&pctrl->lock, flags);
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
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spin_unlock_irqrestore(&pctrl->lock, flags);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
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cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
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@ -1192,7 +1192,7 @@ static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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void __iomem *reg;
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u32 ctrl0;
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spin_lock_irqsave(&pctrl->lock, flags);
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
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ctrl0 = readl(reg);
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@ -1204,7 +1204,7 @@ static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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chv_writel(ctrl0, reg);
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spin_unlock_irqrestore(&pctrl->lock, flags);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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}
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static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
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@ -1214,9 +1214,9 @@ static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
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u32 ctrl0, direction;
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unsigned long flags;
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spin_lock_irqsave(&pctrl->lock, flags);
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
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spin_unlock_irqrestore(&pctrl->lock, flags);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
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direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
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@ -1254,14 +1254,14 @@ static void chv_gpio_irq_ack(struct irq_data *d)
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int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d));
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u32 intr_line;
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spin_lock(&pctrl->lock);
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raw_spin_lock(&pctrl->lock);
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intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
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intr_line &= CHV_PADCTRL0_INTSEL_MASK;
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intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
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chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT);
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spin_unlock(&pctrl->lock);
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raw_spin_unlock(&pctrl->lock);
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}
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static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
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@ -1272,7 +1272,7 @@ static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
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u32 value, intr_line;
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unsigned long flags;
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spin_lock_irqsave(&pctrl->lock, flags);
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
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intr_line &= CHV_PADCTRL0_INTSEL_MASK;
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@ -1285,7 +1285,7 @@ static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
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value |= BIT(intr_line);
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chv_writel(value, pctrl->regs + CHV_INTMASK);
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spin_unlock_irqrestore(&pctrl->lock, flags);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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}
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static void chv_gpio_irq_mask(struct irq_data *d)
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@ -1319,7 +1319,7 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
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unsigned long flags;
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u32 intsel, value;
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spin_lock_irqsave(&pctrl->lock, flags);
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
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intsel &= CHV_PADCTRL0_INTSEL_MASK;
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intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
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@ -1334,7 +1334,7 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
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irq_set_handler_locked(d, handler);
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pctrl->intr_lines[intsel] = offset;
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}
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spin_unlock_irqrestore(&pctrl->lock, flags);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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}
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chv_gpio_irq_unmask(d);
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@ -1350,7 +1350,7 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned type)
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unsigned long flags;
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u32 value;
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spin_lock_irqsave(&pctrl->lock, flags);
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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/*
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* Pins which can be used as shared interrupt are configured in
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@ -1399,7 +1399,7 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned type)
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else if (type & IRQ_TYPE_LEVEL_MASK)
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irq_set_handler_locked(d, handle_level_irq);
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spin_unlock_irqrestore(&pctrl->lock, flags);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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return 0;
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}
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@ -1511,7 +1511,7 @@ static int chv_pinctrl_probe(struct platform_device *pdev)
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if (i == ARRAY_SIZE(chv_communities))
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return -ENODEV;
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spin_lock_init(&pctrl->lock);
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raw_spin_lock_init(&pctrl->lock);
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pctrl->dev = &pdev->dev;
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#ifdef CONFIG_PM_SLEEP
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