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drm/radeon/kms: add some missing semaphore init
Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -1455,6 +1455,7 @@ int evergreen_cp_resume(struct radeon_device *rdev)
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#endif
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#endif
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WREG32(CP_RB_CNTL, tmp);
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WREG32(CP_RB_CNTL, tmp);
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WREG32(CP_SEM_WAIT_TIMER, 0x0);
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WREG32(CP_SEM_WAIT_TIMER, 0x0);
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WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
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/* Set the write pointer delay */
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/* Set the write pointer delay */
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WREG32(CP_RB_WPTR_DELAY, 0);
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WREG32(CP_RB_WPTR_DELAY, 0);
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@ -108,6 +108,7 @@
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#define CP_RB_WPTR_ADDR_HI 0xC11C
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#define CP_RB_WPTR_ADDR_HI 0xC11C
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#define CP_RB_WPTR_DELAY 0x8704
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#define CP_RB_WPTR_DELAY 0x8704
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#define CP_SEM_WAIT_TIMER 0x85BC
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#define CP_SEM_WAIT_TIMER 0x85BC
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#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8
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#define CP_DEBUG 0xC1FC
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#define CP_DEBUG 0xC1FC
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@ -1219,6 +1219,7 @@ int cayman_cp_resume(struct radeon_device *rdev)
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RREG32(GRBM_SOFT_RESET);
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RREG32(GRBM_SOFT_RESET);
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WREG32(CP_SEM_WAIT_TIMER, 0x0);
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WREG32(CP_SEM_WAIT_TIMER, 0x0);
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WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
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/* Set the write pointer delay */
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/* Set the write pointer delay */
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WREG32(CP_RB_WPTR_DELAY, 0);
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WREG32(CP_RB_WPTR_DELAY, 0);
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@ -222,6 +222,7 @@
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#define SCRATCH_UMSK 0x8540
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#define SCRATCH_UMSK 0x8540
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#define SCRATCH_ADDR 0x8544
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#define SCRATCH_ADDR 0x8544
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#define CP_SEM_WAIT_TIMER 0x85BC
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#define CP_SEM_WAIT_TIMER 0x85BC
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#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8
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#define CP_COHER_CNTL2 0x85E8
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#define CP_COHER_CNTL2 0x85E8
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#define CP_ME_CNTL 0x86D8
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#define CP_ME_CNTL 0x86D8
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#define CP_ME_HALT (1 << 28)
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#define CP_ME_HALT (1 << 28)
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