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EDAC, altera: Refactor for Altera CycloneV SoC
The Arria10 SoC uses a completely different SDRAM controller from the earlier CycloneV and ArriaV SoCs. This patch abstracts the SDRAM bits for the CycloneV/ArriaV SoCs in preparation for the Arria10 support. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: devicetree@vger.kernel.org Cc: dinguyen@opensource.altera.com Cc: galak@codeaurora.org Cc: grant.likely@linaro.org Cc: ijc+devicetree@hellion.org.uk Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac <linux-edac@vger.kernel.org> Cc: m.chehab@samsung.com Cc: mark.rutland@arm.com Cc: pawel.moll@arm.com Cc: robh+dt@kernel.org Cc: tthayer.linux@gmail.com Link: http://lkml.kernel.org/r/1433428128-7292-3-git-send-email-tthayer@opensource.altera.com Signed-off-by: Borislav Petkov <bp@suse.de>
This commit is contained in:
Thor Thayer
Borislav Petkov
parent
f9ae487e04
commit
143f4a5ac5
@ -1,5 +1,5 @@
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/*
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* Copyright Altera Corporation (C) 2014. All rights reserved.
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* Copyright Altera Corporation (C) 2014-2015. All rights reserved.
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* Copyright 2011-2012 Calxeda, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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@ -28,111 +28,64 @@
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#include <linux/types.h>
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#include <linux/uaccess.h>
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#include "altera_edac.h"
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#include "edac_core.h"
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#include "edac_module.h"
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#define EDAC_MOD_STR "altera_edac"
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#define EDAC_VERSION "1"
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/* SDRAM Controller CtrlCfg Register */
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#define CTLCFG_OFST 0x00
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/* SDRAM Controller CtrlCfg Register Bit Masks */
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#define CTLCFG_ECC_EN 0x400
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#define CTLCFG_ECC_CORR_EN 0x800
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#define CTLCFG_GEN_SB_ERR 0x2000
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#define CTLCFG_GEN_DB_ERR 0x4000
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#define CTLCFG_ECC_AUTO_EN (CTLCFG_ECC_EN | \
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CTLCFG_ECC_CORR_EN)
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/* SDRAM Controller Address Width Register */
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#define DRAMADDRW_OFST 0x2C
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/* SDRAM Controller Address Widths Field Register */
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#define DRAMADDRW_COLBIT_MASK 0x001F
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#define DRAMADDRW_COLBIT_SHIFT 0
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#define DRAMADDRW_ROWBIT_MASK 0x03E0
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#define DRAMADDRW_ROWBIT_SHIFT 5
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#define DRAMADDRW_BANKBIT_MASK 0x1C00
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#define DRAMADDRW_BANKBIT_SHIFT 10
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#define DRAMADDRW_CSBIT_MASK 0xE000
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#define DRAMADDRW_CSBIT_SHIFT 13
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/* SDRAM Controller Interface Data Width Register */
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#define DRAMIFWIDTH_OFST 0x30
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/* SDRAM Controller Interface Data Width Defines */
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#define DRAMIFWIDTH_16B_ECC 24
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#define DRAMIFWIDTH_32B_ECC 40
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/* SDRAM Controller DRAM Status Register */
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#define DRAMSTS_OFST 0x38
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/* SDRAM Controller DRAM Status Register Bit Masks */
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#define DRAMSTS_SBEERR 0x04
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#define DRAMSTS_DBEERR 0x08
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#define DRAMSTS_CORR_DROP 0x10
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/* SDRAM Controller DRAM IRQ Register */
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#define DRAMINTR_OFST 0x3C
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/* SDRAM Controller DRAM IRQ Register Bit Masks */
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#define DRAMINTR_INTREN 0x01
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#define DRAMINTR_SBEMASK 0x02
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#define DRAMINTR_DBEMASK 0x04
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#define DRAMINTR_CORRDROPMASK 0x08
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#define DRAMINTR_INTRCLR 0x10
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/* SDRAM Controller Single Bit Error Count Register */
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#define SBECOUNT_OFST 0x40
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/* SDRAM Controller Single Bit Error Count Register Bit Masks */
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#define SBECOUNT_MASK 0x0F
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/* SDRAM Controller Double Bit Error Count Register */
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#define DBECOUNT_OFST 0x44
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/* SDRAM Controller Double Bit Error Count Register Bit Masks */
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#define DBECOUNT_MASK 0x0F
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/* SDRAM Controller ECC Error Address Register */
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#define ERRADDR_OFST 0x48
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/* SDRAM Controller ECC Error Address Register Bit Masks */
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#define ERRADDR_MASK 0xFFFFFFFF
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/* Altera SDRAM Memory Controller data */
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struct altr_sdram_mc_data {
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struct regmap *mc_vbase;
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static const struct altr_sdram_prv_data c5_data = {
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.ecc_ctrl_offset = CV_CTLCFG_OFST,
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.ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN,
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.ecc_stat_offset = CV_DRAMSTS_OFST,
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.ecc_stat_ce_mask = CV_DRAMSTS_SBEERR,
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.ecc_stat_ue_mask = CV_DRAMSTS_DBEERR,
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.ecc_saddr_offset = CV_ERRADDR_OFST,
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.ecc_cecnt_offset = CV_SBECOUNT_OFST,
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.ecc_uecnt_offset = CV_DBECOUNT_OFST,
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.ecc_irq_en_offset = CV_DRAMINTR_OFST,
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.ecc_irq_en_mask = CV_DRAMINTR_INTREN,
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.ecc_irq_clr_offset = CV_DRAMINTR_OFST,
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.ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN),
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.ecc_cnt_rst_offset = CV_DRAMINTR_OFST,
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.ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR,
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#ifdef CONFIG_EDAC_DEBUG
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.ce_ue_trgr_offset = CV_CTLCFG_OFST,
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.ce_set_mask = CV_CTLCFG_GEN_SB_ERR,
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.ue_set_mask = CV_CTLCFG_GEN_DB_ERR,
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#endif
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};
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static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
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{
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struct mem_ctl_info *mci = dev_id;
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struct altr_sdram_mc_data *drvdata = mci->pvt_info;
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const struct altr_sdram_prv_data *priv = drvdata->data;
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u32 status, err_count, err_addr;
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/* Error Address is shared by both SBE & DBE */
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regmap_read(drvdata->mc_vbase, ERRADDR_OFST, &err_addr);
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regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset, &err_addr);
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regmap_read(drvdata->mc_vbase, DRAMSTS_OFST, &status);
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regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status);
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if (status & DRAMSTS_DBEERR) {
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regmap_read(drvdata->mc_vbase, DBECOUNT_OFST, &err_count);
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if (status & priv->ecc_stat_ue_mask) {
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regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset,
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&err_count);
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panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
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err_count, err_addr);
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}
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if (status & DRAMSTS_SBEERR) {
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regmap_read(drvdata->mc_vbase, SBECOUNT_OFST, &err_count);
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if (status & priv->ecc_stat_ce_mask) {
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regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset,
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&err_count);
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
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err_addr >> PAGE_SHIFT,
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err_addr & ~PAGE_MASK, 0,
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0, 0, -1, mci->ctl_name, "");
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}
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regmap_write(drvdata->mc_vbase, DRAMINTR_OFST,
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(DRAMINTR_INTRCLR | DRAMINTR_INTREN));
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regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset,
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priv->ecc_irq_clr_mask);
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return IRQ_HANDLED;
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}
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@ -144,6 +97,7 @@ static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
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{
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struct mem_ctl_info *mci = file->private_data;
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struct altr_sdram_mc_data *drvdata = mci->pvt_info;
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const struct altr_sdram_prv_data *priv = drvdata->data;
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u32 *ptemp;
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dma_addr_t dma_handle;
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u32 reg, read_reg;
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@ -156,8 +110,9 @@ static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
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return -ENOMEM;
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}
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regmap_read(drvdata->mc_vbase, CTLCFG_OFST, &read_reg);
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read_reg &= ~(CTLCFG_GEN_SB_ERR | CTLCFG_GEN_DB_ERR);
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regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
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&read_reg);
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read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask);
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/* Error are injected by writing a word while the SBE or DBE
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* bit in the CTLCFG register is set. Reading the word will
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@ -166,20 +121,20 @@ static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
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if (count == 3) {
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edac_printk(KERN_ALERT, EDAC_MC,
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"Inject Double bit error\n");
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regmap_write(drvdata->mc_vbase, CTLCFG_OFST,
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(read_reg | CTLCFG_GEN_DB_ERR));
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regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
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(read_reg | priv->ue_set_mask));
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} else {
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edac_printk(KERN_ALERT, EDAC_MC,
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"Inject Single bit error\n");
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regmap_write(drvdata->mc_vbase, CTLCFG_OFST,
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(read_reg | CTLCFG_GEN_SB_ERR));
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regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
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(read_reg | priv->ce_set_mask));
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}
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ptemp[0] = 0x5A5A5A5A;
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ptemp[1] = 0xA5A5A5A5;
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/* Clear the error injection bits */
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regmap_write(drvdata->mc_vbase, CTLCFG_OFST, read_reg);
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regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg);
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/* Ensure it has been written out */
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wmb();
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@ -246,18 +201,29 @@ static unsigned long get_total_mem(void)
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return total_mem;
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}
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static const struct of_device_id altr_sdram_ctrl_of_match[] = {
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{ .compatible = "altr,sdram-edac", .data = (void *)&c5_data},
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{},
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};
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MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
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static int altr_sdram_probe(struct platform_device *pdev)
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{
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const struct of_device_id *id;
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struct edac_mc_layer layers[2];
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struct mem_ctl_info *mci;
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struct altr_sdram_mc_data *drvdata;
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const struct altr_sdram_prv_data *priv;
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struct regmap *mc_vbase;
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struct dimm_info *dimm;
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u32 read_reg, mem_size;
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int irq;
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int res = 0;
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u32 read_reg;
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int irq, res = 0;
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unsigned long mem_size;
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id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev);
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if (!id)
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return -ENODEV;
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/* Validate the SDRAM controller has ECC enabled */
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/* Grab the register range from the sdr controller in device tree */
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mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
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"altr,sdr-syscon");
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@ -267,8 +233,13 @@ static int altr_sdram_probe(struct platform_device *pdev)
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return -ENODEV;
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}
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if (regmap_read(mc_vbase, CTLCFG_OFST, &read_reg) ||
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((read_reg & CTLCFG_ECC_AUTO_EN) != CTLCFG_ECC_AUTO_EN)) {
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/* Check specific dependencies for the module */
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priv = of_match_node(altr_sdram_ctrl_of_match,
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pdev->dev.of_node)->data;
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/* Validate the SDRAM controller has ECC enabled */
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if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) ||
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((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
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edac_printk(KERN_ERR, EDAC_MC,
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"No ECC/ECC disabled [0x%08X]\n", read_reg);
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return -ENODEV;
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@ -281,10 +252,27 @@ static int altr_sdram_probe(struct platform_device *pdev)
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return -ENODEV;
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}
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/* Ensure the SDRAM Interrupt is disabled and cleared */
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if (regmap_write(mc_vbase, DRAMINTR_OFST, DRAMINTR_INTRCLR)) {
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/* Ensure the SDRAM Interrupt is disabled */
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if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset,
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priv->ecc_irq_en_mask, 0)) {
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edac_printk(KERN_ERR, EDAC_MC,
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"Error clearing SDRAM ECC IRQ\n");
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"Error disabling SDRAM ECC IRQ\n");
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return -ENODEV;
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}
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/* Toggle to clear the SDRAM Error count */
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if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
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priv->ecc_cnt_rst_mask,
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priv->ecc_cnt_rst_mask)) {
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edac_printk(KERN_ERR, EDAC_MC,
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"Error clearing SDRAM ECC count\n");
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return -ENODEV;
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}
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if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
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priv->ecc_cnt_rst_mask, 0)) {
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edac_printk(KERN_ERR, EDAC_MC,
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"Error clearing SDRAM ECC count\n");
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return -ENODEV;
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}
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@ -309,9 +297,12 @@ static int altr_sdram_probe(struct platform_device *pdev)
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mci->pdev = &pdev->dev;
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drvdata = mci->pvt_info;
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drvdata->mc_vbase = mc_vbase;
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drvdata->data = priv;
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platform_set_drvdata(pdev, mci);
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if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
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edac_printk(KERN_ERR, EDAC_MC,
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"Unable to get managed device resource\n");
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res = -ENOMEM;
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goto free;
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}
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@ -345,8 +336,9 @@ static int altr_sdram_probe(struct platform_device *pdev)
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goto err2;
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}
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if (regmap_write(drvdata->mc_vbase, DRAMINTR_OFST,
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(DRAMINTR_INTRCLR | DRAMINTR_INTREN))) {
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/* Infrastructure ready - enable the IRQ */
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if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
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priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
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edac_mc_printk(mci, KERN_ERR,
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"Error enabling SDRAM ECC IRQ\n");
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res = -ENODEV;
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@ -382,12 +374,6 @@ static int altr_sdram_remove(struct platform_device *pdev)
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return 0;
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}
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static const struct of_device_id altr_sdram_ctrl_of_match[] = {
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{ .compatible = "altr,sdram-edac", },
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{},
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};
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MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
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static struct platform_driver altr_sdram_edac_driver = {
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.probe = altr_sdram_probe,
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.remove = altr_sdram_remove,
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116
drivers/edac/altera_edac.h
Normal file
116
drivers/edac/altera_edac.h
Normal file
@ -0,0 +1,116 @@
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/*
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*
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* Copyright (C) 2015 Altera Corporation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _ALTERA_EDAC_H
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#define _ALTERA_EDAC_H
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#include <linux/edac.h>
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#include <linux/types.h>
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/* SDRAM Controller CtrlCfg Register */
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#define CV_CTLCFG_OFST 0x00
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/* SDRAM Controller CtrlCfg Register Bit Masks */
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#define CV_CTLCFG_ECC_EN 0x400
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#define CV_CTLCFG_ECC_CORR_EN 0x800
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#define CV_CTLCFG_GEN_SB_ERR 0x2000
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#define CV_CTLCFG_GEN_DB_ERR 0x4000
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#define CV_CTLCFG_ECC_AUTO_EN (CV_CTLCFG_ECC_EN | \
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CV_CTLCFG_ECC_CORR_EN)
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/* SDRAM Controller Address Width Register */
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#define CV_DRAMADDRW_OFST 0x2C
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/* SDRAM Controller Address Widths Field Register */
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#define DRAMADDRW_COLBIT_MASK 0x001F
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#define DRAMADDRW_COLBIT_SHIFT 0
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#define DRAMADDRW_ROWBIT_MASK 0x03E0
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#define DRAMADDRW_ROWBIT_SHIFT 5
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#define CV_DRAMADDRW_BANKBIT_MASK 0x1C00
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#define CV_DRAMADDRW_BANKBIT_SHIFT 10
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#define CV_DRAMADDRW_CSBIT_MASK 0xE000
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#define CV_DRAMADDRW_CSBIT_SHIFT 13
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/* SDRAM Controller Interface Data Width Register */
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#define CV_DRAMIFWIDTH_OFST 0x30
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/* SDRAM Controller Interface Data Width Defines */
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#define CV_DRAMIFWIDTH_16B_ECC 24
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#define CV_DRAMIFWIDTH_32B_ECC 40
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/* SDRAM Controller DRAM Status Register */
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#define CV_DRAMSTS_OFST 0x38
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/* SDRAM Controller DRAM Status Register Bit Masks */
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#define CV_DRAMSTS_SBEERR 0x04
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#define CV_DRAMSTS_DBEERR 0x08
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#define CV_DRAMSTS_CORR_DROP 0x10
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/* SDRAM Controller DRAM IRQ Register */
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#define CV_DRAMINTR_OFST 0x3C
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/* SDRAM Controller DRAM IRQ Register Bit Masks */
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#define CV_DRAMINTR_INTREN 0x01
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#define CV_DRAMINTR_SBEMASK 0x02
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#define CV_DRAMINTR_DBEMASK 0x04
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#define CV_DRAMINTR_CORRDROPMASK 0x08
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#define CV_DRAMINTR_INTRCLR 0x10
|
||||
|
||||
/* SDRAM Controller Single Bit Error Count Register */
|
||||
#define CV_SBECOUNT_OFST 0x40
|
||||
|
||||
/* SDRAM Controller Double Bit Error Count Register */
|
||||
#define CV_DBECOUNT_OFST 0x44
|
||||
|
||||
/* SDRAM Controller ECC Error Address Register */
|
||||
#define CV_ERRADDR_OFST 0x48
|
||||
|
||||
struct altr_sdram_prv_data {
|
||||
int ecc_ctrl_offset;
|
||||
int ecc_ctl_en_mask;
|
||||
int ecc_cecnt_offset;
|
||||
int ecc_uecnt_offset;
|
||||
int ecc_stat_offset;
|
||||
int ecc_stat_ce_mask;
|
||||
int ecc_stat_ue_mask;
|
||||
int ecc_saddr_offset;
|
||||
int ecc_daddr_offset;
|
||||
int ecc_irq_en_offset;
|
||||
int ecc_irq_en_mask;
|
||||
int ecc_irq_clr_offset;
|
||||
int ecc_irq_clr_mask;
|
||||
int ecc_cnt_rst_offset;
|
||||
int ecc_cnt_rst_mask;
|
||||
#ifdef CONFIG_EDAC_DEBUG
|
||||
struct edac_dev_sysfs_attribute *eccmgr_sysfs_attr;
|
||||
int ecc_enable_mask;
|
||||
int ce_set_mask;
|
||||
int ue_set_mask;
|
||||
int ce_ue_trgr_offset;
|
||||
#endif
|
||||
};
|
||||
|
||||
/* Altera SDRAM Memory Controller data */
|
||||
struct altr_sdram_mc_data {
|
||||
struct regmap *mc_vbase;
|
||||
int sb_irq;
|
||||
int db_irq;
|
||||
const struct altr_sdram_prv_data *data;
|
||||
};
|
||||
|
||||
#endif /* #ifndef _ALTERA_EDAC_H */
|
||||
Loading…
Reference in New Issue
Block a user