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ARM: S5PV210: Correct clock register properties
1. Corrected shift values of I2S and UART clocks (CLK_GATE_IP3), which were
defined incorrectly.
2. Corrected shift values of sclk_audio, uclk1, sclk_fimd, sclk_mmc,
sclk_spi, sclk_pwm, which had duplicated .enable/.ctrlbit with their
twins defined in struct clk init_clocks_disable[] and struct clk
init_clocks[]. We've changed their .enable/.ctrlbit to use CLK_SRC_MASK
register to avoid the duplicated clock problem described below.
NOTE: Duplicated Clock Problem
Please note that each clock definition should access different control
register; otherwise, the system may suffer lockups. For example, if we
have two clock definitions "a" and "b" which access the same register
(and the shift value). Then, when we do:
module A
clk = clk_get("a");
clk->clk_enable(clk);
module B (context switch)
clk = clk_get("b");
clk->clk_enable(clk);
do something with clk.
clk->clk_disable(clk);
module A (context switch)
do something with clk
* At this point, the system may hang.
Therefore, there should be no clock definitions with the same contol
register/shift. If we need to create "aliases", then, creating child
clocks sharing the clock should be fine.
3. Corrected other sclk_* shift values and access registers.
Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
[kgene.kim@samsung.com: minor title and message fix]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
MyungJoo Ham
Kukjin Kim
parent
79fc72d6d3
commit
154d62e4cd
@ -183,6 +183,11 @@ static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
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return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
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}
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static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
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}
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static struct clk clk_sclk_hdmi27m = {
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.name = "sclk_hdmi27m",
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.id = -1,
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@ -406,14 +411,14 @@ static struct clk init_clocks_disable[] = {
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.id = 0,
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.parent = &clk_p,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<4),
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.ctrlbit = (1 << 5),
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}, {
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.name = "i2s_v32",
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.id = 1,
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.parent = &clk_p,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<4),
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}
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.ctrlbit = (1 << 6),
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},
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};
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static struct clk init_clocks[] = {
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@ -429,25 +434,25 @@ static struct clk init_clocks[] = {
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.id = 0,
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.parent = &clk_pclk_psys.clk,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<7),
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.ctrlbit = (1 << 17),
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}, {
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.name = "uart",
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.id = 1,
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.parent = &clk_pclk_psys.clk,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<8),
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.ctrlbit = (1 << 18),
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}, {
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.name = "uart",
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.id = 2,
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.parent = &clk_pclk_psys.clk,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<9),
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.ctrlbit = (1 << 19),
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}, {
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.name = "uart",
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.id = 3,
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.parent = &clk_pclk_psys.clk,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<10),
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.ctrlbit = (1 << 20),
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},
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};
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@ -497,8 +502,8 @@ static struct clksrc_clk clk_sclk_dac = {
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.clk = {
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.name = "sclk_dac",
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.id = -1,
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.ctrlbit = (1 << 10),
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.enable = s5pv210_clk_ip1_ctrl,
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.enable = s5pv210_clk_mask0_ctrl,
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.ctrlbit = (1 << 2),
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},
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.sources = &clkset_sclk_dac,
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.reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
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@ -527,8 +532,8 @@ static struct clksrc_clk clk_sclk_hdmi = {
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.clk = {
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.name = "sclk_hdmi",
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.id = -1,
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.enable = s5pv210_clk_ip1_ctrl,
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.ctrlbit = (1 << 11),
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.enable = s5pv210_clk_mask0_ctrl,
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.ctrlbit = (1 << 0),
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},
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.sources = &clkset_sclk_hdmi,
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.reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
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@ -565,8 +570,8 @@ static struct clksrc_clk clk_sclk_audio0 = {
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.clk = {
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.name = "sclk_audio",
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.id = 0,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1 << 4),
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.enable = s5pv210_clk_mask0_ctrl,
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.ctrlbit = (1 << 24),
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},
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.sources = &clkset_sclk_audio0,
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.reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
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@ -594,8 +599,8 @@ static struct clksrc_clk clk_sclk_audio1 = {
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.clk = {
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.name = "sclk_audio",
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.id = 1,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1 << 5),
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.enable = s5pv210_clk_mask0_ctrl,
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.ctrlbit = (1 << 25),
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},
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.sources = &clkset_sclk_audio1,
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.reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
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@ -623,8 +628,8 @@ static struct clksrc_clk clk_sclk_audio2 = {
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.clk = {
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.name = "sclk_audio",
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.id = 2,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1 << 6),
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.enable = s5pv210_clk_mask0_ctrl,
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.ctrlbit = (1 << 26),
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},
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.sources = &clkset_sclk_audio2,
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.reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
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@ -680,8 +685,8 @@ static struct clksrc_clk clksrcs[] = {
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.clk = {
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.name = "uclk1",
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.id = 0,
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.ctrlbit = (1<<17),
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.enable = s5pv210_clk_ip3_ctrl,
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.enable = s5pv210_clk_mask0_ctrl,
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.ctrlbit = (1 << 12),
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},
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.sources = &clkset_uart,
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.reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
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@ -690,8 +695,8 @@ static struct clksrc_clk clksrcs[] = {
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.clk = {
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.name = "uclk1",
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.id = 1,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1 << 18),
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.enable = s5pv210_clk_mask0_ctrl,
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.ctrlbit = (1 << 13),
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},
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.sources = &clkset_uart,
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.reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
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@ -700,8 +705,8 @@ static struct clksrc_clk clksrcs[] = {
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.clk = {
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.name = "uclk1",
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.id = 2,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1 << 19),
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.enable = s5pv210_clk_mask0_ctrl,
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.ctrlbit = (1 << 14),
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},
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.sources = &clkset_uart,
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.reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
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@ -710,8 +715,8 @@ static struct clksrc_clk clksrcs[] = {
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.clk = {
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.name = "uclk1",
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.id = 3,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1 << 20),
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.enable = s5pv210_clk_mask0_ctrl,
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.ctrlbit = (1 << 15),
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},
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.sources = &clkset_uart,
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.reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
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@ -720,8 +725,8 @@ static struct clksrc_clk clksrcs[] = {
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.clk = {
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.name = "sclk_mixer",
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.id = -1,
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.enable = s5pv210_clk_ip1_ctrl,
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.ctrlbit = (1 << 9),
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.enable = s5pv210_clk_mask0_ctrl,
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.ctrlbit = (1 << 1),
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},
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.sources = &clkset_sclk_mixer,
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.reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
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@ -738,8 +743,8 @@ static struct clksrc_clk clksrcs[] = {
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.clk = {
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.name = "sclk_fimc",
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.id = 0,
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.enable = s5pv210_clk_ip0_ctrl,
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.ctrlbit = (1 << 24),
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.enable = s5pv210_clk_mask1_ctrl,
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.ctrlbit = (1 << 2),
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
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@ -748,8 +753,8 @@ static struct clksrc_clk clksrcs[] = {
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.clk = {
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.name = "sclk_fimc",
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.id = 1,
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.enable = s5pv210_clk_ip0_ctrl,
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.ctrlbit = (1 << 25),
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.enable = s5pv210_clk_mask1_ctrl,
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.ctrlbit = (1 << 3),
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
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@ -758,8 +763,8 @@ static struct clksrc_clk clksrcs[] = {
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.clk = {
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.name = "sclk_fimc",
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.id = 2,
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.enable = s5pv210_clk_ip0_ctrl,
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.ctrlbit = (1 << 26),
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.enable = s5pv210_clk_mask1_ctrl,
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.ctrlbit = (1 << 4),
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
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@ -768,6 +773,8 @@ static struct clksrc_clk clksrcs[] = {
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.clk = {
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.name = "sclk_cam",
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.id = 0,
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.enable = s5pv210_clk_mask0_ctrl,
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.ctrlbit = (1 << 3),
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
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@ -776,6 +783,8 @@ static struct clksrc_clk clksrcs[] = {
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.clk = {
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.name = "sclk_cam",
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.id = 1,
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.enable = s5pv210_clk_mask0_ctrl,
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.ctrlbit = (1 << 4),
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
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@ -784,8 +793,8 @@ static struct clksrc_clk clksrcs[] = {
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.clk = {
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.name = "sclk_fimd",
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.id = -1,
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.enable = s5pv210_clk_ip1_ctrl,
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.ctrlbit = (1 << 0),
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.enable = s5pv210_clk_mask0_ctrl,
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.ctrlbit = (1 << 5),
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
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@ -794,8 +803,8 @@ static struct clksrc_clk clksrcs[] = {
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.clk = {
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.name = "sclk_mmc",
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.id = 0,
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.enable = s5pv210_clk_ip2_ctrl,
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.ctrlbit = (1 << 16),
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.enable = s5pv210_clk_mask0_ctrl,
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.ctrlbit = (1 << 8),
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
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@ -804,8 +813,8 @@ static struct clksrc_clk clksrcs[] = {
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.clk = {
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.name = "sclk_mmc",
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.id = 1,
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.enable = s5pv210_clk_ip2_ctrl,
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.ctrlbit = (1 << 17),
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.enable = s5pv210_clk_mask0_ctrl,
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.ctrlbit = (1 << 9),
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
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@ -814,8 +823,8 @@ static struct clksrc_clk clksrcs[] = {
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.clk = {
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.name = "sclk_mmc",
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.id = 2,
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.enable = s5pv210_clk_ip2_ctrl,
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.ctrlbit = (1 << 18),
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.enable = s5pv210_clk_mask0_ctrl,
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.ctrlbit = (1 << 10),
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
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@ -824,8 +833,8 @@ static struct clksrc_clk clksrcs[] = {
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.clk = {
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.name = "sclk_mmc",
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.id = 3,
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.enable = s5pv210_clk_ip2_ctrl,
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.ctrlbit = (1 << 19),
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.enable = s5pv210_clk_mask0_ctrl,
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.ctrlbit = (1 << 11),
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
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@ -864,8 +873,8 @@ static struct clksrc_clk clksrcs[] = {
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.clk = {
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.name = "sclk_csis",
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.id = -1,
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.enable = s5pv210_clk_ip0_ctrl,
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.ctrlbit = (1 << 31),
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.enable = s5pv210_clk_mask0_ctrl,
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.ctrlbit = (1 << 6),
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
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@ -874,8 +883,8 @@ static struct clksrc_clk clksrcs[] = {
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.clk = {
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.name = "sclk_spi",
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.id = 0,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1 << 12),
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.enable = s5pv210_clk_mask0_ctrl,
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.ctrlbit = (1 << 16),
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
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@ -884,8 +893,8 @@ static struct clksrc_clk clksrcs[] = {
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.clk = {
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.name = "sclk_spi",
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.id = 1,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1 << 13),
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.enable = s5pv210_clk_mask0_ctrl,
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.ctrlbit = (1 << 17),
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
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@ -894,8 +903,8 @@ static struct clksrc_clk clksrcs[] = {
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.clk = {
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.name = "sclk_pwi",
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.id = -1,
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.enable = &s5pv210_clk_ip4_ctrl,
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.ctrlbit = (1 << 2),
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.enable = s5pv210_clk_mask0_ctrl,
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.ctrlbit = (1 << 29),
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
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@ -904,8 +913,8 @@ static struct clksrc_clk clksrcs[] = {
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.clk = {
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.name = "sclk_pwm",
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.id = -1,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1 << 23),
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.enable = s5pv210_clk_mask0_ctrl,
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.ctrlbit = (1 << 19),
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
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