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gpu: ipu-v3: prg: remove counter load enable

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The counter load enable bit has no effect when the shadow register
set is activated. As we always operate the PRG with shadow enabled
it is safe to remove this.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
This commit is contained in:
Lucas Stach 2017-05-03 18:16:46 +02:00 committed by Philipp Zabel
parent 2ea659a9ef
commit 16e9ab820a
1 changed files with 0 additions and 2 deletions
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2
drivers/gpu/ipu-v3/ipu-prg.c
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@ -318,8 +318,6 @@ int ipu_prg_channel_configure(struct ipuv3_channel *ipu_chan,
writel(val, prg->regs + IPU_PRG_BADDR(prg_chan)); writel(val, prg->regs + IPU_PRG_BADDR(prg_chan));
val = readl(prg->regs + IPU_PRG_CTL); val = readl(prg->regs + IPU_PRG_CTL);
/* counter load enable */
val |= IPU_PRG_CTL_CNT_LOAD_EN(prg_chan);
/* config AXI ID */ /* config AXI ID */
val &= ~(IPU_PRG_CTL_SOFT_ARID_MASK << val &= ~(IPU_PRG_CTL_SOFT_ARID_MASK <<
IPU_PRG_CTL_SOFT_ARID_SHIFT(prg_chan)); IPU_PRG_CTL_SOFT_ARID_SHIFT(prg_chan));