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Merge branch 'defxx-next'
Maciej W. Rozycki says: ==================== defxx: DEFEA fixes and updates I have finally got my hands on an EISA variation of the board (DEC FDDIcontroller/EISA aka DEFEA) and was able to do some testing. Here are initial updates to the driver that address problems I encountered so far. More to come later on as I get back to the system that I have in a remote location -- I need to double-check MMIO support and see what might have been causing spurious interrupts I saw with the 8259A PIC the board's interrupt line has been routed to. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
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18c565eb41
@ -466,7 +466,8 @@ static void dfx_get_bars(struct device *bdev,
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*bar_len = (bar | PI_MEM_ADD_MASK_M) + 1;
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} else {
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*bar_start = base_addr;
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*bar_len = PI_ESIC_K_CSR_IO_LEN;
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*bar_len = PI_ESIC_K_CSR_IO_LEN +
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PI_ESIC_K_BURST_HOLDOFF_LEN;
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}
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}
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if (dfx_bus_tc) {
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@ -683,6 +684,9 @@ static void dfx_bus_init(struct net_device *dev)
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if (dfx_bus_eisa) {
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unsigned long base_addr = to_eisa_device(bdev)->base_addr;
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/* Disable the board before fiddling with the decoders. */
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outb(0, base_addr + PI_ESIC_K_SLOT_CNTRL);
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/* Get the interrupt level from the ESIC chip. */
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val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
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val &= PI_CONFIG_STAT_0_M_IRQ;
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@ -709,38 +713,46 @@ static void dfx_bus_init(struct net_device *dev)
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/*
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* Enable memory decoding (MEMCS0) and/or port decoding
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* (IOCS1/IOCS0) as appropriate in Function Control
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* Register. One of the port chip selects seems to be
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* used for the Burst Holdoff register, but this bit of
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* documentation is missing and as yet it has not been
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* determined which of the two. This is also the reason
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* the size of the decoded port range is twice as large
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* as one required by the PDQ.
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* Register. IOCS0 is used for PDQ registers, taking 16
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* 32-bit words, while IOCS1 is used for the Burst Holdoff
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* register, taking a single 32-bit word only. We use the
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* slot-specific I/O range as per the ESIC spec, that is
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* set bits 15:12 in the mask registers to mask them out.
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*/
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/* Set the decode range of the board. */
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val = ((bp->base.port >> 12) << PI_IO_CMP_V_SLOT);
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outb(base_addr + PI_ESIC_K_IO_ADD_CMP_0_1, val);
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outb(base_addr + PI_ESIC_K_IO_ADD_CMP_0_0, 0);
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outb(base_addr + PI_ESIC_K_IO_ADD_CMP_1_1, val);
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outb(base_addr + PI_ESIC_K_IO_ADD_CMP_1_0, 0);
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val = PI_ESIC_K_CSR_IO_LEN - 1;
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outb(base_addr + PI_ESIC_K_IO_ADD_MASK_0_1, (val >> 8) & 0xff);
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outb(base_addr + PI_ESIC_K_IO_ADD_MASK_0_0, val & 0xff);
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outb(base_addr + PI_ESIC_K_IO_ADD_MASK_1_1, (val >> 8) & 0xff);
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outb(base_addr + PI_ESIC_K_IO_ADD_MASK_1_0, val & 0xff);
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val = 0;
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outb(val, base_addr + PI_ESIC_K_IO_ADD_CMP_0_1);
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val = PI_DEFEA_K_CSR_IO;
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outb(val, base_addr + PI_ESIC_K_IO_ADD_CMP_0_0);
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val = PI_IO_CMP_M_SLOT;
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outb(val, base_addr + PI_ESIC_K_IO_ADD_MASK_0_1);
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val = (PI_ESIC_K_CSR_IO_LEN - 1) & ~3;
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outb(val, base_addr + PI_ESIC_K_IO_ADD_MASK_0_0);
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val = 0;
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outb(val, base_addr + PI_ESIC_K_IO_ADD_CMP_1_1);
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val = PI_DEFEA_K_BURST_HOLDOFF;
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outb(val, base_addr + PI_ESIC_K_IO_ADD_CMP_1_0);
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val = PI_IO_CMP_M_SLOT;
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outb(val, base_addr + PI_ESIC_K_IO_ADD_MASK_1_1);
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val = (PI_ESIC_K_BURST_HOLDOFF_LEN - 1) & ~3;
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outb(val, base_addr + PI_ESIC_K_IO_ADD_MASK_1_0);
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/* Enable the decoders. */
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val = PI_FUNCTION_CNTRL_M_IOCS1 | PI_FUNCTION_CNTRL_M_IOCS0;
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if (dfx_use_mmio)
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val |= PI_FUNCTION_CNTRL_M_MEMCS0;
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outb(base_addr + PI_ESIC_K_FUNCTION_CNTRL, val);
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outb(val, base_addr + PI_ESIC_K_FUNCTION_CNTRL);
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/*
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* Enable access to the rest of the module
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* (including PDQ and packet memory).
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*/
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val = PI_SLOT_CNTRL_M_ENB;
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outb(base_addr + PI_ESIC_K_SLOT_CNTRL, val);
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outb(val, base_addr + PI_ESIC_K_SLOT_CNTRL);
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/*
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* Map PDQ registers into memory or port space. This is
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@ -748,15 +760,15 @@ static void dfx_bus_init(struct net_device *dev)
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*/
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val = inb(base_addr + PI_DEFEA_K_BURST_HOLDOFF);
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if (dfx_use_mmio)
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val |= PI_BURST_HOLDOFF_V_MEM_MAP;
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val |= PI_BURST_HOLDOFF_M_MEM_MAP;
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else
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val &= ~PI_BURST_HOLDOFF_V_MEM_MAP;
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outb(base_addr + PI_DEFEA_K_BURST_HOLDOFF, val);
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val &= ~PI_BURST_HOLDOFF_M_MEM_MAP;
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outb(val, base_addr + PI_DEFEA_K_BURST_HOLDOFF);
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/* Enable interrupts at EISA bus interface chip (ESIC) */
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val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
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val |= PI_CONFIG_STAT_0_M_INT_ENB;
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outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, val);
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outb(val, base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
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}
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if (dfx_bus_pci) {
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struct pci_dev *pdev = to_pci_dev(bdev);
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@ -825,7 +837,7 @@ static void dfx_bus_uninit(struct net_device *dev)
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/* Disable interrupts at EISA bus interface chip (ESIC) */
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val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
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val &= ~PI_CONFIG_STAT_0_M_INT_ENB;
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outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, val);
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outb(val, base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
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}
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if (dfx_bus_pci) {
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/* Disable interrupts at PCI bus interface chip (PFI) */
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@ -1917,7 +1929,7 @@ static irqreturn_t dfx_interrupt(int irq, void *dev_id)
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/* Disable interrupts at the ESIC */
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status &= ~PI_CONFIG_STAT_0_M_INT_ENB;
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outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, status);
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outb(status, base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
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/* Call interrupt service routine for this adapter */
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dfx_int_common(dev);
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@ -1925,7 +1937,7 @@ static irqreturn_t dfx_interrupt(int irq, void *dev_id)
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/* Reenable interrupts at the ESIC */
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status = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
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status |= PI_CONFIG_STAT_0_M_INT_ENB;
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outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, status);
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outb(status, base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
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spin_unlock(&bp->lock);
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}
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@ -1479,8 +1479,10 @@ typedef union
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/* Define EISA controller register offsets */
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#define PI_ESIC_K_CSR_IO_LEN 0x80 /* 128 bytes */
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#define PI_ESIC_K_CSR_IO_LEN 0x40 /* 64 bytes */
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#define PI_ESIC_K_BURST_HOLDOFF_LEN 0x04 /* 4 bytes */
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#define PI_DEFEA_K_CSR_IO 0x000
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#define PI_DEFEA_K_BURST_HOLDOFF 0x040
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#define PI_ESIC_K_SLOT_ID 0xC80
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@ -1558,11 +1560,9 @@ typedef union
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#define PI_MEM_ADD_MASK_M 0x3ff
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/*
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* Define the fields in the IO Compare registers.
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* The driver must initialize the slot field with the slot ID shifted by the
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* amount shown below.
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*/
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/* Define the fields in the I/O Address Compare and Mask registers. */
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#define PI_IO_CMP_M_SLOT 0xf0
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#define PI_IO_CMP_V_SLOT 4
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