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IB/qib: Fix interrupt mitigation
For SusieQ we need to write to the interrupt timer register before updating the header queue head with interrupt count. This is to ensure that the timer is enabled properly and a receive available interrupt is delivered. Otherwise this interrupt can be lost if the receiver header/eager queues are full before the timer is enabled. Signed-off-by: Mike Marciniszyn <mike.marciniszyn@qlogic.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
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aa7374ac19
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@ -766,7 +766,7 @@ struct qib_devdata {
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void (*f_sdma_hw_start_up)(struct qib_pportdata *);
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void (*f_sdma_hw_start_up)(struct qib_pportdata *);
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void (*f_sdma_init_early)(struct qib_pportdata *);
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void (*f_sdma_init_early)(struct qib_pportdata *);
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void (*f_set_cntr_sample)(struct qib_pportdata *, u32, u32);
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void (*f_set_cntr_sample)(struct qib_pportdata *, u32, u32);
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void (*f_update_usrhead)(struct qib_ctxtdata *, u64, u32, u32);
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void (*f_update_usrhead)(struct qib_ctxtdata *, u64, u32, u32, u32);
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u32 (*f_hdrqempty)(struct qib_ctxtdata *);
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u32 (*f_hdrqempty)(struct qib_ctxtdata *);
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u64 (*f_portcntr)(struct qib_pportdata *, u32);
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u64 (*f_portcntr)(struct qib_pportdata *, u32);
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u32 (*f_read_cntrs)(struct qib_devdata *, loff_t, char **,
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u32 (*f_read_cntrs)(struct qib_devdata *, loff_t, char **,
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@ -410,7 +410,7 @@ move_along:
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*/
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*/
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lval = l;
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lval = l;
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if (!last && !(i & 0xf)) {
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if (!last && !(i & 0xf)) {
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dd->f_update_usrhead(rcd, lval, updegr, etail);
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dd->f_update_usrhead(rcd, lval, updegr, etail, i);
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updegr = 0;
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updegr = 0;
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}
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}
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}
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}
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@ -452,7 +452,7 @@ bail:
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* if no packets were processed.
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* if no packets were processed.
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*/
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*/
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lval = (u64)rcd->head | dd->rhdrhead_intr_off;
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lval = (u64)rcd->head | dd->rhdrhead_intr_off;
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dd->f_update_usrhead(rcd, lval, updegr, etail);
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dd->f_update_usrhead(rcd, lval, updegr, etail, i);
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return crcs;
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return crcs;
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}
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}
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@ -2074,7 +2074,7 @@ static void qib_6120_config_ctxts(struct qib_devdata *dd)
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}
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}
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static void qib_update_6120_usrhead(struct qib_ctxtdata *rcd, u64 hd,
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static void qib_update_6120_usrhead(struct qib_ctxtdata *rcd, u64 hd,
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u32 updegr, u32 egrhd)
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u32 updegr, u32 egrhd, u32 npkts)
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{
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{
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qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
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qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
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if (updegr)
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if (updegr)
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@ -2703,7 +2703,7 @@ static int qib_7220_set_loopback(struct qib_pportdata *ppd, const char *what)
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}
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}
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static void qib_update_7220_usrhead(struct qib_ctxtdata *rcd, u64 hd,
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static void qib_update_7220_usrhead(struct qib_ctxtdata *rcd, u64 hd,
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u32 updegr, u32 egrhd)
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u32 updegr, u32 egrhd, u32 npkts)
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{
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{
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qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
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qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
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if (updegr)
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if (updegr)
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@ -2823,7 +2823,6 @@ static irqreturn_t qib_7322intr(int irq, void *data)
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ctxtrbits &= ~rmask;
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ctxtrbits &= ~rmask;
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if (dd->rcd[i]) {
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if (dd->rcd[i]) {
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qib_kreceive(dd->rcd[i], NULL, &npkts);
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qib_kreceive(dd->rcd[i], NULL, &npkts);
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adjust_rcv_timeout(dd->rcd[i], npkts);
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}
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}
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}
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}
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rmask <<= 1;
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rmask <<= 1;
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@ -2873,7 +2872,6 @@ static irqreturn_t qib_7322pintr(int irq, void *data)
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(1ULL << QIB_I_RCVURG_LSB)) << rcd->ctxt);
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(1ULL << QIB_I_RCVURG_LSB)) << rcd->ctxt);
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qib_kreceive(rcd, NULL, &npkts);
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qib_kreceive(rcd, NULL, &npkts);
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adjust_rcv_timeout(rcd, npkts);
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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}
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}
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@ -4047,8 +4045,14 @@ static int qib_7322_set_ib_table(struct qib_pportdata *ppd, int which, void *t)
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}
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}
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static void qib_update_7322_usrhead(struct qib_ctxtdata *rcd, u64 hd,
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static void qib_update_7322_usrhead(struct qib_ctxtdata *rcd, u64 hd,
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u32 updegr, u32 egrhd)
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u32 updegr, u32 egrhd, u32 npkts)
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{
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{
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/*
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* Need to write timeout register before updating rcvhdrhead to ensure
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* that the timer is enabled on reception of a packet.
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*/
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if (hd >> IBA7322_HDRHEAD_PKTINT_SHIFT)
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adjust_rcv_timeout(rcd, npkts);
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qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
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qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
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qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
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qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
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if (updegr)
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if (updegr)
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