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mtd: mediatek: driver for MTK Smart Device
Add support for mediatek's SDG1 NFC nand controller embedded in SoC 2701 Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Tested-by: Xiaolei Li <xiaolei.li@mediatek.com>
This commit is contained in:
Jorge Ramirez-Ortiz
Boris Brezillon
parent
cac4fcc0d3
commit
1d6b1e4649
@ -563,4 +563,11 @@ config MTD_NAND_QCOM
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Enables support for NAND flash chips on SoCs containing the EBI2 NAND
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controller. This controller is found on IPQ806x SoC.
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config MTD_NAND_MTK
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tristate "Support for NAND controller on MTK SoCs"
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depends on HAS_DMA
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help
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Enables support for NAND controller on MTK SoCs.
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This controller is found on mt27xx, mt81xx, mt65xx SoCs.
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endif # MTD_NAND
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@ -57,5 +57,6 @@ obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o
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obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o
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obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
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obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
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obj-$(CONFIG_MTD_NAND_MTK) += mtk_nand.o mtk_ecc.o
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nand-objs := nand_base.o nand_bbt.o nand_timings.o
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530
drivers/mtd/nand/mtk_ecc.c
Normal file
530
drivers/mtd/nand/mtk_ecc.c
Normal file
@ -0,0 +1,530 @@
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/*
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* MTK ECC controller driver.
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* Copyright (C) 2016 MediaTek Inc.
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* Authors: Xiaolei Li <xiaolei.li@mediatek.com>
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* Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/iopoll.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/mutex.h>
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#include "mtk_ecc.h"
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#define ECC_IDLE_MASK BIT(0)
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#define ECC_IRQ_EN BIT(0)
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#define ECC_OP_ENABLE (1)
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#define ECC_OP_DISABLE (0)
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#define ECC_ENCCON (0x00)
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#define ECC_ENCCNFG (0x04)
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#define ECC_CNFG_4BIT (0)
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#define ECC_CNFG_6BIT (1)
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#define ECC_CNFG_8BIT (2)
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#define ECC_CNFG_10BIT (3)
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#define ECC_CNFG_12BIT (4)
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#define ECC_CNFG_14BIT (5)
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#define ECC_CNFG_16BIT (6)
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#define ECC_CNFG_18BIT (7)
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#define ECC_CNFG_20BIT (8)
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#define ECC_CNFG_22BIT (9)
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#define ECC_CNFG_24BIT (0xa)
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#define ECC_CNFG_28BIT (0xb)
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#define ECC_CNFG_32BIT (0xc)
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#define ECC_CNFG_36BIT (0xd)
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#define ECC_CNFG_40BIT (0xe)
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#define ECC_CNFG_44BIT (0xf)
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#define ECC_CNFG_48BIT (0x10)
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#define ECC_CNFG_52BIT (0x11)
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#define ECC_CNFG_56BIT (0x12)
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#define ECC_CNFG_60BIT (0x13)
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#define ECC_MODE_SHIFT (5)
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#define ECC_MS_SHIFT (16)
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#define ECC_ENCDIADDR (0x08)
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#define ECC_ENCIDLE (0x0C)
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#define ECC_ENCPAR(x) (0x10 + (x) * sizeof(u32))
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#define ECC_ENCIRQ_EN (0x80)
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#define ECC_ENCIRQ_STA (0x84)
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#define ECC_DECCON (0x100)
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#define ECC_DECCNFG (0x104)
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#define DEC_EMPTY_EN BIT(31)
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#define DEC_CNFG_CORRECT (0x3 << 12)
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#define ECC_DECIDLE (0x10C)
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#define ECC_DECENUM0 (0x114)
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#define ERR_MASK (0x3f)
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#define ECC_DECDONE (0x124)
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#define ECC_DECIRQ_EN (0x200)
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#define ECC_DECIRQ_STA (0x204)
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#define ECC_TIMEOUT (500000)
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#define ECC_IDLE_REG(op) ((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE)
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#define ECC_CTL_REG(op) ((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON)
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#define ECC_IRQ_REG(op) ((op) == ECC_ENCODE ? \
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ECC_ENCIRQ_EN : ECC_DECIRQ_EN)
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struct mtk_ecc {
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struct device *dev;
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void __iomem *regs;
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struct clk *clk;
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struct completion done;
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struct mutex lock;
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u32 sectors;
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};
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static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
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enum mtk_ecc_operation op)
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{
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struct device *dev = ecc->dev;
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u32 val;
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int ret;
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ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val,
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val & ECC_IDLE_MASK,
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10, ECC_TIMEOUT);
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if (ret)
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dev_warn(dev, "%s NOT idle\n",
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op == ECC_ENCODE ? "encoder" : "decoder");
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}
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static irqreturn_t mtk_ecc_irq(int irq, void *id)
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{
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struct mtk_ecc *ecc = id;
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enum mtk_ecc_operation op;
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u32 dec, enc;
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dec = readw(ecc->regs + ECC_DECIRQ_STA) & ECC_IRQ_EN;
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if (dec) {
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op = ECC_DECODE;
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dec = readw(ecc->regs + ECC_DECDONE);
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if (dec & ecc->sectors) {
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ecc->sectors = 0;
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complete(&ecc->done);
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} else {
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return IRQ_HANDLED;
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}
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} else {
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enc = readl(ecc->regs + ECC_ENCIRQ_STA) & ECC_IRQ_EN;
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if (enc) {
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op = ECC_ENCODE;
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complete(&ecc->done);
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} else {
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return IRQ_NONE;
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}
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}
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writel(0, ecc->regs + ECC_IRQ_REG(op));
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return IRQ_HANDLED;
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}
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static void mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
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{
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u32 ecc_bit = ECC_CNFG_4BIT, dec_sz, enc_sz;
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u32 reg;
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switch (config->strength) {
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case 4:
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ecc_bit = ECC_CNFG_4BIT;
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break;
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case 6:
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ecc_bit = ECC_CNFG_6BIT;
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break;
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case 8:
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ecc_bit = ECC_CNFG_8BIT;
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break;
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case 10:
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ecc_bit = ECC_CNFG_10BIT;
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break;
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case 12:
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ecc_bit = ECC_CNFG_12BIT;
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break;
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case 14:
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ecc_bit = ECC_CNFG_14BIT;
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break;
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case 16:
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ecc_bit = ECC_CNFG_16BIT;
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break;
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case 18:
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ecc_bit = ECC_CNFG_18BIT;
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break;
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case 20:
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ecc_bit = ECC_CNFG_20BIT;
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break;
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case 22:
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ecc_bit = ECC_CNFG_22BIT;
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break;
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case 24:
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ecc_bit = ECC_CNFG_24BIT;
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break;
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case 28:
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ecc_bit = ECC_CNFG_28BIT;
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break;
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case 32:
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ecc_bit = ECC_CNFG_32BIT;
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break;
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case 36:
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ecc_bit = ECC_CNFG_36BIT;
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break;
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case 40:
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ecc_bit = ECC_CNFG_40BIT;
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break;
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case 44:
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ecc_bit = ECC_CNFG_44BIT;
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break;
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case 48:
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ecc_bit = ECC_CNFG_48BIT;
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break;
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case 52:
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ecc_bit = ECC_CNFG_52BIT;
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break;
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case 56:
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ecc_bit = ECC_CNFG_56BIT;
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break;
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case 60:
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ecc_bit = ECC_CNFG_60BIT;
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break;
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default:
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dev_err(ecc->dev, "invalid strength %d, default to 4 bits\n",
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config->strength);
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}
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if (config->op == ECC_ENCODE) {
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/* configure ECC encoder (in bits) */
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enc_sz = config->len << 3;
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reg = ecc_bit | (config->mode << ECC_MODE_SHIFT);
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reg |= (enc_sz << ECC_MS_SHIFT);
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writel(reg, ecc->regs + ECC_ENCCNFG);
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if (config->mode != ECC_NFI_MODE)
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writel(lower_32_bits(config->addr),
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ecc->regs + ECC_ENCDIADDR);
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} else {
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/* configure ECC decoder (in bits) */
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dec_sz = (config->len << 3) +
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config->strength * ECC_PARITY_BITS;
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reg = ecc_bit | (config->mode << ECC_MODE_SHIFT);
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reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT;
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reg |= DEC_EMPTY_EN;
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writel(reg, ecc->regs + ECC_DECCNFG);
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if (config->sectors)
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ecc->sectors = 1 << (config->sectors - 1);
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}
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}
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void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats,
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int sectors)
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{
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u32 offset, i, err;
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u32 bitflips = 0;
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stats->corrected = 0;
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stats->failed = 0;
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for (i = 0; i < sectors; i++) {
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offset = (i >> 2) << 2;
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err = readl(ecc->regs + ECC_DECENUM0 + offset);
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err = err >> ((i % 4) * 8);
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err &= ERR_MASK;
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if (err == ERR_MASK) {
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/* uncorrectable errors */
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stats->failed++;
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continue;
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}
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stats->corrected += err;
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bitflips = max_t(u32, bitflips, err);
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}
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stats->bitflips = bitflips;
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}
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EXPORT_SYMBOL(mtk_ecc_get_stats);
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void mtk_ecc_release(struct mtk_ecc *ecc)
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{
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clk_disable_unprepare(ecc->clk);
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put_device(ecc->dev);
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}
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EXPORT_SYMBOL(mtk_ecc_release);
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static void mtk_ecc_hw_init(struct mtk_ecc *ecc)
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{
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mtk_ecc_wait_idle(ecc, ECC_ENCODE);
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writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON);
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mtk_ecc_wait_idle(ecc, ECC_DECODE);
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writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON);
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}
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static struct mtk_ecc *mtk_ecc_get(struct device_node *np)
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{
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struct platform_device *pdev;
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struct mtk_ecc *ecc;
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pdev = of_find_device_by_node(np);
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if (!pdev || !platform_get_drvdata(pdev))
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return ERR_PTR(-EPROBE_DEFER);
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get_device(&pdev->dev);
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ecc = platform_get_drvdata(pdev);
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clk_prepare_enable(ecc->clk);
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mtk_ecc_hw_init(ecc);
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return ecc;
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}
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struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node)
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{
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struct mtk_ecc *ecc = NULL;
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struct device_node *np;
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np = of_parse_phandle(of_node, "ecc-engine", 0);
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if (np) {
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ecc = mtk_ecc_get(np);
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of_node_put(np);
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}
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return ecc;
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}
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EXPORT_SYMBOL(of_mtk_ecc_get);
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int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
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{
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enum mtk_ecc_operation op = config->op;
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int ret;
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ret = mutex_lock_interruptible(&ecc->lock);
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if (ret) {
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dev_err(ecc->dev, "interrupted when attempting to lock\n");
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return ret;
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}
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mtk_ecc_wait_idle(ecc, op);
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mtk_ecc_config(ecc, config);
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writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));
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init_completion(&ecc->done);
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writew(ECC_IRQ_EN, ecc->regs + ECC_IRQ_REG(op));
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return 0;
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}
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EXPORT_SYMBOL(mtk_ecc_enable);
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void mtk_ecc_disable(struct mtk_ecc *ecc)
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{
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enum mtk_ecc_operation op = ECC_ENCODE;
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/* find out the running operation */
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if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE)
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op = ECC_DECODE;
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/* disable it */
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mtk_ecc_wait_idle(ecc, op);
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writew(0, ecc->regs + ECC_IRQ_REG(op));
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writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op));
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mutex_unlock(&ecc->lock);
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}
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EXPORT_SYMBOL(mtk_ecc_disable);
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int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op)
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{
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int ret;
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ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500));
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if (!ret) {
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dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n",
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(op == ECC_ENCODE) ? "encoder" : "decoder");
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return -ETIMEDOUT;
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}
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return 0;
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}
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EXPORT_SYMBOL(mtk_ecc_wait_done);
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int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config,
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u8 *data, u32 bytes)
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{
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dma_addr_t addr;
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u32 *p, len, i;
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int ret = 0;
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addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE);
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ret = dma_mapping_error(ecc->dev, addr);
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if (ret) {
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dev_err(ecc->dev, "dma mapping error\n");
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return -EINVAL;
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}
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config->op = ECC_ENCODE;
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config->addr = addr;
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ret = mtk_ecc_enable(ecc, config);
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if (ret) {
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dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
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return ret;
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}
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ret = mtk_ecc_wait_done(ecc, ECC_ENCODE);
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if (ret)
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goto timeout;
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mtk_ecc_wait_idle(ecc, ECC_ENCODE);
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/* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */
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len = (config->strength * ECC_PARITY_BITS + 7) >> 3;
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p = (u32 *)(data + bytes);
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/* write the parity bytes generated by the ECC back to the OOB region */
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for (i = 0; i < len; i++)
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p[i] = readl(ecc->regs + ECC_ENCPAR(i));
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timeout:
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dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
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mtk_ecc_disable(ecc);
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return ret;
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}
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EXPORT_SYMBOL(mtk_ecc_encode);
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void mtk_ecc_adjust_strength(u32 *p)
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{
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u32 ecc[] = {4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
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40, 44, 48, 52, 56, 60};
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int i;
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for (i = 0; i < ARRAY_SIZE(ecc); i++) {
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if (*p <= ecc[i]) {
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if (!i)
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*p = ecc[i];
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else if (*p != ecc[i])
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*p = ecc[i - 1];
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return;
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}
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}
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*p = ecc[ARRAY_SIZE(ecc) - 1];
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}
|
||||
EXPORT_SYMBOL(mtk_ecc_adjust_strength);
|
||||
|
||||
static int mtk_ecc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct mtk_ecc *ecc;
|
||||
struct resource *res;
|
||||
int irq, ret;
|
||||
|
||||
ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
|
||||
if (!ecc)
|
||||
return -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
ecc->regs = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(ecc->regs)) {
|
||||
dev_err(dev, "failed to map regs: %ld\n", PTR_ERR(ecc->regs));
|
||||
return PTR_ERR(ecc->regs);
|
||||
}
|
||||
|
||||
ecc->clk = devm_clk_get(dev, NULL);
|
||||
if (IS_ERR(ecc->clk)) {
|
||||
dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk));
|
||||
return PTR_ERR(ecc->clk);
|
||||
}
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
dev_err(dev, "failed to get irq\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = dma_set_mask(dev, DMA_BIT_MASK(32));
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to set DMA mask\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to request irq\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ecc->dev = dev;
|
||||
mutex_init(&ecc->lock);
|
||||
platform_set_drvdata(pdev, ecc);
|
||||
dev_info(dev, "probed\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int mtk_ecc_suspend(struct device *dev)
|
||||
{
|
||||
struct mtk_ecc *ecc = dev_get_drvdata(dev);
|
||||
|
||||
clk_disable_unprepare(ecc->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_ecc_resume(struct device *dev)
|
||||
{
|
||||
struct mtk_ecc *ecc = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(ecc->clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to enable clk\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
mtk_ecc_hw_init(ecc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume);
|
||||
#endif
|
||||
|
||||
static const struct of_device_id mtk_ecc_dt_match[] = {
|
||||
{ .compatible = "mediatek,mt2701-ecc" },
|
||||
{},
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match);
|
||||
|
||||
static struct platform_driver mtk_ecc_driver = {
|
||||
.probe = mtk_ecc_probe,
|
||||
.driver = {
|
||||
.name = "mtk-ecc",
|
||||
.of_match_table = of_match_ptr(mtk_ecc_dt_match),
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
.pm = &mtk_ecc_pm_ops,
|
||||
#endif
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(mtk_ecc_driver);
|
||||
|
||||
MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>");
|
||||
MODULE_DESCRIPTION("MTK Nand ECC Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
50
drivers/mtd/nand/mtk_ecc.h
Normal file
50
drivers/mtd/nand/mtk_ecc.h
Normal file
@ -0,0 +1,50 @@
|
||||
/*
|
||||
* MTK SDG1 ECC controller
|
||||
*
|
||||
* Copyright (c) 2016 Mediatek
|
||||
* Authors: Xiaolei Li <xiaolei.li@mediatek.com>
|
||||
* Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__
|
||||
#define __DRIVERS_MTD_NAND_MTK_ECC_H__
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
#define ECC_PARITY_BITS (14)
|
||||
|
||||
enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1};
|
||||
enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE};
|
||||
|
||||
struct device_node;
|
||||
struct mtk_ecc;
|
||||
|
||||
struct mtk_ecc_stats {
|
||||
u32 corrected;
|
||||
u32 bitflips;
|
||||
u32 failed;
|
||||
};
|
||||
|
||||
struct mtk_ecc_config {
|
||||
enum mtk_ecc_operation op;
|
||||
enum mtk_ecc_mode mode;
|
||||
dma_addr_t addr;
|
||||
u32 strength;
|
||||
u32 sectors;
|
||||
u32 len;
|
||||
};
|
||||
|
||||
int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32);
|
||||
void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int);
|
||||
int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation);
|
||||
int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *);
|
||||
void mtk_ecc_disable(struct mtk_ecc *);
|
||||
void mtk_ecc_adjust_strength(u32 *);
|
||||
|
||||
struct mtk_ecc *of_mtk_ecc_get(struct device_node *);
|
||||
void mtk_ecc_release(struct mtk_ecc *);
|
||||
|
||||
#endif
|
||||
1526
drivers/mtd/nand/mtk_nand.c
Normal file
1526
drivers/mtd/nand/mtk_nand.c
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user