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serial/mpc52xx_uart: add MPC5125 PSC support
Add MPC5125 PSC register layout structure, MPC5125 specific psc_ops function set and the compatible string. Signed-off-by: Vladimir Ermakov <vooon341@gmail.com> Signed-off-by: Matteo Facchinetti <matteo.facchinetti@sirius-es.it> Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Matteo Facchinetti
Greg Kroah-Hartman
parent
2574b27eee
commit
1f48c499df
@ -299,4 +299,53 @@ struct mpc512x_psc_fifo {
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#define rxdata_32 rxdata.rxdata_32
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};
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struct mpc5125_psc {
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u8 mr1; /* PSC + 0x00 */
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u8 reserved0[3];
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u8 mr2; /* PSC + 0x04 */
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u8 reserved1[3];
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struct {
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u16 status; /* PSC + 0x08 */
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u8 reserved2[2];
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u8 clock_select; /* PSC + 0x0c */
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u8 reserved3[3];
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} sr_csr;
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u8 command; /* PSC + 0x10 */
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u8 reserved4[3];
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union { /* PSC + 0x14 */
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u8 buffer_8;
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u16 buffer_16;
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u32 buffer_32;
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} buffer;
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struct {
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u8 ipcr; /* PSC + 0x18 */
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u8 reserved5[3];
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u8 acr; /* PSC + 0x1c */
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u8 reserved6[3];
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} ipcr_acr;
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struct {
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u16 isr; /* PSC + 0x20 */
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u8 reserved7[2];
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u16 imr; /* PSC + 0x24 */
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u8 reserved8[2];
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} isr_imr;
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u8 ctur; /* PSC + 0x28 */
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u8 reserved9[3];
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u8 ctlr; /* PSC + 0x2c */
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u8 reserved10[3];
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u32 ccr; /* PSC + 0x30 */
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u32 ac97slots; /* PSC + 0x34 */
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u32 ac97cmd; /* PSC + 0x38 */
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u32 ac97data; /* PSC + 0x3c */
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u8 reserved11[4];
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u8 ip; /* PSC + 0x44 */
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u8 reserved12[3];
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u8 op1; /* PSC + 0x48 */
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u8 reserved13[3];
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u8 op0; /* PSC + 0x4c */
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u8 reserved14[3];
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u32 sicr; /* PSC + 0x50 */
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u8 reserved15[4]; /* make eq. sizeof(mpc52xx_psc) */
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};
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#endif /* __ASM_MPC52xx_PSC_H__ */
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@ -648,6 +648,246 @@ static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np)
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port->irqflags = IRQF_SHARED;
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port->irq = psc_fifoc_irq;
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}
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#endif
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#ifdef CONFIG_PPC_MPC512x
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#define PSC_5125(port) ((struct mpc5125_psc __iomem *)((port)->membase))
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#define FIFO_5125(port) ((struct mpc512x_psc_fifo __iomem *)(PSC_5125(port)+1))
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static void mpc5125_psc_fifo_init(struct uart_port *port)
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{
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/* /32 prescaler */
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out_8(&PSC_5125(port)->mpc52xx_psc_clock_select, 0xdd);
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out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
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out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
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out_be32(&FIFO_5125(port)->txalarm, 1);
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out_be32(&FIFO_5125(port)->tximr, 0);
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out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
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out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
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out_be32(&FIFO_5125(port)->rxalarm, 1);
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out_be32(&FIFO_5125(port)->rximr, 0);
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out_be32(&FIFO_5125(port)->tximr, MPC512x_PSC_FIFO_ALARM);
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out_be32(&FIFO_5125(port)->rximr, MPC512x_PSC_FIFO_ALARM);
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}
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static int mpc5125_psc_raw_rx_rdy(struct uart_port *port)
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{
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return !(in_be32(&FIFO_5125(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
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}
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static int mpc5125_psc_raw_tx_rdy(struct uart_port *port)
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{
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return !(in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_FULL);
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}
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static int mpc5125_psc_rx_rdy(struct uart_port *port)
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{
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return in_be32(&FIFO_5125(port)->rxsr) &
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in_be32(&FIFO_5125(port)->rximr) & MPC512x_PSC_FIFO_ALARM;
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}
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static int mpc5125_psc_tx_rdy(struct uart_port *port)
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{
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return in_be32(&FIFO_5125(port)->txsr) &
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in_be32(&FIFO_5125(port)->tximr) & MPC512x_PSC_FIFO_ALARM;
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}
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static int mpc5125_psc_tx_empty(struct uart_port *port)
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{
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return in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_EMPTY;
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}
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static void mpc5125_psc_stop_rx(struct uart_port *port)
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{
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unsigned long rx_fifo_imr;
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rx_fifo_imr = in_be32(&FIFO_5125(port)->rximr);
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rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
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out_be32(&FIFO_5125(port)->rximr, rx_fifo_imr);
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}
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static void mpc5125_psc_start_tx(struct uart_port *port)
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{
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unsigned long tx_fifo_imr;
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tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr);
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tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM;
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out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);
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}
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static void mpc5125_psc_stop_tx(struct uart_port *port)
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{
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unsigned long tx_fifo_imr;
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tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr);
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tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
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out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);
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}
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static void mpc5125_psc_rx_clr_irq(struct uart_port *port)
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{
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out_be32(&FIFO_5125(port)->rxisr, in_be32(&FIFO_5125(port)->rxisr));
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}
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static void mpc5125_psc_tx_clr_irq(struct uart_port *port)
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{
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out_be32(&FIFO_5125(port)->txisr, in_be32(&FIFO_5125(port)->txisr));
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}
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static void mpc5125_psc_write_char(struct uart_port *port, unsigned char c)
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{
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out_8(&FIFO_5125(port)->txdata_8, c);
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}
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static unsigned char mpc5125_psc_read_char(struct uart_port *port)
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{
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return in_8(&FIFO_5125(port)->rxdata_8);
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}
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static void mpc5125_psc_cw_disable_ints(struct uart_port *port)
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{
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port->read_status_mask =
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in_be32(&FIFO_5125(port)->tximr) << 16 |
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in_be32(&FIFO_5125(port)->rximr);
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out_be32(&FIFO_5125(port)->tximr, 0);
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out_be32(&FIFO_5125(port)->rximr, 0);
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}
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static void mpc5125_psc_cw_restore_ints(struct uart_port *port)
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{
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out_be32(&FIFO_5125(port)->tximr,
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(port->read_status_mask >> 16) & 0x7f);
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out_be32(&FIFO_5125(port)->rximr, port->read_status_mask & 0x7f);
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}
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static inline void mpc5125_set_divisor(struct mpc5125_psc __iomem *psc,
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u8 prescaler, unsigned int divisor)
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{
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/* select prescaler */
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out_8(&psc->mpc52xx_psc_clock_select, prescaler);
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out_8(&psc->ctur, divisor >> 8);
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out_8(&psc->ctlr, divisor & 0xff);
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}
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static unsigned int mpc5125_psc_set_baudrate(struct uart_port *port,
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struct ktermios *new,
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struct ktermios *old)
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{
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unsigned int baud;
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unsigned int divisor;
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/*
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* Calculate with a /16 prescaler here.
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*/
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/* uartclk contains the ips freq */
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baud = uart_get_baud_rate(port, new, old,
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port->uartclk / (16 * 0xffff) + 1,
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port->uartclk / 16);
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divisor = (port->uartclk + 8 * baud) / (16 * baud);
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/* enable the /16 prescaler and set the divisor */
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mpc5125_set_divisor(PSC_5125(port), 0xdd, divisor);
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return baud;
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}
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/*
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* MPC5125 have compatible PSC FIFO Controller.
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* Special init not needed.
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*/
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static u16 mpc5125_psc_get_status(struct uart_port *port)
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{
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return in_be16(&PSC_5125(port)->mpc52xx_psc_status);
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}
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static u8 mpc5125_psc_get_ipcr(struct uart_port *port)
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{
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return in_8(&PSC_5125(port)->mpc52xx_psc_ipcr);
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}
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static void mpc5125_psc_command(struct uart_port *port, u8 cmd)
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{
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out_8(&PSC_5125(port)->command, cmd);
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}
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static void mpc5125_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2)
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{
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out_8(&PSC_5125(port)->mr1, mr1);
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out_8(&PSC_5125(port)->mr2, mr2);
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}
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static void mpc5125_psc_set_rts(struct uart_port *port, int state)
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{
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if (state & TIOCM_RTS)
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out_8(&PSC_5125(port)->op1, MPC52xx_PSC_OP_RTS);
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else
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out_8(&PSC_5125(port)->op0, MPC52xx_PSC_OP_RTS);
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}
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static void mpc5125_psc_enable_ms(struct uart_port *port)
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{
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struct mpc5125_psc __iomem *psc = PSC_5125(port);
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/* clear D_*-bits by reading them */
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in_8(&psc->mpc52xx_psc_ipcr);
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/* enable CTS and DCD as IPC interrupts */
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out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
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port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
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out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
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}
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static void mpc5125_psc_set_sicr(struct uart_port *port, u32 val)
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{
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out_be32(&PSC_5125(port)->sicr, val);
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}
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static void mpc5125_psc_set_imr(struct uart_port *port, u16 val)
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{
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out_be16(&PSC_5125(port)->mpc52xx_psc_imr, val);
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}
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static u8 mpc5125_psc_get_mr1(struct uart_port *port)
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{
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return in_8(&PSC_5125(port)->mr1);
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}
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static struct psc_ops mpc5125_psc_ops = {
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.fifo_init = mpc5125_psc_fifo_init,
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.raw_rx_rdy = mpc5125_psc_raw_rx_rdy,
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.raw_tx_rdy = mpc5125_psc_raw_tx_rdy,
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.rx_rdy = mpc5125_psc_rx_rdy,
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.tx_rdy = mpc5125_psc_tx_rdy,
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.tx_empty = mpc5125_psc_tx_empty,
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.stop_rx = mpc5125_psc_stop_rx,
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.start_tx = mpc5125_psc_start_tx,
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.stop_tx = mpc5125_psc_stop_tx,
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.rx_clr_irq = mpc5125_psc_rx_clr_irq,
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.tx_clr_irq = mpc5125_psc_tx_clr_irq,
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.write_char = mpc5125_psc_write_char,
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.read_char = mpc5125_psc_read_char,
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.cw_disable_ints = mpc5125_psc_cw_disable_ints,
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.cw_restore_ints = mpc5125_psc_cw_restore_ints,
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.set_baudrate = mpc5125_psc_set_baudrate,
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.clock = mpc512x_psc_clock,
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.fifoc_init = mpc512x_psc_fifoc_init,
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.fifoc_uninit = mpc512x_psc_fifoc_uninit,
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.get_irq = mpc512x_psc_get_irq,
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.handle_irq = mpc512x_psc_handle_irq,
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.get_status = mpc5125_psc_get_status,
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.get_ipcr = mpc5125_psc_get_ipcr,
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.command = mpc5125_psc_command,
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.set_mode = mpc5125_psc_set_mode,
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.set_rts = mpc5125_psc_set_rts,
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.enable_ms = mpc5125_psc_enable_ms,
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.set_sicr = mpc5125_psc_set_sicr,
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.set_imr = mpc5125_psc_set_imr,
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.get_mr1 = mpc5125_psc_get_mr1,
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};
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static struct psc_ops mpc512x_psc_ops = {
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.fifo_init = mpc512x_psc_fifo_init,
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@ -1371,6 +1611,7 @@ static struct of_device_id mpc52xx_uart_of_match[] = {
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#endif
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#ifdef CONFIG_PPC_MPC512x
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{ .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, },
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{ .compatible = "fsl,mpc5125-psc-uart", .data = &mpc5125_psc_ops, },
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#endif
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{},
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};
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