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https://github.com/FEX-Emu/linux.git
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locking, x86, iommu: Annotate iommu->register_lock as raw
The iommu->register_lock can be taken in atomic context and therefore must not be preempted on -rt - annotate it. In mainline this change documents the low level nature of the lock - otherwise there's no functional difference. Lockdep and Sparse checking will work as usual. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Thomas Gleixner
Ingo Molnar
parent
289b4e7a48
commit
1f5b3c3fd2
@ -800,7 +800,7 @@ int alloc_iommu(struct dmar_drhd_unit *drhd)
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(unsigned long long)iommu->cap,
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(unsigned long long)iommu->ecap);
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spin_lock_init(&iommu->register_lock);
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raw_spin_lock_init(&iommu->register_lock);
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drhd->iommu = iommu;
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return 0;
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@ -1062,7 +1062,7 @@ void dmar_disable_qi(struct intel_iommu *iommu)
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if (!ecap_qis(iommu->ecap))
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return;
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spin_lock_irqsave(&iommu->register_lock, flags);
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raw_spin_lock_irqsave(&iommu->register_lock, flags);
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sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
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if (!(sts & DMA_GSTS_QIES))
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@ -1082,7 +1082,7 @@ void dmar_disable_qi(struct intel_iommu *iommu)
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl,
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!(sts & DMA_GSTS_QIES), sts);
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end:
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spin_unlock_irqrestore(&iommu->register_lock, flags);
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raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
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}
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/*
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@ -1097,7 +1097,7 @@ static void __dmar_enable_qi(struct intel_iommu *iommu)
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qi->free_head = qi->free_tail = 0;
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qi->free_cnt = QI_LENGTH;
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spin_lock_irqsave(&iommu->register_lock, flags);
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raw_spin_lock_irqsave(&iommu->register_lock, flags);
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/* write zero to the tail reg */
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writel(0, iommu->reg + DMAR_IQT_REG);
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@ -1110,7 +1110,7 @@ static void __dmar_enable_qi(struct intel_iommu *iommu)
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/* Make sure hardware complete it */
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts);
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spin_unlock_irqrestore(&iommu->register_lock, flags);
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raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
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}
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/*
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@ -1225,11 +1225,11 @@ void dmar_msi_unmask(struct irq_data *data)
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unsigned long flag;
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/* unmask it */
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spin_lock_irqsave(&iommu->register_lock, flag);
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raw_spin_lock_irqsave(&iommu->register_lock, flag);
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writel(0, iommu->reg + DMAR_FECTL_REG);
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/* Read a reg to force flush the post write */
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readl(iommu->reg + DMAR_FECTL_REG);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
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}
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void dmar_msi_mask(struct irq_data *data)
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@ -1238,11 +1238,11 @@ void dmar_msi_mask(struct irq_data *data)
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struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);
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/* mask it */
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spin_lock_irqsave(&iommu->register_lock, flag);
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raw_spin_lock_irqsave(&iommu->register_lock, flag);
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writel(DMA_FECTL_IM, iommu->reg + DMAR_FECTL_REG);
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/* Read a reg to force flush the post write */
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readl(iommu->reg + DMAR_FECTL_REG);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
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}
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void dmar_msi_write(int irq, struct msi_msg *msg)
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@ -1250,11 +1250,11 @@ void dmar_msi_write(int irq, struct msi_msg *msg)
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struct intel_iommu *iommu = irq_get_handler_data(irq);
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unsigned long flag;
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spin_lock_irqsave(&iommu->register_lock, flag);
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raw_spin_lock_irqsave(&iommu->register_lock, flag);
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writel(msg->data, iommu->reg + DMAR_FEDATA_REG);
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writel(msg->address_lo, iommu->reg + DMAR_FEADDR_REG);
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writel(msg->address_hi, iommu->reg + DMAR_FEUADDR_REG);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
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}
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void dmar_msi_read(int irq, struct msi_msg *msg)
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@ -1262,11 +1262,11 @@ void dmar_msi_read(int irq, struct msi_msg *msg)
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struct intel_iommu *iommu = irq_get_handler_data(irq);
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unsigned long flag;
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spin_lock_irqsave(&iommu->register_lock, flag);
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raw_spin_lock_irqsave(&iommu->register_lock, flag);
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msg->data = readl(iommu->reg + DMAR_FEDATA_REG);
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msg->address_lo = readl(iommu->reg + DMAR_FEADDR_REG);
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msg->address_hi = readl(iommu->reg + DMAR_FEUADDR_REG);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
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}
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static int dmar_fault_do_one(struct intel_iommu *iommu, int type,
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@ -1303,7 +1303,7 @@ irqreturn_t dmar_fault(int irq, void *dev_id)
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u32 fault_status;
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unsigned long flag;
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spin_lock_irqsave(&iommu->register_lock, flag);
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raw_spin_lock_irqsave(&iommu->register_lock, flag);
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fault_status = readl(iommu->reg + DMAR_FSTS_REG);
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if (fault_status)
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printk(KERN_ERR "DRHD: handling fault status reg %x\n",
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@ -1342,7 +1342,7 @@ irqreturn_t dmar_fault(int irq, void *dev_id)
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writel(DMA_FRCD_F, iommu->reg + reg +
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fault_index * PRIMARY_FAULT_REG_LEN + 12);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
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dmar_fault_do_one(iommu, type, fault_reason,
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source_id, guest_addr);
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@ -1350,14 +1350,14 @@ irqreturn_t dmar_fault(int irq, void *dev_id)
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fault_index++;
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if (fault_index >= cap_num_fault_regs(iommu->cap))
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fault_index = 0;
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spin_lock_irqsave(&iommu->register_lock, flag);
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raw_spin_lock_irqsave(&iommu->register_lock, flag);
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}
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clear_rest:
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/* clear all the other faults */
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fault_status = readl(iommu->reg + DMAR_FSTS_REG);
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writel(fault_status, iommu->reg + DMAR_FSTS_REG);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
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return IRQ_HANDLED;
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}
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@ -932,7 +932,7 @@ static void iommu_set_root_entry(struct intel_iommu *iommu)
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addr = iommu->root_entry;
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spin_lock_irqsave(&iommu->register_lock, flag);
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raw_spin_lock_irqsave(&iommu->register_lock, flag);
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dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
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writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
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@ -941,7 +941,7 @@ static void iommu_set_root_entry(struct intel_iommu *iommu)
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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readl, (sts & DMA_GSTS_RTPS), sts);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
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}
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static void iommu_flush_write_buffer(struct intel_iommu *iommu)
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@ -952,14 +952,14 @@ static void iommu_flush_write_buffer(struct intel_iommu *iommu)
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if (!rwbf_quirk && !cap_rwbf(iommu->cap))
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return;
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spin_lock_irqsave(&iommu->register_lock, flag);
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raw_spin_lock_irqsave(&iommu->register_lock, flag);
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writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
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/* Make sure hardware complete it */
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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readl, (!(val & DMA_GSTS_WBFS)), val);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
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}
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/* return value determine if we need a write buffer flush */
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@ -986,14 +986,14 @@ static void __iommu_flush_context(struct intel_iommu *iommu,
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}
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val |= DMA_CCMD_ICC;
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spin_lock_irqsave(&iommu->register_lock, flag);
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raw_spin_lock_irqsave(&iommu->register_lock, flag);
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dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
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/* Make sure hardware complete it */
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IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
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dmar_readq, (!(val & DMA_CCMD_ICC)), val);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
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}
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/* return value determine if we need a write buffer flush */
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@ -1032,7 +1032,7 @@ static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
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if (cap_write_drain(iommu->cap))
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val |= DMA_TLB_WRITE_DRAIN;
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spin_lock_irqsave(&iommu->register_lock, flag);
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raw_spin_lock_irqsave(&iommu->register_lock, flag);
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/* Note: Only uses first TLB reg currently */
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if (val_iva)
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dmar_writeq(iommu->reg + tlb_offset, val_iva);
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@ -1042,7 +1042,7 @@ static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
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IOMMU_WAIT_OP(iommu, tlb_offset + 8,
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dmar_readq, (!(val & DMA_TLB_IVT)), val);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
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/* check IOTLB invalidation granularity */
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if (DMA_TLB_IAIG(val) == 0)
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@ -1158,7 +1158,7 @@ static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
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u32 pmen;
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unsigned long flags;
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spin_lock_irqsave(&iommu->register_lock, flags);
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raw_spin_lock_irqsave(&iommu->register_lock, flags);
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pmen = readl(iommu->reg + DMAR_PMEN_REG);
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pmen &= ~DMA_PMEN_EPM;
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writel(pmen, iommu->reg + DMAR_PMEN_REG);
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@ -1167,7 +1167,7 @@ static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
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IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
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readl, !(pmen & DMA_PMEN_PRS), pmen);
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spin_unlock_irqrestore(&iommu->register_lock, flags);
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raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
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}
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static int iommu_enable_translation(struct intel_iommu *iommu)
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@ -1175,7 +1175,7 @@ static int iommu_enable_translation(struct intel_iommu *iommu)
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u32 sts;
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unsigned long flags;
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spin_lock_irqsave(&iommu->register_lock, flags);
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raw_spin_lock_irqsave(&iommu->register_lock, flags);
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iommu->gcmd |= DMA_GCMD_TE;
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writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
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@ -1183,7 +1183,7 @@ static int iommu_enable_translation(struct intel_iommu *iommu)
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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readl, (sts & DMA_GSTS_TES), sts);
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spin_unlock_irqrestore(&iommu->register_lock, flags);
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raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
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return 0;
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}
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@ -1192,7 +1192,7 @@ static int iommu_disable_translation(struct intel_iommu *iommu)
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u32 sts;
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unsigned long flag;
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spin_lock_irqsave(&iommu->register_lock, flag);
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raw_spin_lock_irqsave(&iommu->register_lock, flag);
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iommu->gcmd &= ~DMA_GCMD_TE;
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writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
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@ -1200,7 +1200,7 @@ static int iommu_disable_translation(struct intel_iommu *iommu)
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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readl, (!(sts & DMA_GSTS_TES)), sts);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
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return 0;
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}
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@ -3320,7 +3320,7 @@ static int iommu_suspend(void)
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for_each_active_iommu(iommu, drhd) {
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iommu_disable_translation(iommu);
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spin_lock_irqsave(&iommu->register_lock, flag);
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raw_spin_lock_irqsave(&iommu->register_lock, flag);
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iommu->iommu_state[SR_DMAR_FECTL_REG] =
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readl(iommu->reg + DMAR_FECTL_REG);
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@ -3331,7 +3331,7 @@ static int iommu_suspend(void)
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iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
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readl(iommu->reg + DMAR_FEUADDR_REG);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
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}
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return 0;
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@ -3358,7 +3358,7 @@ static void iommu_resume(void)
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for_each_active_iommu(iommu, drhd) {
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spin_lock_irqsave(&iommu->register_lock, flag);
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raw_spin_lock_irqsave(&iommu->register_lock, flag);
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writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
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iommu->reg + DMAR_FECTL_REG);
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@ -3369,7 +3369,7 @@ static void iommu_resume(void)
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writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
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iommu->reg + DMAR_FEUADDR_REG);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
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}
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for_each_active_iommu(iommu, drhd)
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@ -409,7 +409,7 @@ static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
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addr = virt_to_phys((void *)iommu->ir_table->base);
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spin_lock_irqsave(&iommu->register_lock, flags);
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raw_spin_lock_irqsave(&iommu->register_lock, flags);
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dmar_writeq(iommu->reg + DMAR_IRTA_REG,
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(addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
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@ -420,7 +420,7 @@ static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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readl, (sts & DMA_GSTS_IRTPS), sts);
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spin_unlock_irqrestore(&iommu->register_lock, flags);
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raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
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/*
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* global invalidation of interrupt entry cache before enabling
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@ -428,7 +428,7 @@ static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
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*/
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qi_global_iec(iommu);
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spin_lock_irqsave(&iommu->register_lock, flags);
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raw_spin_lock_irqsave(&iommu->register_lock, flags);
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/* Enable interrupt-remapping */
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iommu->gcmd |= DMA_GCMD_IRE;
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@ -437,7 +437,7 @@ static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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readl, (sts & DMA_GSTS_IRES), sts);
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spin_unlock_irqrestore(&iommu->register_lock, flags);
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raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
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}
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@ -485,7 +485,7 @@ static void iommu_disable_intr_remapping(struct intel_iommu *iommu)
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*/
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qi_global_iec(iommu);
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spin_lock_irqsave(&iommu->register_lock, flags);
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raw_spin_lock_irqsave(&iommu->register_lock, flags);
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sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
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if (!(sts & DMA_GSTS_IRES))
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@ -498,7 +498,7 @@ static void iommu_disable_intr_remapping(struct intel_iommu *iommu)
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readl, !(sts & DMA_GSTS_IRES), sts);
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end:
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spin_unlock_irqrestore(&iommu->register_lock, flags);
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raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
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}
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int __init intr_remapping_supported(void)
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@ -311,7 +311,7 @@ struct intel_iommu {
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u64 cap;
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u64 ecap;
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u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
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spinlock_t register_lock; /* protect register handling */
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raw_spinlock_t register_lock; /* protect register handling */
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int seq_id; /* sequence id of the iommu */
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int agaw; /* agaw of this iommu */
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int msagaw; /* max sagaw of this iommu */
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