mirror of
https://github.com/FEX-Emu/linux.git
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Merge branch 'next/drivers' into late/multiplatform
Multiple parts of next/drivers are prerequisites for the final exynos multiplatform changes, so let's pull in the entire branch. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
22cf644e03
56
Documentation/arm/sunxi/clocks.txt
Normal file
56
Documentation/arm/sunxi/clocks.txt
Normal file
@ -0,0 +1,56 @@
|
||||
Frequently asked questions about the sunxi clock system
|
||||
=======================================================
|
||||
|
||||
This document contains useful bits of information that people tend to ask
|
||||
about the sunxi clock system, as well as accompanying ASCII art when adequate.
|
||||
|
||||
Q: Why is the main 24MHz oscillator gatable? Wouldn't that break the
|
||||
system?
|
||||
|
||||
A: The 24MHz oscillator allows gating to save power. Indeed, if gated
|
||||
carelessly the system would stop functioning, but with the right
|
||||
steps, one can gate it and keep the system running. Consider this
|
||||
simplified suspend example:
|
||||
|
||||
While the system is operational, you would see something like
|
||||
|
||||
24MHz 32kHz
|
||||
|
|
||||
PLL1
|
||||
\
|
||||
\_ CPU Mux
|
||||
|
|
||||
[CPU]
|
||||
|
||||
When you are about to suspend, you switch the CPU Mux to the 32kHz
|
||||
oscillator:
|
||||
|
||||
24Mhz 32kHz
|
||||
| |
|
||||
PLL1 |
|
||||
/
|
||||
CPU Mux _/
|
||||
|
|
||||
[CPU]
|
||||
|
||||
Finally you can gate the main oscillator
|
||||
|
||||
32kHz
|
||||
|
|
||||
|
|
||||
/
|
||||
CPU Mux _/
|
||||
|
|
||||
[CPU]
|
||||
|
||||
Q: Were can I learn more about the sunxi clocks?
|
||||
|
||||
A: The linux-sunxi wiki contains a page documenting the clock registers,
|
||||
you can find it at
|
||||
|
||||
http://linux-sunxi.org/A10/CCM
|
||||
|
||||
The authoritative source for information at this time is the ccmu driver
|
||||
released by Allwinner, you can find it at
|
||||
|
||||
https://github.com/linux-sunxi/linux-sunxi/tree/sunxi-3.0/arch/arm/mach-sun4i/clock/ccmu
|
||||
@ -174,9 +174,9 @@ int clk_foo_enable(struct clk_hw *hw)
|
||||
};
|
||||
|
||||
Below is a matrix detailing which clk_ops are mandatory based upon the
|
||||
hardware capbilities of that clock. A cell marked as "y" means
|
||||
hardware capabilities of that clock. A cell marked as "y" means
|
||||
mandatory, a cell marked as "n" implies that either including that
|
||||
callback is invalid or otherwise uneccesary. Empty cells are either
|
||||
callback is invalid or otherwise unnecessary. Empty cells are either
|
||||
optional or must be evaluated on a case-by-case basis.
|
||||
|
||||
clock hardware characteristics
|
||||
|
||||
@ -1,19 +1,84 @@
|
||||
NVIDIA Tegra Power Management Controller (PMC)
|
||||
|
||||
Properties:
|
||||
The PMC block interacts with an external Power Management Unit. The PMC
|
||||
mostly controls the entry and exit of the system from different sleep
|
||||
modes. It provides power-gating controllers for SoC and CPU power-islands.
|
||||
|
||||
Required properties:
|
||||
- name : Should be pmc
|
||||
- compatible : Should contain "nvidia,tegra<chip>-pmc".
|
||||
- reg : Offset and length of the register set for the device
|
||||
- clocks : Must contain an entry for each entry in clock-names.
|
||||
- clock-names : Must include the following entries:
|
||||
"pclk" (The Tegra clock of that name),
|
||||
"clk32k_in" (The 32KHz clock input to Tegra).
|
||||
|
||||
Optional properties:
|
||||
- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.
|
||||
The PMU is an external Power Management Unit, whose interrupt output
|
||||
signal is fed into the PMC. This signal is optionally inverted, and then
|
||||
fed into the ARM GIC. The PMC is not involved in the detection or
|
||||
handling of this interrupt signal, merely its inversion.
|
||||
- nvidia,suspend-mode : The suspend mode that the platform should use.
|
||||
Valid values are 0, 1 and 2:
|
||||
0 (LP0): CPU + Core voltage off and DRAM in self-refresh
|
||||
1 (LP1): CPU voltage off and DRAM in self-refresh
|
||||
2 (LP2): CPU voltage off
|
||||
- nvidia,core-power-req-active-high : Boolean, core power request active-high
|
||||
- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high
|
||||
- nvidia,combined-power-req : Boolean, combined power request for CPU & Core
|
||||
- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC)
|
||||
is enabled.
|
||||
|
||||
Required properties when nvidia,suspend-mode is specified:
|
||||
- nvidia,cpu-pwr-good-time : CPU power good time in uS.
|
||||
- nvidia,cpu-pwr-off-time : CPU power off time in uS.
|
||||
- nvidia,core-pwr-good-time : <Oscillator-stable-time Power-stable-time>
|
||||
Core power good time in uS.
|
||||
- nvidia,core-pwr-off-time : Core power off time in uS.
|
||||
|
||||
Required properties when nvidia,suspend-mode=<0>:
|
||||
- nvidia,lp0-vec : <start length> Starting address and length of LP0 vector
|
||||
The LP0 vector contains the warm boot code that is executed by AVP when
|
||||
resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7
|
||||
processor and always being the first boot processor when chip is power on
|
||||
or resume from deep sleep mode. When the system is resumed from the deep
|
||||
sleep mode, the warm boot code will restore some PLLs, clocks and then
|
||||
bring up CPU0 for resuming the system.
|
||||
|
||||
Example:
|
||||
|
||||
/ SoC dts including file
|
||||
pmc@7000f400 {
|
||||
compatible = "nvidia,tegra20-pmc";
|
||||
reg = <0x7000e400 0x400>;
|
||||
clocks = <&tegra_car 110>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
nvidia,invert-interrupt;
|
||||
nvidia,suspend-mode = <1>;
|
||||
nvidia,cpu-pwr-good-time = <2000>;
|
||||
nvidia,cpu-pwr-off-time = <100>;
|
||||
nvidia,core-pwr-good-time = <3845 3845>;
|
||||
nvidia,core-pwr-off-time = <458>;
|
||||
nvidia,core-power-req-active-high;
|
||||
nvidia,sys-clock-req-active-high;
|
||||
nvidia,lp0-vec = <0xbdffd000 0x2000>;
|
||||
};
|
||||
|
||||
/ Tegra board dts file
|
||||
{
|
||||
...
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
...
|
||||
};
|
||||
|
||||
@ -35,36 +35,83 @@ Required properties:
|
||||
|
||||
Timing properties for child nodes. All are optional and default to 0.
|
||||
|
||||
- gpmc,sync-clk: Minimum clock period for synchronous mode, in picoseconds
|
||||
- gpmc,sync-clk-ps: Minimum clock period for synchronous mode, in picoseconds
|
||||
|
||||
Chip-select signal timings corresponding to GPMC_CONFIG2:
|
||||
- gpmc,cs-on: Assertion time
|
||||
- gpmc,cs-rd-off: Read deassertion time
|
||||
- gpmc,cs-wr-off: Write deassertion time
|
||||
Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2:
|
||||
- gpmc,cs-on-ns: Assertion time
|
||||
- gpmc,cs-rd-off-ns: Read deassertion time
|
||||
- gpmc,cs-wr-off-ns: Write deassertion time
|
||||
|
||||
ADV signal timings corresponding to GPMC_CONFIG3:
|
||||
- gpmc,adv-on: Assertion time
|
||||
- gpmc,adv-rd-off: Read deassertion time
|
||||
- gpmc,adv-wr-off: Write deassertion time
|
||||
ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3:
|
||||
- gpmc,adv-on-ns: Assertion time
|
||||
- gpmc,adv-rd-off-ns: Read deassertion time
|
||||
- gpmc,adv-wr-off-ns: Write deassertion time
|
||||
|
||||
WE signals timings corresponding to GPMC_CONFIG4:
|
||||
- gpmc,we-on: Assertion time
|
||||
- gpmc,we-off: Deassertion time
|
||||
WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
|
||||
- gpmc,we-on-ns Assertion time
|
||||
- gpmc,we-off-ns: Deassertion time
|
||||
|
||||
OE signals timings corresponding to GPMC_CONFIG4:
|
||||
- gpmc,oe-on: Assertion time
|
||||
- gpmc,oe-off: Deassertion time
|
||||
OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
|
||||
- gpmc,oe-on-ns: Assertion time
|
||||
- gpmc,oe-off-ns: Deassertion time
|
||||
|
||||
Access time and cycle time timings corresponding to GPMC_CONFIG5:
|
||||
- gpmc,page-burst-access: Multiple access word delay
|
||||
- gpmc,access: Start-cycle to first data valid delay
|
||||
- gpmc,rd-cycle: Total read cycle time
|
||||
- gpmc,wr-cycle: Total write cycle time
|
||||
Access time and cycle time timings (in nanoseconds) corresponding to
|
||||
GPMC_CONFIG5:
|
||||
- gpmc,page-burst-access-ns: Multiple access word delay
|
||||
- gpmc,access-ns: Start-cycle to first data valid delay
|
||||
- gpmc,rd-cycle-ns: Total read cycle time
|
||||
- gpmc,wr-cycle-ns: Total write cycle time
|
||||
- gpmc,bus-turnaround-ns: Turn-around time between successive accesses
|
||||
- gpmc,cycle2cycle-delay-ns: Delay between chip-select pulses
|
||||
- gpmc,clk-activation-ns: GPMC clock activation time
|
||||
- gpmc,wait-monitoring-ns: Start of wait monitoring with regard to valid
|
||||
data
|
||||
|
||||
Boolean timing parameters. If property is present parameter enabled and
|
||||
disabled if omitted:
|
||||
- gpmc,adv-extra-delay: ADV signal is delayed by half GPMC clock
|
||||
- gpmc,cs-extra-delay: CS signal is delayed by half GPMC clock
|
||||
- gpmc,cycle2cycle-diffcsen: Add "cycle2cycle-delay" between successive
|
||||
accesses to a different CS
|
||||
- gpmc,cycle2cycle-samecsen: Add "cycle2cycle-delay" between successive
|
||||
accesses to the same CS
|
||||
- gpmc,oe-extra-delay: OE signal is delayed by half GPMC clock
|
||||
- gpmc,we-extra-delay: WE signal is delayed by half GPMC clock
|
||||
- gpmc,time-para-granularity: Multiply all access times by 2
|
||||
|
||||
The following are only applicable to OMAP3+ and AM335x:
|
||||
- gpmc,wr-access
|
||||
- gpmc,wr-data-mux-bus
|
||||
- gpmc,wr-access-ns: In synchronous write mode, for single or
|
||||
burst accesses, defines the number of
|
||||
GPMC_FCLK cycles from start access time
|
||||
to the GPMC_CLK rising edge used by the
|
||||
memory device for the first data capture.
|
||||
- gpmc,wr-data-mux-bus-ns: In address-data multiplex mode, specifies
|
||||
the time when the first data is driven on
|
||||
the address-data bus.
|
||||
|
||||
GPMC chip-select settings properties for child nodes. All are optional.
|
||||
|
||||
- gpmc,burst-length Page/burst length. Must be 4, 8 or 16.
|
||||
- gpmc,burst-wrap Enables wrap bursting
|
||||
- gpmc,burst-read Enables read page/burst mode
|
||||
- gpmc,burst-write Enables write page/burst mode
|
||||
- gpmc,device-nand Device is NAND
|
||||
- gpmc,device-width Total width of device(s) connected to a GPMC
|
||||
chip-select in bytes. The GPMC supports 8-bit
|
||||
and 16-bit devices and so this property must be
|
||||
1 or 2.
|
||||
- gpmc,mux-add-data Address and data multiplexing configuration.
|
||||
Valid values are 1 for address-address-data
|
||||
multiplexing mode and 2 for address-data
|
||||
multiplexing mode.
|
||||
- gpmc,sync-read Enables synchronous read. Defaults to asynchronous
|
||||
is this is not set.
|
||||
- gpmc,sync-write Enables synchronous writes. Defaults to asynchronous
|
||||
is this is not set.
|
||||
- gpmc,wait-pin Wait-pin used by client. Must be less than
|
||||
"gpmc,num-waitpins".
|
||||
- gpmc,wait-on-read Enables wait monitoring on reads.
|
||||
- gpmc,wait-on-write Enables wait monitoring on writes.
|
||||
|
||||
Example for an AM33xx board:
|
||||
|
||||
|
||||
22
Documentation/devicetree/bindings/clock/axi-clkgen.txt
Normal file
22
Documentation/devicetree/bindings/clock/axi-clkgen.txt
Normal file
@ -0,0 +1,22 @@
|
||||
Binding for the axi-clkgen clock generator
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "adi,axi-clkgen".
|
||||
- #clock-cells : from common clock binding; Should always be set to 0.
|
||||
- reg : Address and length of the axi-clkgen register set.
|
||||
- clocks : Phandle and clock specifier for the parent clock.
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : From common clock binding.
|
||||
|
||||
Example:
|
||||
clock@0xff000000 {
|
||||
compatible = "adi,axi-clkgen";
|
||||
#clock-cells = <0>;
|
||||
reg = <0xff000000 0x1000>;
|
||||
clocks = <&osc 1>;
|
||||
};
|
||||
288
Documentation/devicetree/bindings/clock/exynos4-clock.txt
Normal file
288
Documentation/devicetree/bindings/clock/exynos4-clock.txt
Normal file
@ -0,0 +1,288 @@
|
||||
* Samsung Exynos4 Clock Controller
|
||||
|
||||
The Exynos4 clock controller generates and supplies clock to various controllers
|
||||
within the Exynos4 SoC. The clock binding described here is applicable to all
|
||||
SoC's in the Exynos4 family.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- comptible: should be one of the following.
|
||||
- "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
|
||||
- "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
The following is the list of clocks generated by the controller. Each clock is
|
||||
assigned an identifier and client nodes use this identifier to specify the
|
||||
clock which they consume. Some of the clocks are available only on a particular
|
||||
Exynos4 SoC and this is specified where applicable.
|
||||
|
||||
|
||||
[Core Clocks]
|
||||
|
||||
Clock ID SoC (if specific)
|
||||
-----------------------------------------------
|
||||
|
||||
xxti 1
|
||||
xusbxti 2
|
||||
fin_pll 3
|
||||
fout_apll 4
|
||||
fout_mpll 5
|
||||
fout_epll 6
|
||||
fout_vpll 7
|
||||
sclk_apll 8
|
||||
sclk_mpll 9
|
||||
sclk_epll 10
|
||||
sclk_vpll 11
|
||||
arm_clk 12
|
||||
aclk200 13
|
||||
aclk100 14
|
||||
aclk160 15
|
||||
aclk133 16
|
||||
mout_mpll_user_t 17 Exynos4x12
|
||||
mout_mpll_user_c 18 Exynos4x12
|
||||
mout_core 19
|
||||
mout_apll 20
|
||||
|
||||
|
||||
[Clock Gate for Special Clocks]
|
||||
|
||||
Clock ID SoC (if specific)
|
||||
-----------------------------------------------
|
||||
|
||||
sclk_fimc0 128
|
||||
sclk_fimc1 129
|
||||
sclk_fimc2 130
|
||||
sclk_fimc3 131
|
||||
sclk_cam0 132
|
||||
sclk_cam1 133
|
||||
sclk_csis0 134
|
||||
sclk_csis1 135
|
||||
sclk_hdmi 136
|
||||
sclk_mixer 137
|
||||
sclk_dac 138
|
||||
sclk_pixel 139
|
||||
sclk_fimd0 140
|
||||
sclk_mdnie0 141 Exynos4412
|
||||
sclk_mdnie_pwm0 12 142 Exynos4412
|
||||
sclk_mipi0 143
|
||||
sclk_audio0 144
|
||||
sclk_mmc0 145
|
||||
sclk_mmc1 146
|
||||
sclk_mmc2 147
|
||||
sclk_mmc3 148
|
||||
sclk_mmc4 149
|
||||
sclk_sata 150 Exynos4210
|
||||
sclk_uart0 151
|
||||
sclk_uart1 152
|
||||
sclk_uart2 153
|
||||
sclk_uart3 154
|
||||
sclk_uart4 155
|
||||
sclk_audio1 156
|
||||
sclk_audio2 157
|
||||
sclk_spdif 158
|
||||
sclk_spi0 159
|
||||
sclk_spi1 160
|
||||
sclk_spi2 161
|
||||
sclk_slimbus 162
|
||||
sclk_fimd1 163 Exynos4210
|
||||
sclk_mipi1 164 Exynos4210
|
||||
sclk_pcm1 165
|
||||
sclk_pcm2 166
|
||||
sclk_i2s1 167
|
||||
sclk_i2s2 168
|
||||
sclk_mipihsi 169 Exynos4412
|
||||
sclk_mfc 170
|
||||
sclk_pcm0 171
|
||||
sclk_g3d 172
|
||||
sclk_pwm_isp 173 Exynos4x12
|
||||
sclk_spi0_isp 174 Exynos4x12
|
||||
sclk_spi1_isp 175 Exynos4x12
|
||||
sclk_uart_isp 176 Exynos4x12
|
||||
|
||||
[Peripheral Clock Gates]
|
||||
|
||||
Clock ID SoC (if specific)
|
||||
-----------------------------------------------
|
||||
|
||||
fimc0 256
|
||||
fimc1 257
|
||||
fimc2 258
|
||||
fimc3 259
|
||||
csis0 260
|
||||
csis1 261
|
||||
jpeg 262
|
||||
smmu_fimc0 263
|
||||
smmu_fimc1 264
|
||||
smmu_fimc2 265
|
||||
smmu_fimc3 266
|
||||
smmu_jpeg 267
|
||||
vp 268
|
||||
mixer 269
|
||||
tvenc 270 Exynos4210
|
||||
hdmi 271
|
||||
smmu_tv 272
|
||||
mfc 273
|
||||
smmu_mfcl 274
|
||||
smmu_mfcr 275
|
||||
g3d 276
|
||||
g2d 277 Exynos4210
|
||||
rotator 278 Exynos4210
|
||||
mdma 279 Exynos4210
|
||||
smmu_g2d 280 Exynos4210
|
||||
smmu_rotator 281 Exynos4210
|
||||
smmu_mdma 282 Exynos4210
|
||||
fimd0 283
|
||||
mie0 284
|
||||
mdnie0 285 Exynos4412
|
||||
dsim0 286
|
||||
smmu_fimd0 287
|
||||
fimd1 288 Exynos4210
|
||||
mie1 289 Exynos4210
|
||||
dsim1 290 Exynos4210
|
||||
smmu_fimd1 291 Exynos4210
|
||||
pdma0 292
|
||||
pdma1 293
|
||||
pcie_phy 294
|
||||
sata_phy 295 Exynos4210
|
||||
tsi 296
|
||||
sdmmc0 297
|
||||
sdmmc1 298
|
||||
sdmmc2 299
|
||||
sdmmc3 300
|
||||
sdmmc4 301
|
||||
sata 302 Exynos4210
|
||||
sromc 303
|
||||
usb_host 304
|
||||
usb_device 305
|
||||
pcie 306
|
||||
onenand 307
|
||||
nfcon 308
|
||||
smmu_pcie 309
|
||||
gps 310
|
||||
smmu_gps 311
|
||||
uart0 312
|
||||
uart1 313
|
||||
uart2 314
|
||||
uart3 315
|
||||
uart4 316
|
||||
i2c0 317
|
||||
i2c1 318
|
||||
i2c2 319
|
||||
i2c3 320
|
||||
i2c4 321
|
||||
i2c5 322
|
||||
i2c6 323
|
||||
i2c7 324
|
||||
i2c_hdmi 325
|
||||
tsadc 326
|
||||
spi0 327
|
||||
spi1 328
|
||||
spi2 329
|
||||
i2s1 330
|
||||
i2s2 331
|
||||
pcm0 332
|
||||
i2s0 333
|
||||
pcm1 334
|
||||
pcm2 335
|
||||
pwm 336
|
||||
slimbus 337
|
||||
spdif 338
|
||||
ac97 339
|
||||
modemif 340
|
||||
chipid 341
|
||||
sysreg 342
|
||||
hdmi_cec 343
|
||||
mct 344
|
||||
wdt 345
|
||||
rtc 346
|
||||
keyif 347
|
||||
audss 348
|
||||
mipi_hsi 349 Exynos4210
|
||||
mdma2 350 Exynos4210
|
||||
pixelasyncm0 351
|
||||
pixelasyncm1 352
|
||||
fimc_lite0 353 Exynos4x12
|
||||
fimc_lite1 354 Exynos4x12
|
||||
ppmuispx 355 Exynos4x12
|
||||
ppmuispmx 356 Exynos4x12
|
||||
fimc_isp 357 Exynos4x12
|
||||
fimc_drc 358 Exynos4x12
|
||||
fimc_fd 359 Exynos4x12
|
||||
mcuisp 360 Exynos4x12
|
||||
gicisp 361 Exynos4x12
|
||||
smmu_isp 362 Exynos4x12
|
||||
smmu_drc 363 Exynos4x12
|
||||
smmu_fd 364 Exynos4x12
|
||||
smmu_lite0 365 Exynos4x12
|
||||
smmu_lite1 366 Exynos4x12
|
||||
mcuctl_isp 367 Exynos4x12
|
||||
mpwm_isp 368 Exynos4x12
|
||||
i2c0_isp 369 Exynos4x12
|
||||
i2c1_isp 370 Exynos4x12
|
||||
mtcadc_isp 371 Exynos4x12
|
||||
pwm_isp 372 Exynos4x12
|
||||
wdt_isp 373 Exynos4x12
|
||||
uart_isp 374 Exynos4x12
|
||||
asyncaxim 375 Exynos4x12
|
||||
smmu_ispcx 376 Exynos4x12
|
||||
spi0_isp 377 Exynos4x12
|
||||
spi1_isp 378 Exynos4x12
|
||||
pwm_isp_sclk 379 Exynos4x12
|
||||
spi0_isp_sclk 380 Exynos4x12
|
||||
spi1_isp_sclk 381 Exynos4x12
|
||||
uart_isp_sclk 382 Exynos4x12
|
||||
|
||||
[Mux Clocks]
|
||||
|
||||
Clock ID SoC (if specific)
|
||||
-----------------------------------------------
|
||||
|
||||
mout_fimc0 384
|
||||
mout_fimc1 385
|
||||
mout_fimc2 386
|
||||
mout_fimc3 387
|
||||
mout_cam0 388
|
||||
mout_cam1 389
|
||||
mout_csis0 390
|
||||
mout_csis1 391
|
||||
mout_g3d0 392
|
||||
mout_g3d1 393
|
||||
mout_g3d 394
|
||||
aclk400_mcuisp 395 Exynos4x12
|
||||
|
||||
[Div Clocks]
|
||||
|
||||
Clock ID SoC (if specific)
|
||||
-----------------------------------------------
|
||||
|
||||
div_isp0 450 Exynos4x12
|
||||
div_isp1 451 Exynos4x12
|
||||
div_mcuisp0 452 Exynos4x12
|
||||
div_mcuisp1 453 Exynos4x12
|
||||
div_aclk200 454 Exynos4x12
|
||||
div_aclk400_mcuisp 455 Exynos4x12
|
||||
|
||||
|
||||
Example 1: An example of a clock controller node is listed below.
|
||||
|
||||
clock: clock-controller@0x10030000 {
|
||||
compatible = "samsung,exynos4210-clock";
|
||||
reg = <0x10030000 0x20000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Example 2: UART controller node that consumes the clock generated by the clock
|
||||
controller. Refer to the standard clock bindings for information
|
||||
about 'clocks' and 'clock-names' property.
|
||||
|
||||
serial@13820000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13820000 0x100>;
|
||||
interrupts = <0 54 0>;
|
||||
clocks = <&clock 314>, <&clock 153>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
177
Documentation/devicetree/bindings/clock/exynos5250-clock.txt
Normal file
177
Documentation/devicetree/bindings/clock/exynos5250-clock.txt
Normal file
@ -0,0 +1,177 @@
|
||||
* Samsung Exynos5250 Clock Controller
|
||||
|
||||
The Exynos5250 clock controller generates and supplies clock to various
|
||||
controllers within the Exynos5250 SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- comptible: should be one of the following.
|
||||
- "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC.
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
The following is the list of clocks generated by the controller. Each clock is
|
||||
assigned an identifier and client nodes use this identifier to specify the
|
||||
clock which they consume.
|
||||
|
||||
|
||||
[Core Clocks]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
|
||||
fin_pll 1
|
||||
|
||||
[Clock Gate for Special Clocks]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
|
||||
sclk_cam_bayer 128
|
||||
sclk_cam0 129
|
||||
sclk_cam1 130
|
||||
sclk_gscl_wa 131
|
||||
sclk_gscl_wb 132
|
||||
sclk_fimd1 133
|
||||
sclk_mipi1 134
|
||||
sclk_dp 135
|
||||
sclk_hdmi 136
|
||||
sclk_pixel 137
|
||||
sclk_audio0 138
|
||||
sclk_mmc0 139
|
||||
sclk_mmc1 140
|
||||
sclk_mmc2 141
|
||||
sclk_mmc3 142
|
||||
sclk_sata 143
|
||||
sclk_usb3 144
|
||||
sclk_jpeg 145
|
||||
sclk_uart0 146
|
||||
sclk_uart1 147
|
||||
sclk_uart2 148
|
||||
sclk_uart3 149
|
||||
sclk_pwm 150
|
||||
sclk_audio1 151
|
||||
sclk_audio2 152
|
||||
sclk_spdif 153
|
||||
sclk_spi0 154
|
||||
sclk_spi1 155
|
||||
sclk_spi2 156
|
||||
|
||||
|
||||
[Peripheral Clock Gates]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
|
||||
gscl0 256
|
||||
gscl1 257
|
||||
gscl2 258
|
||||
gscl3 259
|
||||
gscl_wa 260
|
||||
gscl_wb 261
|
||||
smmu_gscl0 262
|
||||
smmu_gscl1 263
|
||||
smmu_gscl2 264
|
||||
smmu_gscl3 265
|
||||
mfc 266
|
||||
smmu_mfcl 267
|
||||
smmu_mfcr 268
|
||||
rotator 269
|
||||
jpeg 270
|
||||
mdma1 271
|
||||
smmu_rotator 272
|
||||
smmu_jpeg 273
|
||||
smmu_mdma1 274
|
||||
pdma0 275
|
||||
pdma1 276
|
||||
sata 277
|
||||
usbotg 278
|
||||
mipi_hsi 279
|
||||
sdmmc0 280
|
||||
sdmmc1 281
|
||||
sdmmc2 282
|
||||
sdmmc3 283
|
||||
sromc 284
|
||||
usb2 285
|
||||
usb3 286
|
||||
sata_phyctrl 287
|
||||
sata_phyi2c 288
|
||||
uart0 289
|
||||
uart1 290
|
||||
uart2 291
|
||||
uart3 292
|
||||
uart4 293
|
||||
i2c0 294
|
||||
i2c1 295
|
||||
i2c2 296
|
||||
i2c3 297
|
||||
i2c4 298
|
||||
i2c5 299
|
||||
i2c6 300
|
||||
i2c7 301
|
||||
i2c_hdmi 302
|
||||
adc 303
|
||||
spi0 304
|
||||
spi1 305
|
||||
spi2 306
|
||||
i2s1 307
|
||||
i2s2 308
|
||||
pcm1 309
|
||||
pcm2 310
|
||||
pwm 311
|
||||
spdif 312
|
||||
ac97 313
|
||||
hsi2c0 314
|
||||
hsi2c1 315
|
||||
hs12c2 316
|
||||
hs12c3 317
|
||||
chipid 318
|
||||
sysreg 319
|
||||
pmu 320
|
||||
cmu_top 321
|
||||
cmu_core 322
|
||||
cmu_mem 323
|
||||
tzpc0 324
|
||||
tzpc1 325
|
||||
tzpc2 326
|
||||
tzpc3 327
|
||||
tzpc4 328
|
||||
tzpc5 329
|
||||
tzpc6 330
|
||||
tzpc7 331
|
||||
tzpc8 332
|
||||
tzpc9 333
|
||||
hdmi_cec 334
|
||||
mct 335
|
||||
wdt 336
|
||||
rtc 337
|
||||
tmu 338
|
||||
fimd1 339
|
||||
mie1 340
|
||||
dsim0 341
|
||||
dp 342
|
||||
mixer 343
|
||||
hdmi 345
|
||||
|
||||
Example 1: An example of a clock controller node is listed below.
|
||||
|
||||
clock: clock-controller@0x10010000 {
|
||||
compatible = "samsung,exynos5250-clock";
|
||||
reg = <0x10010000 0x30000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Example 2: UART controller node that consumes the clock generated by the clock
|
||||
controller. Refer to the standard clock bindings for information
|
||||
about 'clocks' and 'clock-names' property.
|
||||
|
||||
serial@13820000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13820000 0x100>;
|
||||
interrupts = <0 54 0>;
|
||||
clocks = <&clock 314>, <&clock 153>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
61
Documentation/devicetree/bindings/clock/exynos5440-clock.txt
Normal file
61
Documentation/devicetree/bindings/clock/exynos5440-clock.txt
Normal file
@ -0,0 +1,61 @@
|
||||
* Samsung Exynos5440 Clock Controller
|
||||
|
||||
The Exynos5440 clock controller generates and supplies clock to various
|
||||
controllers within the Exynos5440 SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- comptible: should be "samsung,exynos5440-clock".
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
The following is the list of clocks generated by the controller. Each clock is
|
||||
assigned an identifier and client nodes use this identifier to specify the
|
||||
clock which they consume.
|
||||
|
||||
|
||||
[Core Clocks]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
|
||||
xtal 1
|
||||
arm_clk 2
|
||||
|
||||
[Peripheral Clock Gates]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
|
||||
spi_baud 16
|
||||
pb0_250 17
|
||||
pr0_250 18
|
||||
pr1_250 19
|
||||
b_250 20
|
||||
b_125 21
|
||||
b_200 22
|
||||
sata 23
|
||||
usb 24
|
||||
gmac0 25
|
||||
cs250 26
|
||||
pb0_250_o 27
|
||||
pr0_250_o 28
|
||||
pr1_250_o 29
|
||||
b_250_o 30
|
||||
b_125_o 31
|
||||
b_200_o 32
|
||||
sata_o 33
|
||||
usb_o 34
|
||||
gmac0_o 35
|
||||
cs250_o 36
|
||||
|
||||
Example: An example of a clock controller node is listed below.
|
||||
|
||||
clock: clock-controller@0x10010000 {
|
||||
compatible = "samsung,exynos5440-clock";
|
||||
reg = <0x160000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
303
Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
Normal file
303
Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
Normal file
@ -0,0 +1,303 @@
|
||||
NVIDIA Tegra114 Clock And Reset Controller
|
||||
|
||||
This binding uses the common clock binding:
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
|
||||
for muxing and gating Tegra's clocks, and setting their rates.
|
||||
|
||||
Required properties :
|
||||
- compatible : Should be "nvidia,tegra114-car"
|
||||
- reg : Should contain CAR registers location and length
|
||||
- clocks : Should contain phandle and clock specifiers for two clocks:
|
||||
the 32 KHz "32k_in", and the board-specific oscillator "osc".
|
||||
- #clock-cells : Should be 1.
|
||||
In clock consumers, this cell represents the clock ID exposed by the CAR.
|
||||
|
||||
The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
|
||||
registers. These IDs often match those in the CAR's RST_DEVICES registers,
|
||||
but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
|
||||
this case, those clocks are assigned IDs above 160 in order to highlight
|
||||
this issue. Implementations that interpret these clock IDs as bit values
|
||||
within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
|
||||
explicitly handle these special cases.
|
||||
|
||||
The balance of the clocks controlled by the CAR are assigned IDs of 160 and
|
||||
above.
|
||||
|
||||
0 unassigned
|
||||
1 unassigned
|
||||
2 unassigned
|
||||
3 unassigned
|
||||
4 rtc
|
||||
5 timer
|
||||
6 uarta
|
||||
7 unassigned (register bit affects uartb and vfir)
|
||||
8 unassigned
|
||||
9 sdmmc2
|
||||
10 unassigned (register bit affects spdif_in and spdif_out)
|
||||
11 i2s1
|
||||
12 i2c1
|
||||
13 ndflash
|
||||
14 sdmmc1
|
||||
15 sdmmc4
|
||||
16 unassigned
|
||||
17 pwm
|
||||
18 i2s2
|
||||
19 epp
|
||||
20 unassigned (register bit affects vi and vi_sensor)
|
||||
21 2d
|
||||
22 usbd
|
||||
23 isp
|
||||
24 3d
|
||||
25 unassigned
|
||||
26 disp2
|
||||
27 disp1
|
||||
28 host1x
|
||||
29 vcp
|
||||
30 i2s0
|
||||
31 unassigned
|
||||
|
||||
32 unassigned
|
||||
33 unassigned
|
||||
34 apbdma
|
||||
35 unassigned
|
||||
36 kbc
|
||||
37 unassigned
|
||||
38 unassigned
|
||||
39 unassigned (register bit affects fuse and fuse_burn)
|
||||
40 kfuse
|
||||
41 sbc1
|
||||
42 nor
|
||||
43 unassigned
|
||||
44 sbc2
|
||||
45 unassigned
|
||||
46 sbc3
|
||||
47 i2c5
|
||||
48 dsia
|
||||
49 unassigned
|
||||
50 mipi
|
||||
51 hdmi
|
||||
52 csi
|
||||
53 unassigned
|
||||
54 i2c2
|
||||
55 uartc
|
||||
56 mipi-cal
|
||||
57 emc
|
||||
58 usb2
|
||||
59 usb3
|
||||
60 msenc
|
||||
61 vde
|
||||
62 bsea
|
||||
63 bsev
|
||||
|
||||
64 unassigned
|
||||
65 uartd
|
||||
66 unassigned
|
||||
67 i2c3
|
||||
68 sbc4
|
||||
69 sdmmc3
|
||||
70 unassigned
|
||||
71 owr
|
||||
72 afi
|
||||
73 csite
|
||||
74 unassigned
|
||||
75 unassigned
|
||||
76 la
|
||||
77 trace
|
||||
78 soc_therm
|
||||
79 dtv
|
||||
80 ndspeed
|
||||
81 i2cslow
|
||||
82 dsib
|
||||
83 tsec
|
||||
84 unassigned
|
||||
85 unassigned
|
||||
86 unassigned
|
||||
87 unassigned
|
||||
88 unassigned
|
||||
89 xusb_host
|
||||
90 unassigned
|
||||
91 msenc
|
||||
92 csus
|
||||
93 unassigned
|
||||
94 unassigned
|
||||
95 unassigned (bit affects xusb_dev and xusb_dev_src)
|
||||
|
||||
96 unassigned
|
||||
97 unassigned
|
||||
98 unassigned
|
||||
99 mselect
|
||||
100 tsensor
|
||||
101 i2s3
|
||||
102 i2s4
|
||||
103 i2c4
|
||||
104 sbc5
|
||||
105 sbc6
|
||||
106 d_audio
|
||||
107 apbif
|
||||
108 dam0
|
||||
109 dam1
|
||||
110 dam2
|
||||
111 hda2codec_2x
|
||||
112 unassigned
|
||||
113 audio0_2x
|
||||
114 audio1_2x
|
||||
115 audio2_2x
|
||||
116 audio3_2x
|
||||
117 audio4_2x
|
||||
118 spdif_2x
|
||||
119 actmon
|
||||
120 extern1
|
||||
121 extern2
|
||||
122 extern3
|
||||
123 unassigned
|
||||
124 unassigned
|
||||
125 hda
|
||||
126 unassigned
|
||||
127 se
|
||||
|
||||
128 hda2hdmi
|
||||
129 unassigned
|
||||
130 unassigned
|
||||
131 unassigned
|
||||
132 unassigned
|
||||
133 unassigned
|
||||
134 unassigned
|
||||
135 unassigned
|
||||
136 unassigned
|
||||
137 unassigned
|
||||
138 unassigned
|
||||
139 unassigned
|
||||
140 unassigned
|
||||
141 unassigned
|
||||
142 unassigned
|
||||
143 unassigned (bit affects xusb_falcon_src, xusb_fs_src,
|
||||
xusb_host_src and xusb_ss_src)
|
||||
144 cilab
|
||||
145 cilcd
|
||||
146 cile
|
||||
147 dsialp
|
||||
148 dsiblp
|
||||
149 unassigned
|
||||
150 dds
|
||||
151 unassigned
|
||||
152 dp2
|
||||
153 amx
|
||||
154 adx
|
||||
155 unassigned (bit affects dfll_ref and dfll_soc)
|
||||
156 xusb_ss
|
||||
|
||||
192 uartb
|
||||
193 vfir
|
||||
194 spdif_in
|
||||
195 spdif_out
|
||||
196 vi
|
||||
197 vi_sensor
|
||||
198 fuse
|
||||
199 fuse_burn
|
||||
200 clk_32k
|
||||
201 clk_m
|
||||
202 clk_m_div2
|
||||
203 clk_m_div4
|
||||
204 pll_ref
|
||||
205 pll_c
|
||||
206 pll_c_out1
|
||||
207 pll_c2
|
||||
208 pll_c3
|
||||
209 pll_m
|
||||
210 pll_m_out1
|
||||
211 pll_p
|
||||
212 pll_p_out1
|
||||
213 pll_p_out2
|
||||
214 pll_p_out3
|
||||
215 pll_p_out4
|
||||
216 pll_a
|
||||
217 pll_a_out0
|
||||
218 pll_d
|
||||
219 pll_d_out0
|
||||
220 pll_d2
|
||||
221 pll_d2_out0
|
||||
222 pll_u
|
||||
223 pll_u_480M
|
||||
224 pll_u_60M
|
||||
225 pll_u_48M
|
||||
226 pll_u_12M
|
||||
227 pll_x
|
||||
228 pll_x_out0
|
||||
229 pll_re_vco
|
||||
230 pll_re_out
|
||||
231 pll_e_out0
|
||||
232 spdif_in_sync
|
||||
233 i2s0_sync
|
||||
234 i2s1_sync
|
||||
235 i2s2_sync
|
||||
236 i2s3_sync
|
||||
237 i2s4_sync
|
||||
238 vimclk_sync
|
||||
239 audio0
|
||||
240 audio1
|
||||
241 audio2
|
||||
242 audio3
|
||||
243 audio4
|
||||
244 spdif
|
||||
245 clk_out_1
|
||||
246 clk_out_2
|
||||
247 clk_out_3
|
||||
248 blink
|
||||
252 xusb_host_src
|
||||
253 xusb_falcon_src
|
||||
254 xusb_fs_src
|
||||
255 xusb_ss_src
|
||||
256 xusb_dev_src
|
||||
257 xusb_dev
|
||||
258 xusb_hs_src
|
||||
259 sclk
|
||||
260 hclk
|
||||
261 pclk
|
||||
262 cclk_g
|
||||
263 cclk_lp
|
||||
264 dfll_ref
|
||||
265 dfll_soc
|
||||
|
||||
Example SoC include file:
|
||||
|
||||
/ {
|
||||
tegra_car: clock {
|
||||
compatible = "nvidia,tegra114-car";
|
||||
reg = <0x60006000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
usb@c5004000 {
|
||||
clocks = <&tegra_car 58>; /* usb2 */
|
||||
};
|
||||
};
|
||||
|
||||
Example board file:
|
||||
|
||||
/ {
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
osc: clock@0 {
|
||||
compatible = "fixed-clock";
|
||||
reg = <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
||||
clk_32k: clock@1 {
|
||||
compatible = "fixed-clock";
|
||||
reg = <1>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
&tegra_car {
|
||||
clocks = <&clk_32k> <&osc>;
|
||||
};
|
||||
};
|
||||
@ -120,8 +120,8 @@ Required properties :
|
||||
90 clk_d
|
||||
91 unassigned
|
||||
92 sus
|
||||
93 cdev1
|
||||
94 cdev2
|
||||
93 cdev2
|
||||
94 cdev1
|
||||
95 unassigned
|
||||
|
||||
96 uart2
|
||||
|
||||
44
Documentation/devicetree/bindings/clock/sunxi.txt
Normal file
44
Documentation/devicetree/bindings/clock/sunxi.txt
Normal file
@ -0,0 +1,44 @@
|
||||
Device Tree Clock bindings for arch-sunxi
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be one of the following:
|
||||
"allwinner,sun4i-osc-clk" - for a gatable oscillator
|
||||
"allwinner,sun4i-pll1-clk" - for the main PLL clock
|
||||
"allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
|
||||
"allwinner,sun4i-axi-clk" - for the AXI clock
|
||||
"allwinner,sun4i-ahb-clk" - for the AHB clock
|
||||
"allwinner,sun4i-apb0-clk" - for the APB0 clock
|
||||
"allwinner,sun4i-apb1-clk" - for the APB1 clock
|
||||
"allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
|
||||
|
||||
Required properties for all clocks:
|
||||
- reg : shall be the control register address for the clock.
|
||||
- clocks : shall be the input parent clock(s) phandle for the clock
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
|
||||
For example:
|
||||
|
||||
osc24M: osc24M@01c20050 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-osc-clk";
|
||||
reg = <0x01c20050 0x4>;
|
||||
clocks = <&osc24M_fixed>;
|
||||
};
|
||||
|
||||
pll1: pll1@01c20000 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-pll1-clk";
|
||||
reg = <0x01c20000 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
};
|
||||
|
||||
cpu: cpu@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-cpu-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&osc32k>, <&osc24M>, <&pll1>;
|
||||
};
|
||||
@ -1,24 +0,0 @@
|
||||
VIA/Wondermedia VT8500 GPIO Controller
|
||||
-----------------------------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible : "via,vt8500-gpio", "wm,wm8505-gpio"
|
||||
or "wm,wm8650-gpio" depending on your SoC
|
||||
- reg : Should contain 1 register range (address and length)
|
||||
- #gpio-cells : should be <3>.
|
||||
1) bank
|
||||
2) pin number
|
||||
3) flags - should be 0
|
||||
|
||||
Example:
|
||||
|
||||
gpio: gpio-controller@d8110000 {
|
||||
compatible = "via,vt8500-gpio";
|
||||
gpio-controller;
|
||||
reg = <0xd8110000 0x10000>;
|
||||
#gpio-cells = <3>;
|
||||
};
|
||||
|
||||
vibrate {
|
||||
gpios = <&gpio 0 1 0>; /* Bank 0, Pin 1, No flags */
|
||||
};
|
||||
@ -0,0 +1,53 @@
|
||||
Samsung S3C24XX Interrupt Controllers
|
||||
|
||||
The S3C24XX SoCs contain a custom set of interrupt controllers providing a
|
||||
varying number of interrupt sources. The set consists of a main- and sub-
|
||||
controller and on newer SoCs even a second main controller.
|
||||
|
||||
Required properties:
|
||||
- compatible: Compatible property value should be "samsung,s3c2410-irq"
|
||||
for machines before s3c2416 and "samsung,s3c2416-irq" for s3c2416 and later.
|
||||
|
||||
- reg: Physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
interrupt source. The value shall be 4 and interrupt descriptor shall
|
||||
have the following format:
|
||||
<ctrl_num parent_irq ctrl_irq type>
|
||||
|
||||
ctrl_num contains the controller to use:
|
||||
- 0 ... main controller
|
||||
- 1 ... sub controller
|
||||
- 2 ... second main controller on s3c2416 and s3c2450
|
||||
parent_irq contains the parent bit in the main controller and will be
|
||||
ignored in main controllers
|
||||
ctrl_irq contains the interrupt bit of the controller
|
||||
type contains the trigger type to use
|
||||
|
||||
Example:
|
||||
|
||||
interrupt-controller@4a000000 {
|
||||
compatible = "samsung,s3c2410-irq";
|
||||
reg = <0x4a000000 0x100>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells=<4>;
|
||||
};
|
||||
|
||||
[...]
|
||||
|
||||
serial@50000000 {
|
||||
compatible = "samsung,s3c2410-uart";
|
||||
reg = <0x50000000 0x4000>;
|
||||
interrupt-parent = <&subintc>;
|
||||
interrupts = <1 28 0 4>, <1 28 1 4>;
|
||||
};
|
||||
|
||||
rtc@57000000 {
|
||||
compatible = "samsung,s3c2410-rtc";
|
||||
reg = <0x57000000 0x100>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 30 0 3>, <0 8 0 3>;
|
||||
};
|
||||
@ -21,3 +21,24 @@ Required properties:
|
||||
|
||||
- samsung,mfc-l : Base address of the second memory bank used by MFC
|
||||
for DMA contiguous memory allocation and its size.
|
||||
|
||||
Optional properties:
|
||||
- samsung,power-domain : power-domain property defined with a phandle
|
||||
to respective power domain.
|
||||
|
||||
Example:
|
||||
SoC specific DT entry:
|
||||
|
||||
mfc: codec@13400000 {
|
||||
compatible = "samsung,mfc-v5";
|
||||
reg = <0x13400000 0x10000>;
|
||||
interrupts = <0 94 0>;
|
||||
samsung,power-domain = <&pd_mfc>;
|
||||
};
|
||||
|
||||
Board specific DT entry:
|
||||
|
||||
codec@13400000 {
|
||||
samsung,mfc-r = <0x43000000 0x800000>;
|
||||
samsung,mfc-l = <0x51000000 0x800000>;
|
||||
};
|
||||
|
||||
98
Documentation/devicetree/bindings/mtd/gpmc-nor.txt
Normal file
98
Documentation/devicetree/bindings/mtd/gpmc-nor.txt
Normal file
@ -0,0 +1,98 @@
|
||||
Device tree bindings for NOR flash connect to TI GPMC
|
||||
|
||||
NOR flash connected to the TI GPMC (found on OMAP boards) are represented as
|
||||
child nodes of the GPMC controller with a name of "nor".
|
||||
|
||||
All timing relevant properties as well as generic GPMC child properties are
|
||||
explained in a separate documents. Please refer to
|
||||
Documentation/devicetree/bindings/bus/ti-gpmc.txt
|
||||
|
||||
Required properties:
|
||||
- bank-width: Width of NOR flash in bytes. GPMC supports 8-bit and
|
||||
16-bit devices and so must be either 1 or 2 bytes.
|
||||
- compatible: Documentation/devicetree/bindings/mtd/mtd-physmap.txt
|
||||
- gpmc,cs-on-ns: Chip-select assertion time
|
||||
- gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads
|
||||
- gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes
|
||||
- gpmc,oe-on-ns: Output-enable assertion time
|
||||
- gpmc,oe-off-ns: Output-enable de-assertion time
|
||||
- gpmc,we-on-ns Write-enable assertion time
|
||||
- gpmc,we-off-ns: Write-enable de-assertion time
|
||||
- gpmc,access-ns: Start cycle to first data capture (read access)
|
||||
- gpmc,rd-cycle-ns: Total read cycle time
|
||||
- gpmc,wr-cycle-ns: Total write cycle time
|
||||
- linux,mtd-name: Documentation/devicetree/bindings/mtd/mtd-physmap.txt
|
||||
- reg: Chip-select, base address (relative to chip-select)
|
||||
and size of NOR flash. Note that base address will be
|
||||
typically 0 as this is the start of the chip-select.
|
||||
|
||||
Optional properties:
|
||||
- gpmc,XXX Additional GPMC timings and settings parameters. See
|
||||
Documentation/devicetree/bindings/bus/ti-gpmc.txt
|
||||
|
||||
Optional properties for partiton table parsing:
|
||||
- #address-cells: should be set to 1
|
||||
- #size-cells: should be set to 1
|
||||
|
||||
Example:
|
||||
|
||||
gpmc: gpmc@6e000000 {
|
||||
compatible = "ti,omap3430-gpmc", "simple-bus";
|
||||
ti,hwmods = "gpmc";
|
||||
reg = <0x6e000000 0x1000>;
|
||||
interrupts = <20>;
|
||||
gpmc,num-cs = <8>;
|
||||
gpmc,num-waitpins = <4>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
ranges = <0 0 0x10000000 0x08000000>;
|
||||
|
||||
nor@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
linux,mtd-name= "intel,pf48f6000m0y1be";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0 0 0x08000000>;
|
||||
bank-width = <2>;
|
||||
|
||||
gpmc,mux-add-data;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <186>;
|
||||
gpmc,cs-wr-off-ns = <186>;
|
||||
gpmc,adv-on-ns = <12>;
|
||||
gpmc,adv-rd-off-ns = <48>;
|
||||
gpmc,adv-wr-off-ns = <48>;
|
||||
gpmc,oe-on-ns = <54>;
|
||||
gpmc,oe-off-ns = <168>;
|
||||
gpmc,we-on-ns = <54>;
|
||||
gpmc,we-off-ns = <168>;
|
||||
gpmc,rd-cycle-ns = <186>;
|
||||
gpmc,wr-cycle-ns = <186>;
|
||||
gpmc,access-ns = <114>;
|
||||
gpmc,page-burst-access-ns = <6>;
|
||||
gpmc,bus-turnaround-ns = <12>;
|
||||
gpmc,cycle2cycle-delay-ns = <18>;
|
||||
gpmc,wr-data-mux-bus-ns = <90>;
|
||||
gpmc,wr-access-ns = <186>;
|
||||
gpmc,cycle2cycle-samecsen;
|
||||
gpmc,cycle2cycle-diffcsen;
|
||||
|
||||
partition@0 {
|
||||
label = "bootloader-nor";
|
||||
reg = <0 0x40000>;
|
||||
};
|
||||
partition@0x40000 {
|
||||
label = "params-nor";
|
||||
reg = <0x40000 0x40000>;
|
||||
};
|
||||
partition@0x80000 {
|
||||
label = "kernel-nor";
|
||||
reg = <0x80000 0x200000>;
|
||||
};
|
||||
partition@0x280000 {
|
||||
label = "filesystem-nor";
|
||||
reg = <0x240000 0x7d80000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -10,6 +10,8 @@ Documentation/devicetree/bindings/bus/ti-gpmc.txt
|
||||
Required properties:
|
||||
|
||||
- reg: The CS line the peripheral is connected to
|
||||
- gpmc,device-width Width of the ONENAND device connected to the GPMC
|
||||
in bytes. Must be 1 or 2.
|
||||
|
||||
Optional properties:
|
||||
|
||||
@ -34,6 +36,7 @@ Example for an OMAP3430 board:
|
||||
|
||||
onenand@0 {
|
||||
reg = <0 0 0>; /* CS0, offset 0 */
|
||||
gpmc,device-width = <2>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
97
Documentation/devicetree/bindings/net/gpmc-eth.txt
Normal file
97
Documentation/devicetree/bindings/net/gpmc-eth.txt
Normal file
@ -0,0 +1,97 @@
|
||||
Device tree bindings for Ethernet chip connected to TI GPMC
|
||||
|
||||
Besides being used to interface with external memory devices, the
|
||||
General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices
|
||||
such as ethernet controllers to processors using the TI GPMC as a data bus.
|
||||
|
||||
Ethernet controllers connected to TI GPMC are represented as child nodes of
|
||||
the GPMC controller with an "ethernet" name.
|
||||
|
||||
All timing relevant properties as well as generic GPMC child properties are
|
||||
explained in a separate documents. Please refer to
|
||||
Documentation/devicetree/bindings/bus/ti-gpmc.txt
|
||||
|
||||
For the properties relevant to the ethernet controller connected to the GPMC
|
||||
refer to the binding documentation of the device. For example, the documentation
|
||||
for the SMSC 911x is Documentation/devicetree/bindings/net/smsc911x.txt
|
||||
|
||||
Child nodes need to specify the GPMC bus address width using the "bank-width"
|
||||
property but is possible that an ethernet controller also has a property to
|
||||
specify the I/O registers address width. Even when the GPMC has a maximum 16-bit
|
||||
address width, it supports devices with 32-bit word registers.
|
||||
For example with an SMSC LAN911x/912x controller connected to the TI GPMC on an
|
||||
OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".
|
||||
|
||||
Required properties:
|
||||
- bank-width: Address width of the device in bytes. GPMC supports 8-bit
|
||||
and 16-bit devices and so must be either 1 or 2 bytes.
|
||||
- compatible: Compatible string property for the ethernet child device.
|
||||
- gpmc,cs-on: Chip-select assertion time
|
||||
- gpmc,cs-rd-off: Chip-select de-assertion time for reads
|
||||
- gpmc,cs-wr-off: Chip-select de-assertion time for writes
|
||||
- gpmc,oe-on: Output-enable assertion time
|
||||
- gpmc,oe-off Output-enable de-assertion time
|
||||
- gpmc,we-on: Write-enable assertion time
|
||||
- gpmc,we-off: Write-enable de-assertion time
|
||||
- gpmc,access: Start cycle to first data capture (read access)
|
||||
- gpmc,rd-cycle: Total read cycle time
|
||||
- gpmc,wr-cycle: Total write cycle time
|
||||
- reg: Chip-select, base address (relative to chip-select)
|
||||
and size of the memory mapped for the device.
|
||||
Note that base address will be typically 0 as this
|
||||
is the start of the chip-select.
|
||||
|
||||
Optional properties:
|
||||
- gpmc,XXX Additional GPMC timings and settings parameters. See
|
||||
Documentation/devicetree/bindings/bus/ti-gpmc.txt
|
||||
|
||||
Example:
|
||||
|
||||
gpmc: gpmc@6e000000 {
|
||||
compatible = "ti,omap3430-gpmc";
|
||||
ti,hwmods = "gpmc";
|
||||
reg = <0x6e000000 0x1000>;
|
||||
interrupts = <20>;
|
||||
gpmc,num-cs = <8>;
|
||||
gpmc,num-waitpins = <4>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
ranges = <5 0 0x2c000000 0x1000000>;
|
||||
|
||||
ethernet@5,0 {
|
||||
compatible = "smsc,lan9221", "smsc,lan9115";
|
||||
reg = <5 0 0xff>;
|
||||
bank-width = <2>;
|
||||
|
||||
gpmc,mux-add-data;
|
||||
gpmc,cs-on = <0>;
|
||||
gpmc,cs-rd-off = <186>;
|
||||
gpmc,cs-wr-off = <186>;
|
||||
gpmc,adv-on = <12>;
|
||||
gpmc,adv-rd-off = <48>;
|
||||
gpmc,adv-wr-off = <48>;
|
||||
gpmc,oe-on = <54>;
|
||||
gpmc,oe-off = <168>;
|
||||
gpmc,we-on = <54>;
|
||||
gpmc,we-off = <168>;
|
||||
gpmc,rd-cycle = <186>;
|
||||
gpmc,wr-cycle = <186>;
|
||||
gpmc,access = <114>;
|
||||
gpmc,page-burst-access = <6>;
|
||||
gpmc,bus-turnaround = <12>;
|
||||
gpmc,cycle2cycle-delay = <18>;
|
||||
gpmc,wr-data-mux-bus = <90>;
|
||||
gpmc,wr-access = <186>;
|
||||
gpmc,cycle2cycle-samecsen;
|
||||
gpmc,cycle2cycle-diffcsen;
|
||||
|
||||
interrupt-parent = <&gpio6>;
|
||||
interrupts = <16>;
|
||||
vmmc-supply = <&vddvario>;
|
||||
vmmc_aux-supply = <&vdd33a>;
|
||||
reg-io-width = <4>;
|
||||
|
||||
smsc,save-mac-address;
|
||||
};
|
||||
};
|
||||
57
Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt
Normal file
57
Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt
Normal file
@ -0,0 +1,57 @@
|
||||
VIA VT8500 and Wondermedia WM8xxx-series pinmux/gpio controller
|
||||
|
||||
These SoCs contain a combined Pinmux/GPIO module. Each pin may operate as
|
||||
either a GPIO in, GPIO out or as an alternate function (I2C, SPI etc).
|
||||
|
||||
Required properties:
|
||||
- compatible: "via,vt8500-pinctrl", "wm,wm8505-pinctrl", "wm,wm8650-pinctrl",
|
||||
"wm8750-pinctrl" or "wm,wm8850-pinctrl"
|
||||
- reg: Should contain the physical address of the module's registers.
|
||||
- interrupt-controller: Marks the device node as an interrupt controller.
|
||||
- #interrupt-cells: Should be two.
|
||||
- gpio-controller: Marks the device node as a GPIO controller.
|
||||
- #gpio-cells : Should be two. The first cell is the pin number and the
|
||||
second cell is used to specify optional parameters.
|
||||
bit 0 - active low
|
||||
|
||||
Please refer to ../gpio/gpio.txt for a general description of GPIO bindings.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
Each pin configuration node lists the pin(s) to which it applies, and one or
|
||||
more of the mux functions to select on those pin(s), and pull-up/down
|
||||
configuration. Each subnode only affects those parameters that are explicitly
|
||||
listed. In other words, a subnode that lists only a mux function implies no
|
||||
information about any pull configuration. Similarly, a subnode that lists only
|
||||
a pull parameter implies no information about the mux function.
|
||||
|
||||
Required subnode-properties:
|
||||
- wm,pins: An array of cells. Each cell contains the ID of a pin.
|
||||
|
||||
Optional subnode-properties:
|
||||
- wm,function: Integer, containing the function to mux to the pin(s):
|
||||
0: GPIO in
|
||||
1: GPIO out
|
||||
2: alternate
|
||||
|
||||
- wm,pull: Integer, representing the pull-down/up to apply to the pin(s):
|
||||
0: none
|
||||
1: down
|
||||
2: up
|
||||
|
||||
Each of wm,function and wm,pull may contain either a single value which
|
||||
will be applied to all pins in wm,pins, or one value for each entry in
|
||||
wm,pins.
|
||||
|
||||
Example:
|
||||
|
||||
pinctrl: pinctrl {
|
||||
compatible = "wm,wm8505-pinctrl";
|
||||
reg = <0xD8110000 0x10000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
75
Documentation/devicetree/bindings/reset/reset.txt
Normal file
75
Documentation/devicetree/bindings/reset/reset.txt
Normal file
@ -0,0 +1,75 @@
|
||||
= Reset Signal Device Tree Bindings =
|
||||
|
||||
This binding is intended to represent the hardware reset signals present
|
||||
internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole
|
||||
standalone chips are most likely better represented as GPIOs, although there
|
||||
are likely to be exceptions to this rule.
|
||||
|
||||
Hardware blocks typically receive a reset signal. This signal is generated by
|
||||
a reset provider (e.g. power management or clock module) and received by a
|
||||
reset consumer (the module being reset, or a module managing when a sub-
|
||||
ordinate module is reset). This binding exists to represent the provider and
|
||||
consumer, and provide a way to couple the two together.
|
||||
|
||||
A reset signal is represented by the phandle of the provider, plus a reset
|
||||
specifier - a list of DT cells that represents the reset signal within the
|
||||
provider. The length (number of cells) and semantics of the reset specifier
|
||||
are dictated by the binding of the reset provider, although common schemes
|
||||
are described below.
|
||||
|
||||
A word on where to place reset signal consumers in device tree: It is possible
|
||||
in hardware for a reset signal to affect multiple logically separate HW blocks
|
||||
at once. In this case, it would be unwise to represent this reset signal in
|
||||
the DT node of each affected HW block, since if activated, an unrelated block
|
||||
may be reset. Instead, reset signals should be represented in the DT node
|
||||
where it makes most sense to control it; this may be a bus node if all
|
||||
children of the bus are affected by the reset signal, or an individual HW
|
||||
block node for dedicated reset signals. The intent of this binding is to give
|
||||
appropriate software access to the reset signals in order to manage the HW,
|
||||
rather than to slavishly enumerate the reset signal that affects each HW
|
||||
block.
|
||||
|
||||
= Reset providers =
|
||||
|
||||
Required properties:
|
||||
#reset-cells: Number of cells in a reset specifier; Typically 0 for nodes
|
||||
with a single reset output and 1 for nodes with multiple
|
||||
reset outputs.
|
||||
|
||||
For example:
|
||||
|
||||
rst: reset-controller {
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
= Reset consumers =
|
||||
|
||||
Required properties:
|
||||
resets: List of phandle and reset specifier pairs, one pair
|
||||
for each reset signal that affects the device, or that the
|
||||
device manages. Note: if the reset provider specifies '0' for
|
||||
#reset-cells, then only the phandle portion of the pair will
|
||||
appear.
|
||||
|
||||
Optional properties:
|
||||
reset-names: List of reset signal name strings sorted in the same order as
|
||||
the resets property. Consumers drivers will use reset-names to
|
||||
match reset signal names with reset specifiers.
|
||||
|
||||
For example:
|
||||
|
||||
device {
|
||||
resets = <&rst 20>;
|
||||
reset-names = "reset";
|
||||
};
|
||||
|
||||
This represents a device with a single reset signal named "reset".
|
||||
|
||||
bus {
|
||||
resets = <&rst 10> <&rst 11> <&rst 12> <&rst 11>;
|
||||
reset-names = "i2s1", "i2s2", "dma", "mixer";
|
||||
};
|
||||
|
||||
This represents a bus that controls the reset signal of each of four sub-
|
||||
ordinate devices. Consider for example a bus that fails to operate unless no
|
||||
child device has reset asserted.
|
||||
@ -0,0 +1,17 @@
|
||||
Cadence TTC - Triple Timer Counter
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "cdns,ttc".
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
- interrupts : A list of 3 interrupts; one per timer channel.
|
||||
- clocks: phandle to the source clock
|
||||
|
||||
Example:
|
||||
|
||||
ttc0: ttc0@f8001000 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = < 0 10 4 0 11 4 0 12 4 >;
|
||||
compatible = "cdns,ttc";
|
||||
reg = <0xF8001000 0x1000>;
|
||||
clocks = <&cpu_clk 3>;
|
||||
};
|
||||
@ -0,0 +1,68 @@
|
||||
Samsung's Multi Core Timer (MCT)
|
||||
|
||||
The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
|
||||
global timer and CPU local timers. The global timer is a 64-bit free running
|
||||
up-counter and can generate 4 interrupts when the counter reaches one of the
|
||||
four preset counter values. The CPU local timers are 32-bit free running
|
||||
down-counters and generate an interrupt when the counter expires. There is
|
||||
one CPU local timer instantiated in MCT for every CPU in the system.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: should be "samsung,exynos4210-mct".
|
||||
(a) "samsung,exynos4210-mct", for mct compatible with Exynos4210 mct.
|
||||
(b) "samsung,exynos4412-mct", for mct compatible with Exynos4412 mct.
|
||||
|
||||
- reg: base address of the mct controller and length of the address space
|
||||
it occupies.
|
||||
|
||||
- interrupts: the list of interrupts generated by the controller. The following
|
||||
should be the order of the interrupts specified. The local timer interrupts
|
||||
should be specified after the four global timer interrupts have been
|
||||
specified.
|
||||
|
||||
0: Global Timer Interrupt 0
|
||||
1: Global Timer Interrupt 1
|
||||
2: Global Timer Interrupt 2
|
||||
3: Global Timer Interrupt 3
|
||||
4: Local Timer Interrupt 0
|
||||
5: Local Timer Interrupt 1
|
||||
6: ..
|
||||
7: ..
|
||||
i: Local Timer Interrupt n
|
||||
|
||||
Example 1: In this example, the system uses only the first global timer
|
||||
interrupt generated by MCT and the remaining three global timer
|
||||
interrupts are unused. Two local timer interrupts have been
|
||||
specified.
|
||||
|
||||
mct@10050000 {
|
||||
compatible = "samsung,exynos4210-mct";
|
||||
reg = <0x10050000 0x800>;
|
||||
interrupts = <0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>,
|
||||
<0 42 0>, <0 48 0>;
|
||||
};
|
||||
|
||||
Example 2: In this example, the MCT global and local timer interrupts are
|
||||
connected to two seperate interrupt controllers. Hence, an
|
||||
interrupt-map is created to map the interrupts to the respective
|
||||
interrupt controllers.
|
||||
|
||||
mct@101C0000 {
|
||||
compatible = "samsung,exynos4210-mct";
|
||||
reg = <0x101C0000 0x800>;
|
||||
interrupt-controller;
|
||||
#interrups-cells = <2>;
|
||||
interrupt-parent = <&mct_map>;
|
||||
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
|
||||
<4 0>, <5 0>;
|
||||
|
||||
mct_map: mct-map {
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <0x0 0 &combiner 23 3>,
|
||||
<0x4 0 &gic 0 120 0>,
|
||||
<0x5 0 &gic 0 121 0>;
|
||||
};
|
||||
};
|
||||
40
Documentation/devicetree/bindings/usb/exynos-usb.txt
Normal file
40
Documentation/devicetree/bindings/usb/exynos-usb.txt
Normal file
@ -0,0 +1,40 @@
|
||||
Samsung Exynos SoC USB controller
|
||||
|
||||
The USB devices interface with USB controllers on Exynos SOCs.
|
||||
The device node has following properties.
|
||||
|
||||
EHCI
|
||||
Required properties:
|
||||
- compatible: should be "samsung,exynos4210-ehci" for USB 2.0
|
||||
EHCI controller in host mode.
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- interrupts: interrupt number to the cpu.
|
||||
|
||||
Optional properties:
|
||||
- samsung,vbus-gpio: if present, specifies the GPIO that
|
||||
needs to be pulled up for the bus to be powered.
|
||||
|
||||
Example:
|
||||
|
||||
usb@12110000 {
|
||||
compatible = "samsung,exynos4210-ehci";
|
||||
reg = <0x12110000 0x100>;
|
||||
interrupts = <0 71 0>;
|
||||
samsung,vbus-gpio = <&gpx2 6 1 3 3>;
|
||||
};
|
||||
|
||||
OHCI
|
||||
Required properties:
|
||||
- compatible: should be "samsung,exynos4210-ohci" for USB 2.0
|
||||
OHCI companion controller in host mode.
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- interrupts: interrupt number to the cpu.
|
||||
|
||||
Example:
|
||||
usb@12120000 {
|
||||
compatible = "samsung,exynos4210-ohci";
|
||||
reg = <0x12120000 0x100>;
|
||||
interrupts = <0 71 0>;
|
||||
};
|
||||
@ -673,6 +673,7 @@ config ARCH_TEGRA
|
||||
select HAVE_CLK
|
||||
select HAVE_SMP
|
||||
select MIGHT_HAVE_CACHE_L2X0
|
||||
select SOC_BUS
|
||||
select SPARSE_IRQ
|
||||
select USE_OF
|
||||
help
|
||||
@ -769,12 +770,15 @@ config ARCH_SA1100
|
||||
config ARCH_S3C24XX
|
||||
bool "Samsung S3C24XX SoCs"
|
||||
select ARCH_HAS_CPUFREQ
|
||||
select ARCH_USES_GETTIMEOFFSET
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select CLKDEV_LOOKUP
|
||||
select CLKSRC_MMIO
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_CLK
|
||||
select HAVE_S3C2410_I2C if I2C
|
||||
select HAVE_S3C2410_WATCHDOG if WATCHDOG
|
||||
select HAVE_S3C_RTC if RTC_CLASS
|
||||
select MULTI_IRQ_HANDLER
|
||||
select NEED_MACH_GPIO_H
|
||||
select NEED_MACH_IO_H
|
||||
help
|
||||
@ -787,10 +791,11 @@ config ARCH_S3C64XX
|
||||
bool "Samsung S3C64XX"
|
||||
select ARCH_HAS_CPUFREQ
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARCH_USES_GETTIMEOFFSET
|
||||
select ARM_VIC
|
||||
select CLKDEV_LOOKUP
|
||||
select CLKSRC_MMIO
|
||||
select CPU_V6
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_CLK
|
||||
select HAVE_S3C2410_I2C if I2C
|
||||
select HAVE_S3C2410_WATCHDOG if WATCHDOG
|
||||
@ -824,9 +829,11 @@ config ARCH_S5P64X0
|
||||
|
||||
config ARCH_S5PC100
|
||||
bool "Samsung S5PC100"
|
||||
select ARCH_USES_GETTIMEOFFSET
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select CLKDEV_LOOKUP
|
||||
select CLKSRC_MMIO
|
||||
select CPU_V7
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_CLK
|
||||
select HAVE_S3C2410_I2C if I2C
|
||||
select HAVE_S3C2410_WATCHDOG if WATCHDOG
|
||||
@ -853,18 +860,11 @@ config ARCH_S5PV210
|
||||
help
|
||||
Samsung S5PV210/S5PC110 series based systems
|
||||
|
||||
config ARCH_EXYNOS
|
||||
config ARCH_EXYNOS_SINGLE
|
||||
bool "Samsung EXYNOS"
|
||||
select ARCH_HAS_CPUFREQ
|
||||
select ARCH_HAS_HOLES_MEMORYMODEL
|
||||
select ARCH_SPARSEMEM_ENABLE
|
||||
select CLKDEV_LOOKUP
|
||||
select CPU_V7
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_CLK
|
||||
select HAVE_S3C2410_I2C if I2C
|
||||
select HAVE_S3C2410_WATCHDOG if WATCHDOG
|
||||
select HAVE_S3C_RTC if RTC_CLASS
|
||||
select NEED_MACH_GPIO_H
|
||||
select NEED_MACH_MEMORY_H
|
||||
help
|
||||
@ -1603,6 +1603,7 @@ config HAVE_ARM_ARCH_TIMER
|
||||
config HAVE_ARM_TWD
|
||||
bool
|
||||
depends on SMP
|
||||
select CLKSRC_OF if OF
|
||||
help
|
||||
This options enables support for the ARM timer and watchdog unit
|
||||
|
||||
@ -1656,7 +1657,7 @@ config LOCAL_TIMERS
|
||||
bool "Use local timer interrupts"
|
||||
depends on SMP
|
||||
default y
|
||||
select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
|
||||
select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !CLKSRC_EXYNOS_MCT)
|
||||
help
|
||||
Enable support for local timers on SMP platforms, rather then the
|
||||
legacy IPI broadcast method. Local timers allows the system
|
||||
@ -1671,7 +1672,8 @@ config ARCH_NR_GPIO
|
||||
default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
|
||||
default 512 if SOC_OMAP5
|
||||
default 355 if ARCH_U8500
|
||||
default 288 if ARCH_VT8500 || ARCH_SUNXI
|
||||
default 352 if ARCH_VT8500
|
||||
default 288 if ARCH_SUNXI
|
||||
default 264 if MACH_H4700
|
||||
default 0
|
||||
help
|
||||
|
||||
@ -330,6 +330,7 @@ choice
|
||||
|
||||
config DEBUG_S3C_UART0
|
||||
depends on PLAT_SAMSUNG
|
||||
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
|
||||
bool "Use S3C UART 0 for low-level debug"
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
@ -341,6 +342,7 @@ choice
|
||||
|
||||
config DEBUG_S3C_UART1
|
||||
depends on PLAT_SAMSUNG
|
||||
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
|
||||
bool "Use S3C UART 1 for low-level debug"
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
@ -352,6 +354,7 @@ choice
|
||||
|
||||
config DEBUG_S3C_UART2
|
||||
depends on PLAT_SAMSUNG
|
||||
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
|
||||
bool "Use S3C UART 2 for low-level debug"
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
@ -363,6 +366,7 @@ choice
|
||||
|
||||
config DEBUG_S3C_UART3
|
||||
depends on PLAT_SAMSUNG && ARCH_EXYNOS
|
||||
select DEBUG_EXYNOS_UART
|
||||
bool "Use S3C UART 3 for low-level debug"
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
@ -485,6 +489,9 @@ choice
|
||||
|
||||
endchoice
|
||||
|
||||
config DEBUG_EXYNOS_UART
|
||||
bool
|
||||
|
||||
config DEBUG_IMX_UART_PORT
|
||||
int "i.MX Debug UART Port Selection" if DEBUG_IMX1_UART || \
|
||||
DEBUG_IMX25_UART || \
|
||||
@ -580,6 +587,7 @@ endchoice
|
||||
|
||||
config DEBUG_LL_INCLUDE
|
||||
string
|
||||
default "debug/exynos.S" if DEBUG_EXYNOS_UART
|
||||
default "debug/icedcc.S" if DEBUG_ICEDCC
|
||||
default "debug/imx.S" if DEBUG_IMX1_UART || \
|
||||
DEBUG_IMX25_UART || \
|
||||
|
||||
@ -42,7 +42,10 @@ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
|
||||
dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
|
||||
exynos4210-smdkv310.dtb \
|
||||
exynos4210-trats.dtb \
|
||||
exynos4412-odroidx.dtb \
|
||||
exynos4412-smdk4412.dtb \
|
||||
exynos4412-origen.dtb \
|
||||
exynos5250-arndale.dtb \
|
||||
exynos5250-smdk5250.dtb \
|
||||
exynos5250-snow.dtb \
|
||||
exynos5440-ssdk5440.dtb
|
||||
|
||||
@ -24,6 +24,144 @@
|
||||
samsung,i2c-max-bus-freq = <378000>;
|
||||
gpios = <&gpb3 0 2 3 0>,
|
||||
<&gpb3 1 2 3 0>;
|
||||
|
||||
max77686@09 {
|
||||
compatible = "maxim,max77686";
|
||||
reg = <0x09>;
|
||||
|
||||
voltage-regulators {
|
||||
ldo1_reg: LDO1 {
|
||||
regulator-name = "P1.0V_LDO_OUT1";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: LDO2 {
|
||||
regulator-name = "P1.8V_LDO_OUT2";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3_reg: LDO3 {
|
||||
regulator-name = "P1.8V_LDO_OUT3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo7_reg: LDO7 {
|
||||
regulator-name = "P1.1V_LDO_OUT7";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo8_reg: LDO8 {
|
||||
regulator-name = "P1.0V_LDO_OUT8";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo10_reg: LDO10 {
|
||||
regulator-name = "P1.8V_LDO_OUT10";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo12_reg: LDO12 {
|
||||
regulator-name = "P3.0V_LDO_OUT12";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo14_reg: LDO14 {
|
||||
regulator-name = "P1.8V_LDO_OUT14";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo15_reg: LDO15 {
|
||||
regulator-name = "P1.0V_LDO_OUT15";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo16_reg: LDO16 {
|
||||
regulator-name = "P1.8V_LDO_OUT16";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck1_reg: BUCK1 {
|
||||
regulator-name = "vdd_mif";
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck2_reg: BUCK2 {
|
||||
regulator-name = "vdd_arm";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck3_reg: BUCK3 {
|
||||
regulator-name = "vdd_int";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck4_reg: BUCK4 {
|
||||
regulator-name = "vdd_g3d";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck5_reg: BUCK5 {
|
||||
regulator-name = "P1.8V_BUCK_OUT5";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck6_reg: BUCK6 {
|
||||
regulator-name = "P1.35V_BUCK_OUT6";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck7_reg: BUCK7 {
|
||||
regulator-name = "P2.0V_BUCK_OUT7";
|
||||
regulator-min-microvolt = <2000000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck8_reg: BUCK8 {
|
||||
regulator-name = "P2.85V_BUCK_OUT8";
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@12C70000 {
|
||||
|
||||
@ -86,6 +86,8 @@
|
||||
compatible = "samsung,s3c2410-wdt";
|
||||
reg = <0x10060000 0x100>;
|
||||
interrupts = <0 43 0>;
|
||||
clocks = <&clock 345>;
|
||||
clock-names = "watchdog";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -93,6 +95,8 @@
|
||||
compatible = "samsung,s3c6410-rtc";
|
||||
reg = <0x10070000 0x100>;
|
||||
interrupts = <0 44 0>, <0 45 0>;
|
||||
clocks = <&clock 346>;
|
||||
clock-names = "rtc";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -100,6 +104,8 @@
|
||||
compatible = "samsung,s5pv210-keypad";
|
||||
reg = <0x100A0000 0x100>;
|
||||
interrupts = <0 109 0>;
|
||||
clocks = <&clock 347>;
|
||||
clock-names = "keypad";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -107,6 +113,8 @@
|
||||
compatible = "samsung,exynos4210-sdhci";
|
||||
reg = <0x12510000 0x100>;
|
||||
interrupts = <0 73 0>;
|
||||
clocks = <&clock 297>, <&clock 145>;
|
||||
clock-names = "hsmmc", "mmc_busclk.2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -114,6 +122,8 @@
|
||||
compatible = "samsung,exynos4210-sdhci";
|
||||
reg = <0x12520000 0x100>;
|
||||
interrupts = <0 74 0>;
|
||||
clocks = <&clock 298>, <&clock 146>;
|
||||
clock-names = "hsmmc", "mmc_busclk.2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -121,6 +131,8 @@
|
||||
compatible = "samsung,exynos4210-sdhci";
|
||||
reg = <0x12530000 0x100>;
|
||||
interrupts = <0 75 0>;
|
||||
clocks = <&clock 299>, <&clock 147>;
|
||||
clock-names = "hsmmc", "mmc_busclk.2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -128,6 +140,16 @@
|
||||
compatible = "samsung,exynos4210-sdhci";
|
||||
reg = <0x12540000 0x100>;
|
||||
interrupts = <0 76 0>;
|
||||
clocks = <&clock 300>, <&clock 148>;
|
||||
clock-names = "hsmmc", "mmc_busclk.2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mfc: codec@13400000 {
|
||||
compatible = "samsung,mfc-v5";
|
||||
reg = <0x13400000 0x10000>;
|
||||
interrupts = <0 94 0>;
|
||||
samsung,power-domain = <&pd_mfc>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -135,6 +157,8 @@
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13800000 0x100>;
|
||||
interrupts = <0 52 0>;
|
||||
clocks = <&clock 312>, <&clock 151>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -142,6 +166,8 @@
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13810000 0x100>;
|
||||
interrupts = <0 53 0>;
|
||||
clocks = <&clock 313>, <&clock 152>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -149,6 +175,8 @@
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13820000 0x100>;
|
||||
interrupts = <0 54 0>;
|
||||
clocks = <&clock 314>, <&clock 153>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -156,6 +184,8 @@
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13830000 0x100>;
|
||||
interrupts = <0 55 0>;
|
||||
clocks = <&clock 315>, <&clock 154>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -165,6 +195,8 @@
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x13860000 0x100>;
|
||||
interrupts = <0 58 0>;
|
||||
clocks = <&clock 317>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -174,6 +206,8 @@
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x13870000 0x100>;
|
||||
interrupts = <0 59 0>;
|
||||
clocks = <&clock 318>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -183,6 +217,8 @@
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x13880000 0x100>;
|
||||
interrupts = <0 60 0>;
|
||||
clocks = <&clock 319>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -192,6 +228,8 @@
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x13890000 0x100>;
|
||||
interrupts = <0 61 0>;
|
||||
clocks = <&clock 320>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -201,6 +239,8 @@
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x138A0000 0x100>;
|
||||
interrupts = <0 62 0>;
|
||||
clocks = <&clock 321>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -210,6 +250,8 @@
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x138B0000 0x100>;
|
||||
interrupts = <0 63 0>;
|
||||
clocks = <&clock 322>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -219,6 +261,8 @@
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x138C0000 0x100>;
|
||||
interrupts = <0 64 0>;
|
||||
clocks = <&clock 323>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -228,6 +272,8 @@
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x138D0000 0x100>;
|
||||
interrupts = <0 65 0>;
|
||||
clocks = <&clock 324>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -239,6 +285,8 @@
|
||||
rx-dma-channel = <&pdma0 6>; /* preliminary */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 327>, <&clock 159>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -250,6 +298,8 @@
|
||||
rx-dma-channel = <&pdma1 6>; /* preliminary */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 328>, <&clock 160>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -261,6 +311,8 @@
|
||||
rx-dma-channel = <&pdma0 8>; /* preliminary */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 329>, <&clock 161>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -275,6 +327,8 @@
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x12680000 0x1000>;
|
||||
interrupts = <0 35 0>;
|
||||
clocks = <&clock 292>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
@ -284,6 +338,8 @@
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x12690000 0x1000>;
|
||||
interrupts = <0 36 0>;
|
||||
clocks = <&clock 293>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
@ -293,6 +349,8 @@
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x12850000 0x1000>;
|
||||
interrupts = <0 34 0>;
|
||||
clocks = <&clock 279>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <1>;
|
||||
|
||||
@ -57,6 +57,12 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
codec@13400000 {
|
||||
samsung,mfc-r = <0x43000000 0x800000>;
|
||||
samsung,mfc-l = <0x51000000 0x800000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13800000 {
|
||||
status = "okay";
|
||||
};
|
||||
@ -121,4 +127,16 @@
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
xusbxti {
|
||||
compatible = "samsung,clock-xusbxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -43,6 +43,12 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
codec@13400000 {
|
||||
samsung,mfc-r = <0x43000000 0x800000>;
|
||||
samsung,mfc-l = <0x51000000 0x800000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13800000 {
|
||||
status = "okay";
|
||||
};
|
||||
@ -189,4 +195,16 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
||||
xusbxti {
|
||||
compatible = "samsung,clock-xusbxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -289,4 +289,16 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
xusbxti {
|
||||
compatible = "samsung,clock-xusbxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -47,6 +47,42 @@
|
||||
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
|
||||
};
|
||||
|
||||
mct@10050000 {
|
||||
compatible = "samsung,exynos4210-mct";
|
||||
reg = <0x10050000 0x800>;
|
||||
interrupt-controller;
|
||||
#interrups-cells = <2>;
|
||||
interrupt-parent = <&mct_map>;
|
||||
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
|
||||
<4 0>, <5 0>;
|
||||
clocks = <&clock 3>, <&clock 344>;
|
||||
clock-names = "fin_pll", "mct";
|
||||
|
||||
mct_map: mct-map {
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <0x0 0 &gic 0 57 0>,
|
||||
<0x1 0 &gic 0 69 0>,
|
||||
<0x2 0 &combiner 12 6>,
|
||||
<0x3 0 &combiner 12 7>,
|
||||
<0x4 0 &gic 0 42 0>,
|
||||
<0x5 0 &gic 0 48 0>;
|
||||
};
|
||||
};
|
||||
|
||||
clock: clock-controller@0x10030000 {
|
||||
compatible = "samsung,exynos4210-clock";
|
||||
reg = <0x10030000 0x20000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupt-parent = <&combiner>;
|
||||
interrupts = <2 2>, <3 2>;
|
||||
};
|
||||
|
||||
pinctrl_0: pinctrl@11400000 {
|
||||
compatible = "samsung,exynos4210-pinctrl";
|
||||
reg = <0x11400000 0x1000>;
|
||||
|
||||
@ -25,4 +25,26 @@
|
||||
gic:interrupt-controller@10490000 {
|
||||
cpu-offset = <0x8000>;
|
||||
};
|
||||
|
||||
mct@10050000 {
|
||||
compatible = "samsung,exynos4412-mct";
|
||||
reg = <0x10050000 0x800>;
|
||||
interrupt-controller;
|
||||
#interrups-cells = <2>;
|
||||
interrupt-parent = <&mct_map>;
|
||||
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
|
||||
<4 0>, <5 0>;
|
||||
|
||||
mct_map: mct-map {
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <0x0 0 &gic 0 57 0>,
|
||||
<0x1 0 &combiner 12 5>,
|
||||
<0x2 0 &combiner 12 6>,
|
||||
<0x3 0 &combiner 12 7>,
|
||||
<0x4 0 &gic 1 12 0>,
|
||||
<0x5 0 &gic 1 12 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
111
arch/arm/boot/dts/exynos4412-odroidx.dts
Normal file
111
arch/arm/boot/dts/exynos4412-odroidx.dts
Normal file
@ -0,0 +1,111 @@
|
||||
/*
|
||||
* Hardkernel's Exynos4412 based ODROID-X board device tree source
|
||||
*
|
||||
* Copyright (c) 2012 Dongjin Kim <tobetter@gmail.com>
|
||||
*
|
||||
* Device tree source file for Hardkernel's ODROID-X board which is based on
|
||||
* Samsung's Exynos4412 SoC.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "exynos4412.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Hardkernel ODROID-X board based on Exynos4412";
|
||||
compatible = "hardkernel,odroid-x", "samsung,exynos4412";
|
||||
|
||||
memory {
|
||||
reg = <0x40000000 0x40000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
led1 {
|
||||
label = "led1:heart";
|
||||
gpios = <&gpc1 0 1>;
|
||||
default-state = "on";
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
led2 {
|
||||
label = "led2:mmc0";
|
||||
gpios = <&gpc1 2 1>;
|
||||
default-state = "on";
|
||||
linux,default-trigger = "mmc0";
|
||||
};
|
||||
};
|
||||
|
||||
mshc@12550000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
num-slots = <1>;
|
||||
supports-highspeed;
|
||||
broken-cd;
|
||||
fifo-depth = <0x80>;
|
||||
card-detect-delay = <200>;
|
||||
samsung,dw-mshc-ciu-div = <3>;
|
||||
samsung,dw-mshc-sdr-timing = <2 3>;
|
||||
samsung,dw-mshc-ddr-timing = <1 2>;
|
||||
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
regulator_p3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "p3v3_en";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpa1 1 1>;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
rtc@10070000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sdhci@12530000 {
|
||||
bus-width = <4>;
|
||||
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13810000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13820000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13830000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
xusbxti {
|
||||
compatible = "samsung,clock-xusbxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
432
arch/arm/boot/dts/exynos4412-origen.dts
Normal file
432
arch/arm/boot/dts/exynos4412-origen.dts
Normal file
@ -0,0 +1,432 @@
|
||||
/*
|
||||
* Insignal's Exynos4412 based Origen board device tree source
|
||||
*
|
||||
* Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Device tree source file for Insignal's Origen board which is based on
|
||||
* Samsung's Exynos4412 SoC.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "exynos4412.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Insignal Origen evaluation board based on Exynos4412";
|
||||
compatible = "insignal,origen4412", "samsung,exynos4412";
|
||||
|
||||
memory {
|
||||
reg = <0x40000000 0x40000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs ="console=ttySAC2,115200";
|
||||
};
|
||||
|
||||
mmc_reg: voltage-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VMEM_VDD_2.8V";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
gpio = <&gpx1 1 0>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
sdhci@12530000 {
|
||||
bus-width = <4>;
|
||||
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
|
||||
pinctrl-names = "default";
|
||||
vmmc-supply = <&mmc_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mshc@12550000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
num-slots = <1>;
|
||||
supports-highspeed;
|
||||
broken-cd;
|
||||
fifo-depth = <0x80>;
|
||||
card-detect-delay = <200>;
|
||||
samsung,dw-mshc-ciu-div = <3>;
|
||||
samsung,dw-mshc-sdr-timing = <2 3>;
|
||||
samsung,dw-mshc-ddr-timing = <1 2>;
|
||||
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
codec@13400000 {
|
||||
samsung,mfc-r = <0x43000000 0x800000>;
|
||||
samsung,mfc-l = <0x51000000 0x800000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13810000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13820000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13830000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@13860000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
samsung,i2c-sda-delay = <100>;
|
||||
samsung,i2c-max-bus-freq = <20000>;
|
||||
pinctrl-0 = <&i2c0_bus>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
s5m8767_pmic@66 {
|
||||
compatible = "samsung,s5m8767-pmic";
|
||||
reg = <0x66>;
|
||||
|
||||
s5m8767,pmic-buck-default-dvs-idx = <3>;
|
||||
|
||||
s5m8767,pmic-buck-dvs-gpios = <&gpx2 3 0>,
|
||||
<&gpx2 4 0>,
|
||||
<&gpx2 5 0>;
|
||||
|
||||
s5m8767,pmic-buck-ds-gpios = <&gpm3 5 0>,
|
||||
<&gpm3 6 0>,
|
||||
<&gpm3 7 0>;
|
||||
|
||||
s5m8767,pmic-buck2-dvs-voltage = <1250000>, <1200000>,
|
||||
<1200000>, <1200000>,
|
||||
<1200000>, <1200000>,
|
||||
<1200000>, <1200000>;
|
||||
|
||||
s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>,
|
||||
<1100000>, <1100000>,
|
||||
<1100000>, <1100000>,
|
||||
<1100000>, <1100000>;
|
||||
|
||||
s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>,
|
||||
<1200000>, <1200000>,
|
||||
<1200000>, <1200000>,
|
||||
<1200000>, <1200000>;
|
||||
|
||||
regulators {
|
||||
ldo1_reg: LDO1 {
|
||||
regulator-name = "VDD_ALIVE";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo2_reg: LDO2 {
|
||||
regulator-name = "VDDQ_M12";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo3_reg: LDO3 {
|
||||
regulator-name = "VDDIOAP_18";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo4_reg: LDO4 {
|
||||
regulator-name = "VDDQ_PRE";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo5_reg: LDO5 {
|
||||
regulator-name = "VDD18_2M";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo6_reg: LDO6 {
|
||||
regulator-name = "VDD10_MPLL";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo7_reg: LDO7 {
|
||||
regulator-name = "VDD10_XPLL";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo8_reg: LDO8 {
|
||||
regulator-name = "VDD10_MIPI";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo9_reg: LDO9 {
|
||||
regulator-name = "VDD33_LCD";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo10_reg: LDO10 {
|
||||
regulator-name = "VDD18_MIPI";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo11_reg: LDO11 {
|
||||
regulator-name = "VDD18_ABB1";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo12_reg: LDO12 {
|
||||
regulator-name = "VDD33_UOTG";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo13_reg: LDO13 {
|
||||
regulator-name = "VDDIOPERI_18";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo14_reg: LDO14 {
|
||||
regulator-name = "VDD18_ABB02";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo15_reg: LDO15 {
|
||||
regulator-name = "VDD10_USH";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo16_reg: LDO16 {
|
||||
regulator-name = "VDD18_HSIC";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo17_reg: LDO17 {
|
||||
regulator-name = "VDDIOAP_MMC012_28";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo18_reg: LDO18 {
|
||||
regulator-name = "VDDIOPERI_28";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo19_reg: LDO19 {
|
||||
regulator-name = "DVDD25";
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo20_reg: LDO20 {
|
||||
regulator-name = "VDD28_CAM";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo21_reg: LDO21 {
|
||||
regulator-name = "VDD28_AF";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo22_reg: LDO22 {
|
||||
regulator-name = "VDDA28_2M";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo23_reg: LDO23 {
|
||||
regulator-name = "VDD28_TF";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo24_reg: LDO24 {
|
||||
regulator-name = "VDD33_A31";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo25_reg: LDO25 {
|
||||
regulator-name = "VDD18_CAM";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo26_reg: LDO26 {
|
||||
regulator-name = "VDD18_A31";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo27_reg: LDO27 {
|
||||
regulator-name = "GPS_1V8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo28_reg: LDO28 {
|
||||
regulator-name = "DVDD12";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
buck1_reg: BUCK1 {
|
||||
regulator-name = "vdd_mif";
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
buck2_reg: BUCK2 {
|
||||
regulator-name = "vdd_arm";
|
||||
regulator-min-microvolt = <925000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
buck3_reg: BUCK3 {
|
||||
regulator-name = "vdd_int";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
buck4_reg: BUCK4 {
|
||||
regulator-name = "vdd_g3d";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
buck5_reg: BUCK5 {
|
||||
regulator-name = "vdd_m12";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
buck6_reg: BUCK6 {
|
||||
regulator-name = "vdd12_5m";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
buck9_reg: BUCK9 {
|
||||
regulator-name = "vddf28_emmc";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
xusbxti {
|
||||
compatible = "samsung,clock-xusbxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -27,6 +27,19 @@
|
||||
bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
|
||||
};
|
||||
|
||||
sdhci@12530000 {
|
||||
bus-width = <4>;
|
||||
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
codec@13400000 {
|
||||
samsung,mfc-r = <0x43000000 0x800000>;
|
||||
samsung,mfc-l = <0x51000000 0x800000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13800000 {
|
||||
status = "okay";
|
||||
};
|
||||
@ -42,4 +55,16 @@
|
||||
serial@13830000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
xusbxti {
|
||||
compatible = "samsung,clock-xusbxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -25,4 +25,30 @@
|
||||
gic:interrupt-controller@10490000 {
|
||||
cpu-offset = <0x4000>;
|
||||
};
|
||||
|
||||
mct@10050000 {
|
||||
compatible = "samsung,exynos4412-mct";
|
||||
reg = <0x10050000 0x800>;
|
||||
interrupt-controller;
|
||||
#interrups-cells = <2>;
|
||||
interrupt-parent = <&mct_map>;
|
||||
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
|
||||
<4 0>, <5 0>, <6 0>, <7 0>;
|
||||
clocks = <&clock 3>, <&clock 344>;
|
||||
clock-names = "fin_pll", "mct";
|
||||
|
||||
mct_map: mct-map {
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <0x0 0 &gic 0 57 0>,
|
||||
<0x1 0 &combiner 12 5>,
|
||||
<0x2 0 &combiner 12 6>,
|
||||
<0x3 0 &combiner 12 7>,
|
||||
<0x4 0 &gic 1 12 0>,
|
||||
<0x5 0 &gic 1 12 0>,
|
||||
<0x6 0 &gic 1 12 0>,
|
||||
<0x7 0 &gic 1 12 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -36,6 +36,12 @@
|
||||
<0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>;
|
||||
};
|
||||
|
||||
clock: clock-controller@0x10030000 {
|
||||
compatible = "samsung,exynos4412-clock";
|
||||
reg = <0x10030000 0x20000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
pinctrl_0: pinctrl@11400000 {
|
||||
compatible = "samsung,exynos4x12-pinctrl";
|
||||
reg = <0x11400000 0x1000>;
|
||||
|
||||
129
arch/arm/boot/dts/exynos5250-arndale.dts
Normal file
129
arch/arm/boot/dts/exynos5250-arndale.dts
Normal file
@ -0,0 +1,129 @@
|
||||
/*
|
||||
* Samsung's Exynos5250 based Arndale board device tree source
|
||||
*
|
||||
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "exynos5250.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Insignal Arndale evaluation board based on EXYNOS5250";
|
||||
compatible = "insignal,arndale", "samsung,exynos5250";
|
||||
|
||||
memory {
|
||||
reg = <0x40000000 0x80000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttySAC2,115200";
|
||||
};
|
||||
|
||||
i2c@12C60000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@12C70000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@12C80000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@12C90000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@12CA0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@12CB0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@12CC0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@12CD0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@121D0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dwmmc_0: dwmmc0@12200000 {
|
||||
num-slots = <1>;
|
||||
supports-highspeed;
|
||||
broken-cd;
|
||||
fifo-depth = <0x80>;
|
||||
card-detect-delay = <200>;
|
||||
samsung,dw-mshc-ciu-div = <3>;
|
||||
samsung,dw-mshc-sdr-timing = <2 3>;
|
||||
samsung,dw-mshc-ddr-timing = <1 2>;
|
||||
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <8>;
|
||||
gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
|
||||
<&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
|
||||
<&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>,
|
||||
<&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
|
||||
<&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>;
|
||||
};
|
||||
};
|
||||
|
||||
dwmmc_1: dwmmc1@12210000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dwmmc_2: dwmmc2@12220000 {
|
||||
num-slots = <1>;
|
||||
supports-highspeed;
|
||||
fifo-depth = <0x80>;
|
||||
card-detect-delay = <200>;
|
||||
samsung,dw-mshc-ciu-div = <3>;
|
||||
samsung,dw-mshc-sdr-timing = <2 3>;
|
||||
samsung,dw-mshc-ddr-timing = <1 2>;
|
||||
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
|
||||
gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
|
||||
<&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
|
||||
<&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>;
|
||||
};
|
||||
};
|
||||
|
||||
dwmmc_3: dwmmc3@12230000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi_0: spi@12d20000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi_1: spi@12d30000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi_2: spi@12d40000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -231,4 +231,24 @@
|
||||
samsung,i2s-controller = <&i2s0>;
|
||||
samsung,audio-codec = <&wm8994>;
|
||||
};
|
||||
|
||||
usb@12110000 {
|
||||
samsung,vbus-gpio = <&gpx2 6 1 3 3>;
|
||||
};
|
||||
|
||||
dp-controller {
|
||||
samsung,color-space = <0>;
|
||||
samsung,dynamic-range = <0>;
|
||||
samsung,ycbcr-coeff = <0>;
|
||||
samsung,color-depth = <1>;
|
||||
samsung,link-rate = <0x0a>;
|
||||
samsung,lane-count = <4>;
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -40,4 +40,15 @@
|
||||
<&gpc4 5 2 3 0>, <&gpc4 6 2 3 0>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@12110000 {
|
||||
samsung,vbus-gpio = <&gpx1 1 1 3 3>;
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -46,6 +46,22 @@
|
||||
i2c8 = &i2c_8;
|
||||
};
|
||||
|
||||
pd_gsc: gsc-power-domain@0x10044000 {
|
||||
compatible = "samsung,exynos4210-pd";
|
||||
reg = <0x10044000 0x20>;
|
||||
};
|
||||
|
||||
pd_mfc: mfc-power-domain@0x10044040 {
|
||||
compatible = "samsung,exynos4210-pd";
|
||||
reg = <0x10044040 0x20>;
|
||||
};
|
||||
|
||||
clock: clock-controller@0x10010000 {
|
||||
compatible = "samsung,exynos5250-clock";
|
||||
reg = <0x10010000 0x30000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
gic:interrupt-controller@10481000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
@ -69,58 +85,105 @@
|
||||
<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
|
||||
};
|
||||
|
||||
mct@101C0000 {
|
||||
compatible = "samsung,exynos4210-mct";
|
||||
reg = <0x101C0000 0x800>;
|
||||
interrupt-controller;
|
||||
#interrups-cells = <2>;
|
||||
interrupt-parent = <&mct_map>;
|
||||
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
|
||||
<4 0>, <5 0>;
|
||||
clocks = <&clock 1>, <&clock 335>;
|
||||
clock-names = "fin_pll", "mct";
|
||||
|
||||
mct_map: mct-map {
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <0x0 0 &combiner 23 3>,
|
||||
<0x1 0 &combiner 23 4>,
|
||||
<0x2 0 &combiner 25 2>,
|
||||
<0x3 0 &combiner 25 3>,
|
||||
<0x4 0 &gic 0 120 0>,
|
||||
<0x5 0 &gic 0 121 0>;
|
||||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a15-pmu";
|
||||
interrupt-parent = <&combiner>;
|
||||
interrupts = <1 2>, <22 4>;
|
||||
};
|
||||
|
||||
watchdog {
|
||||
compatible = "samsung,s3c2410-wdt";
|
||||
reg = <0x101D0000 0x100>;
|
||||
interrupts = <0 42 0>;
|
||||
clocks = <&clock 336>;
|
||||
clock-names = "watchdog";
|
||||
};
|
||||
|
||||
codec@11000000 {
|
||||
compatible = "samsung,mfc-v6";
|
||||
reg = <0x11000000 0x10000>;
|
||||
interrupts = <0 96 0>;
|
||||
samsung,power-domain = <&pd_mfc>;
|
||||
};
|
||||
|
||||
rtc {
|
||||
compatible = "samsung,s3c6410-rtc";
|
||||
reg = <0x101E0000 0x100>;
|
||||
interrupts = <0 43 0>, <0 44 0>;
|
||||
clocks = <&clock 337>;
|
||||
clock-names = "rtc";
|
||||
};
|
||||
|
||||
tmu@10060000 {
|
||||
compatible = "samsung,exynos5250-tmu";
|
||||
reg = <0x10060000 0x100>;
|
||||
interrupts = <0 65 0>;
|
||||
clocks = <&clock 338>;
|
||||
clock-names = "tmu_apbif";
|
||||
};
|
||||
|
||||
serial@12C00000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x12C00000 0x100>;
|
||||
interrupts = <0 51 0>;
|
||||
clocks = <&clock 289>, <&clock 146>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
serial@12C10000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x12C10000 0x100>;
|
||||
interrupts = <0 52 0>;
|
||||
clocks = <&clock 290>, <&clock 147>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
serial@12C20000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x12C20000 0x100>;
|
||||
interrupts = <0 53 0>;
|
||||
clocks = <&clock 291>, <&clock 148>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
serial@12C30000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x12C30000 0x100>;
|
||||
interrupts = <0 54 0>;
|
||||
clocks = <&clock 292>, <&clock 149>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
sata@122F0000 {
|
||||
compatible = "samsung,exynos5-sata-ahci";
|
||||
reg = <0x122F0000 0x1ff>;
|
||||
interrupts = <0 115 0>;
|
||||
clocks = <&clock 277>, <&clock 143>;
|
||||
clock-names = "sata", "sclk_sata";
|
||||
};
|
||||
|
||||
sata-phy@12170000 {
|
||||
@ -134,6 +197,8 @@
|
||||
interrupts = <0 56 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 294>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c_1: i2c@12C70000 {
|
||||
@ -142,6 +207,8 @@
|
||||
interrupts = <0 57 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 295>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c_2: i2c@12C80000 {
|
||||
@ -150,6 +217,8 @@
|
||||
interrupts = <0 58 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 296>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c_3: i2c@12C90000 {
|
||||
@ -158,6 +227,8 @@
|
||||
interrupts = <0 59 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 297>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c_4: i2c@12CA0000 {
|
||||
@ -166,6 +237,8 @@
|
||||
interrupts = <0 60 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 298>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c_5: i2c@12CB0000 {
|
||||
@ -174,6 +247,8 @@
|
||||
interrupts = <0 61 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 299>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c_6: i2c@12CC0000 {
|
||||
@ -182,6 +257,8 @@
|
||||
interrupts = <0 62 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 300>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c_7: i2c@12CD0000 {
|
||||
@ -190,6 +267,8 @@
|
||||
interrupts = <0 63 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 301>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c_8: i2c@12CE0000 {
|
||||
@ -198,6 +277,8 @@
|
||||
interrupts = <0 64 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 302>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c@121D0000 {
|
||||
@ -205,6 +286,8 @@
|
||||
reg = <0x121D0000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 288>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
spi_0: spi@12d20000 {
|
||||
@ -216,6 +299,8 @@
|
||||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 304>, <&clock 154>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
};
|
||||
|
||||
spi_1: spi@12d30000 {
|
||||
@ -227,6 +312,8 @@
|
||||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 305>, <&clock 155>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
};
|
||||
|
||||
spi_2: spi@12d40000 {
|
||||
@ -238,6 +325,8 @@
|
||||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 306>, <&clock 156>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
};
|
||||
|
||||
dwmmc_0: dwmmc0@12200000 {
|
||||
@ -246,6 +335,8 @@
|
||||
interrupts = <0 75 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 280>, <&clock 139>;
|
||||
clock-names = "biu", "ciu";
|
||||
};
|
||||
|
||||
dwmmc_1: dwmmc1@12210000 {
|
||||
@ -254,6 +345,8 @@
|
||||
interrupts = <0 76 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 281>, <&clock 140>;
|
||||
clock-names = "biu", "ciu";
|
||||
};
|
||||
|
||||
dwmmc_2: dwmmc2@12220000 {
|
||||
@ -262,6 +355,8 @@
|
||||
interrupts = <0 77 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 282>, <&clock 141>;
|
||||
clock-names = "biu", "ciu";
|
||||
};
|
||||
|
||||
dwmmc_3: dwmmc3@12230000 {
|
||||
@ -270,6 +365,8 @@
|
||||
interrupts = <0 78 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 283>, <&clock 142>;
|
||||
clock-names = "biu", "ciu";
|
||||
};
|
||||
|
||||
i2s0: i2s@03830000 {
|
||||
@ -301,6 +398,18 @@
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
usb@12110000 {
|
||||
compatible = "samsung,exynos4210-ehci";
|
||||
reg = <0x12110000 0x100>;
|
||||
interrupts = <0 71 0>;
|
||||
};
|
||||
|
||||
usb@12120000 {
|
||||
compatible = "samsung,exynos4210-ohci";
|
||||
reg = <0x12120000 0x100>;
|
||||
interrupts = <0 71 0>;
|
||||
};
|
||||
|
||||
amba {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
@ -312,6 +421,8 @@
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x121A0000 0x1000>;
|
||||
interrupts = <0 34 0>;
|
||||
clocks = <&clock 275>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
@ -321,6 +432,8 @@
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x121B0000 0x1000>;
|
||||
interrupts = <0 35 0>;
|
||||
clocks = <&clock 276>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
@ -330,6 +443,8 @@
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x10800000 0x1000>;
|
||||
interrupts = <0 33 0>;
|
||||
clocks = <&clock 271>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <1>;
|
||||
@ -339,6 +454,8 @@
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x11C10000 0x1000>;
|
||||
interrupts = <0 124 0>;
|
||||
clocks = <&clock 271>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <1>;
|
||||
@ -592,34 +709,51 @@
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
gsc_0: gsc@0x13e00000 {
|
||||
compatible = "samsung,exynos5-gsc";
|
||||
reg = <0x13e00000 0x1000>;
|
||||
interrupts = <0 85 0>;
|
||||
samsung,power-domain = <&pd_gsc>;
|
||||
clocks = <&clock 256>;
|
||||
clock-names = "gscl";
|
||||
};
|
||||
|
||||
gsc_1: gsc@0x13e10000 {
|
||||
compatible = "samsung,exynos5-gsc";
|
||||
reg = <0x13e10000 0x1000>;
|
||||
interrupts = <0 86 0>;
|
||||
samsung,power-domain = <&pd_gsc>;
|
||||
clocks = <&clock 257>;
|
||||
clock-names = "gscl";
|
||||
};
|
||||
|
||||
gsc_2: gsc@0x13e20000 {
|
||||
compatible = "samsung,exynos5-gsc";
|
||||
reg = <0x13e20000 0x1000>;
|
||||
interrupts = <0 87 0>;
|
||||
samsung,power-domain = <&pd_gsc>;
|
||||
clocks = <&clock 258>;
|
||||
clock-names = "gscl";
|
||||
};
|
||||
|
||||
gsc_3: gsc@0x13e30000 {
|
||||
compatible = "samsung,exynos5-gsc";
|
||||
reg = <0x13e30000 0x1000>;
|
||||
interrupts = <0 88 0>;
|
||||
samsung,power-domain = <&pd_gsc>;
|
||||
clocks = <&clock 259>;
|
||||
clock-names = "gscl";
|
||||
};
|
||||
|
||||
hdmi {
|
||||
compatible = "samsung,exynos5-hdmi";
|
||||
reg = <0x14530000 0x70000>;
|
||||
interrupts = <0 95 0>;
|
||||
clocks = <&clock 333>, <&clock 136>, <&clock 137>,
|
||||
<&clock 333>, <&clock 333>;
|
||||
clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
|
||||
"sclk_hdmiphy", "hdmiphy";
|
||||
};
|
||||
|
||||
mixer {
|
||||
@ -627,4 +761,18 @@
|
||||
reg = <0x14450000 0x10000>;
|
||||
interrupts = <0 94 0>;
|
||||
};
|
||||
|
||||
dp-controller {
|
||||
compatible = "samsung,exynos5-dp";
|
||||
reg = <0x145b0000 0x1000>;
|
||||
interrupts = <10 3>;
|
||||
interrupt-parent = <&combiner>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dptx-phy {
|
||||
reg = <0x10040720>;
|
||||
samsung,enable-mask = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -28,19 +28,10 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@F0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@100000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc {
|
||||
status = "disabled";
|
||||
fixed-rate-clocks {
|
||||
xtal {
|
||||
compatible = "samsung,clock-xtal";
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -16,6 +16,12 @@
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
clock: clock-controller@0x160000 {
|
||||
compatible = "samsung,exynos5440-clock";
|
||||
reg = <0x160000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
gic:interrupt-controller@2E0000 {
|
||||
compatible = "arm,cortex-a15-gic";
|
||||
#interrupt-cells = <3>;
|
||||
@ -24,55 +30,51 @@
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a15";
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 13 0xf08>;
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
reg = <0>;
|
||||
};
|
||||
cpu@1 {
|
||||
compatible = "arm,cortex-a15";
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 14 0xf08>;
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
reg = <1>;
|
||||
};
|
||||
cpu@2 {
|
||||
compatible = "arm,cortex-a15";
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 14 0xf08>;
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
reg = <2>;
|
||||
};
|
||||
cpu@3 {
|
||||
compatible = "arm,cortex-a15";
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 14 0xf08>;
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
common {
|
||||
compatible = "samsung,exynos5440";
|
||||
|
||||
timer {
|
||||
compatible = "arm,cortex-a15-timer",
|
||||
"arm,armv7-timer";
|
||||
interrupts = <1 13 0xf08>,
|
||||
<1 14 0xf08>,
|
||||
<1 11 0xf08>,
|
||||
<1 10 0xf08>;
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
|
||||
serial@B0000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0xB0000 0x1000>;
|
||||
interrupts = <0 2 0>;
|
||||
clocks = <&clock 21>, <&clock 21>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
serial@C0000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0xC0000 0x1000>;
|
||||
interrupts = <0 3 0>;
|
||||
clocks = <&clock 21>, <&clock 21>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
spi {
|
||||
@ -83,6 +85,8 @@
|
||||
rx-dma-channel = <&pdma0 4>; /* preliminary */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 21>, <&clock 16>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
};
|
||||
|
||||
pinctrl {
|
||||
@ -110,25 +114,31 @@
|
||||
};
|
||||
|
||||
i2c@F0000 {
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
compatible = "samsung,exynos5440-i2c";
|
||||
reg = <0xF0000 0x1000>;
|
||||
interrupts = <0 5 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 21>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c@100000 {
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
compatible = "samsung,exynos5440-i2c";
|
||||
reg = <0x100000 0x1000>;
|
||||
interrupts = <0 6 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 21>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
watchdog {
|
||||
compatible = "samsung,s3c2410-wdt";
|
||||
reg = <0x110000 0x1000>;
|
||||
interrupts = <0 1 0>;
|
||||
clocks = <&clock 21>;
|
||||
clock-names = "watchdog";
|
||||
};
|
||||
|
||||
amba {
|
||||
@ -142,6 +152,8 @@
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x120000 0x1000>;
|
||||
interrupts = <0 34 0>;
|
||||
clocks = <&clock 21>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
@ -151,6 +163,8 @@
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x121000 0x1000>;
|
||||
interrupts = <0 35 0>;
|
||||
clocks = <&clock 21>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
@ -161,5 +175,7 @@
|
||||
compatible = "samsung,s3c6410-rtc";
|
||||
reg = <0x130000 0x1000>;
|
||||
interrupts = <0 17 0>, <0 16 0>;
|
||||
clocks = <&clock 21>;
|
||||
clock-names = "rtc";
|
||||
};
|
||||
};
|
||||
|
||||
@ -38,6 +38,57 @@
|
||||
};
|
||||
};
|
||||
|
||||
/* HS USB Port 2 RESET */
|
||||
hsusb2_reset: hsusb2_reset_reg {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "hsusb2_reset";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio5 19 0>; /* gpio_147 */
|
||||
startup-delay-us = <70000>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
/* HS USB Port 2 Power */
|
||||
hsusb2_power: hsusb2_power_reg {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "hsusb2_vbus";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&twl_gpio 18 0>; /* GPIO LEDA */
|
||||
startup-delay-us = <70000>;
|
||||
};
|
||||
|
||||
/* HS USB Host PHY on PORT 2 */
|
||||
hsusb2_phy: hsusb2_phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
reset-supply = <&hsusb2_reset>;
|
||||
vcc-supply = <&hsusb2_power>;
|
||||
};
|
||||
};
|
||||
|
||||
&omap3_pmx_core {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <
|
||||
&hsusbb2_pins
|
||||
>;
|
||||
|
||||
hsusbb2_pins: pinmux_hsusbb2_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x5c0 0x3 /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_clk OUTPUT */
|
||||
0x5c2 0x3 /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_stp OUTPUT */
|
||||
0x5c4 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dir INPUT | PULLDOWN */
|
||||
0x5c6 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_nxt INPUT | PULLDOWN */
|
||||
0x5c8 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat0 INPUT | PULLDOWN */
|
||||
0x5cA 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat1 INPUT | PULLDOWN */
|
||||
0x1a4 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat2 INPUT | PULLDOWN */
|
||||
0x1a6 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat3 INPUT | PULLDOWN */
|
||||
0x1a8 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat4 INPUT | PULLDOWN */
|
||||
0x1aa 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat5 INPUT | PULLDOWN */
|
||||
0x1ac 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat6 INPUT | PULLDOWN */
|
||||
0x1ae 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat7 INPUT | PULLDOWN */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
@ -65,3 +116,23 @@
|
||||
&mmc3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usbhshost {
|
||||
port2-mode = "ehci-phy";
|
||||
};
|
||||
|
||||
&usbhsehci {
|
||||
phys = <0 &hsusb2_phy>;
|
||||
};
|
||||
|
||||
&twl_gpio {
|
||||
ti,use-leds;
|
||||
/* pullups: BIT(1) */
|
||||
ti,pullups = <0x000002>;
|
||||
/*
|
||||
* pulldowns:
|
||||
* BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
|
||||
* BIT(15), BIT(16), BIT(17)
|
||||
*/
|
||||
ti,pulldowns = <0x03a1c4>;
|
||||
};
|
||||
|
||||
@ -397,5 +397,36 @@
|
||||
ti,timer-alwon;
|
||||
ti,timer-secure;
|
||||
};
|
||||
|
||||
usbhstll: usbhstll@48062000 {
|
||||
compatible = "ti,usbhs-tll";
|
||||
reg = <0x48062000 0x1000>;
|
||||
interrupts = <78>;
|
||||
ti,hwmods = "usb_tll_hs";
|
||||
};
|
||||
|
||||
usbhshost: usbhshost@48064000 {
|
||||
compatible = "ti,usbhs-host";
|
||||
reg = <0x48064000 0x400>;
|
||||
ti,hwmods = "usb_host_hs";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
usbhsohci: ohci@48064400 {
|
||||
compatible = "ti,ohci-omap3", "usb-ohci";
|
||||
reg = <0x48064400 0x400>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <76>;
|
||||
};
|
||||
|
||||
usbhsehci: ehci@48064800 {
|
||||
compatible = "ti,ehci-omap", "usb-ehci";
|
||||
reg = <0x48064800 0x400>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <77>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
@ -529,5 +529,35 @@
|
||||
ti,hwmods = "timer11";
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
usbhstll: usbhstll@4a062000 {
|
||||
compatible = "ti,usbhs-tll";
|
||||
reg = <0x4a062000 0x1000>;
|
||||
interrupts = <0 78 0x4>;
|
||||
ti,hwmods = "usb_tll_hs";
|
||||
};
|
||||
|
||||
usbhshost: usbhshost@4a064000 {
|
||||
compatible = "ti,usbhs-host";
|
||||
reg = <0x4a064000 0x800>;
|
||||
ti,hwmods = "usb_host_hs";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
usbhsohci: ohci@4a064800 {
|
||||
compatible = "ti,ohci-omap3", "usb-ohci";
|
||||
reg = <0x4a064800 0x400>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 76 0x4>;
|
||||
};
|
||||
|
||||
usbhsehci: ehci@4a064c00 {
|
||||
compatible = "ti,ehci-omap", "usb-ehci";
|
||||
reg = <0x4a064c00 0x400>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 77 0x4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
98
arch/arm/boot/dts/r8a7779.dtsi
Normal file
98
arch/arm/boot/dts/r8a7779.dtsi
Normal file
@ -0,0 +1,98 @@
|
||||
/*
|
||||
* Device Tree Source for Renesas r8a7779
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
* Copyright (C) 2013 Simon Horman
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a7779";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
};
|
||||
cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <2>;
|
||||
};
|
||||
cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f0001000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0xf0001000 0x1000>,
|
||||
<0xf0000100 0x100>;
|
||||
};
|
||||
|
||||
i2c0: i2c@0xffc70000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "renesas,rmobile-iic";
|
||||
reg = <0xffc70000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 79 0x4>;
|
||||
};
|
||||
|
||||
i2c1: i2c@0xffc71000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "renesas,rmobile-iic";
|
||||
reg = <0xffc71000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 82 0x4>;
|
||||
};
|
||||
|
||||
i2c2: i2c@0xffc72000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "renesas,rmobile-iic";
|
||||
reg = <0xffc72000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 80 0x4>;
|
||||
};
|
||||
|
||||
i2c3: i2c@0xffc73000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "renesas,rmobile-iic";
|
||||
reg = <0xffc73000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 81 0x4>;
|
||||
};
|
||||
|
||||
thermal@ffc48000 {
|
||||
compatible = "renesas,rcar-thermal";
|
||||
reg = <0xffc48000 0x38>;
|
||||
};
|
||||
|
||||
sata: sata@fc600000 {
|
||||
compatible = "renesas,rcar-sata";
|
||||
reg = <0xfc600000 0x2000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 100 0x4>;
|
||||
};
|
||||
};
|
||||
@ -12,10 +12,22 @@
|
||||
|
||||
serial@70006300 {
|
||||
status = "okay";
|
||||
clock-frequency = <408000000>;
|
||||
};
|
||||
|
||||
pmc {
|
||||
nvidia,invert-interrupt;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -12,10 +12,22 @@
|
||||
|
||||
serial@70006300 {
|
||||
status = "okay";
|
||||
clock-frequency = <408000000>;
|
||||
};
|
||||
|
||||
pmc {
|
||||
nvidia,invert-interrupt;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -24,10 +24,11 @@
|
||||
0 42 0x04
|
||||
0 121 0x04
|
||||
0 122 0x04>;
|
||||
clocks = <&tegra_car 5>;
|
||||
};
|
||||
|
||||
tegra_car: clock {
|
||||
compatible = "nvidia,tegra114-car, nvidia,tegra30-car";
|
||||
compatible = "nvidia,tegra114-car";
|
||||
reg = <0x60006000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -66,6 +67,7 @@
|
||||
reg-shift = <2>;
|
||||
interrupts = <0 36 0x04>;
|
||||
status = "disabled";
|
||||
clocks = <&tegra_car 6>;
|
||||
};
|
||||
|
||||
serial@70006040 {
|
||||
@ -74,6 +76,7 @@
|
||||
reg-shift = <2>;
|
||||
interrupts = <0 37 0x04>;
|
||||
status = "disabled";
|
||||
clocks = <&tegra_car 192>;
|
||||
};
|
||||
|
||||
serial@70006200 {
|
||||
@ -82,6 +85,7 @@
|
||||
reg-shift = <2>;
|
||||
interrupts = <0 46 0x04>;
|
||||
status = "disabled";
|
||||
clocks = <&tegra_car 55>;
|
||||
};
|
||||
|
||||
serial@70006300 {
|
||||
@ -90,17 +94,21 @@
|
||||
reg-shift = <2>;
|
||||
interrupts = <0 90 0x04>;
|
||||
status = "disabled";
|
||||
clocks = <&tegra_car 65>;
|
||||
};
|
||||
|
||||
rtc {
|
||||
compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
|
||||
reg = <0x7000e000 0x100>;
|
||||
interrupts = <0 2 0x04>;
|
||||
clocks = <&tegra_car 4>;
|
||||
};
|
||||
|
||||
pmc {
|
||||
compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc";
|
||||
compatible = "nvidia,tegra114-pmc";
|
||||
reg = <0x7000e400 0x400>;
|
||||
clocks = <&tegra_car 261>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
};
|
||||
|
||||
iommu {
|
||||
|
||||
@ -444,7 +444,20 @@
|
||||
};
|
||||
|
||||
sdhci@c8000600 {
|
||||
cd-gpios = <&gpio 23 0>; /* gpio PC7 */
|
||||
cd-gpios = <&gpio 23 1>; /* gpio PC7 */
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
|
||||
@ -437,7 +437,7 @@
|
||||
|
||||
sdhci@c8000200 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
|
||||
power-gpios = <&gpio 155 0>; /* gpio PT3 */
|
||||
bus-width = <4>;
|
||||
@ -445,12 +445,25 @@
|
||||
|
||||
sdhci@c8000600 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 58 0>; /* gpio PH2 */
|
||||
cd-gpios = <&gpio 58 1>; /* gpio PH2 */
|
||||
wp-gpios = <&gpio 59 0>; /* gpio PH3 */
|
||||
power-gpios = <&gpio 70 0>; /* gpio PI6 */
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
kbc {
|
||||
status = "okay";
|
||||
nvidia,debounce-delay-ms = <2>;
|
||||
|
||||
@ -436,7 +436,7 @@
|
||||
|
||||
sdhci@c8000000 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 173 0>; /* gpio PV5 */
|
||||
cd-gpios = <&gpio 173 1>; /* gpio PV5 */
|
||||
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
|
||||
power-gpios = <&gpio 169 0>; /* gpio PV1 */
|
||||
bus-width = <4>;
|
||||
@ -447,6 +447,19 @@
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
|
||||
@ -584,7 +584,7 @@
|
||||
|
||||
sdhci@c8000400 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
|
||||
power-gpios = <&gpio 70 0>; /* gpio PI6 */
|
||||
bus-width = <4>;
|
||||
@ -595,6 +595,19 @@
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
|
||||
@ -465,12 +465,25 @@
|
||||
};
|
||||
|
||||
sdhci@c8000600 {
|
||||
cd-gpios = <&gpio 58 0>; /* gpio PH2 */
|
||||
cd-gpios = <&gpio 58 1>; /* gpio PH2 */
|
||||
wp-gpios = <&gpio 59 0>; /* gpio PH3 */
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
|
||||
|
||||
@ -325,11 +325,24 @@
|
||||
|
||||
sdhci@c8000600 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 121 0>; /* gpio PP1 */
|
||||
cd-gpios = <&gpio 121 1>; /* gpio PP1 */
|
||||
wp-gpios = <&gpio 122 0>; /* gpio PP2 */
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
poweroff {
|
||||
compatible = "gpio-poweroff";
|
||||
gpios = <&gpio 191 1>; /* gpio PX7, active low */
|
||||
|
||||
@ -520,7 +520,7 @@
|
||||
|
||||
sdhci@c8000400 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
|
||||
power-gpios = <&gpio 70 0>; /* gpio PI6 */
|
||||
bus-width = <4>;
|
||||
@ -531,6 +531,19 @@
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
||||
@ -510,6 +510,7 @@
|
||||
|
||||
sdhci@c8000400 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 173 0>; /* gpio PV5 */
|
||||
bus-width = <8>;
|
||||
};
|
||||
@ -519,6 +520,19 @@
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
kbc {
|
||||
status = "okay";
|
||||
nvidia,debounce-delay-ms = <20>;
|
||||
|
||||
@ -145,6 +145,7 @@
|
||||
0 1 0x04
|
||||
0 41 0x04
|
||||
0 42 0x04>;
|
||||
clocks = <&tegra_car 5>;
|
||||
};
|
||||
|
||||
tegra_car: clock {
|
||||
@ -304,6 +305,7 @@
|
||||
compatible = "nvidia,tegra20-rtc";
|
||||
reg = <0x7000e000 0x100>;
|
||||
interrupts = <0 2 0x04>;
|
||||
clocks = <&tegra_car 4>;
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
@ -416,6 +418,8 @@
|
||||
pmc {
|
||||
compatible = "nvidia,tegra20-pmc";
|
||||
reg = <0x7000e400 0x400>;
|
||||
clocks = <&tegra_car 110>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
};
|
||||
|
||||
memory-controller@7000f000 {
|
||||
|
||||
@ -257,7 +257,7 @@
|
||||
|
||||
sdhci@78000000 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 155 0>; /* gpio PT3 */
|
||||
power-gpios = <&gpio 31 0>; /* gpio PD7 */
|
||||
bus-width = <4>;
|
||||
@ -268,6 +268,19 @@
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
||||
@ -311,7 +311,7 @@
|
||||
|
||||
sdhci@78000000 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 155 0>; /* gpio PT3 */
|
||||
power-gpios = <&gpio 31 0>; /* gpio PD7 */
|
||||
bus-width = <4>;
|
||||
@ -322,6 +322,19 @@
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
||||
@ -148,6 +148,7 @@
|
||||
0 42 0x04
|
||||
0 121 0x04
|
||||
0 122 0x04>;
|
||||
clocks = <&tegra_car 5>;
|
||||
};
|
||||
|
||||
tegra_car: clock {
|
||||
@ -291,6 +292,7 @@
|
||||
compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
|
||||
reg = <0x7000e000 0x100>;
|
||||
interrupts = <0 2 0x04>;
|
||||
clocks = <&tegra_car 4>;
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
@ -423,8 +425,10 @@
|
||||
};
|
||||
|
||||
pmc {
|
||||
compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
|
||||
compatible = "nvidia,tegra30-pmc";
|
||||
reg = <0x7000e400 0x400>;
|
||||
clocks = <&tegra_car 218>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
};
|
||||
|
||||
memory-controller {
|
||||
|
||||
@ -25,11 +25,13 @@
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio: gpio-controller@d8110000 {
|
||||
compatible = "via,vt8500-gpio";
|
||||
gpio-controller;
|
||||
pinctrl: pinctrl@d8110000 {
|
||||
compatible = "via,vt8500-pinctrl";
|
||||
reg = <0xd8110000 0x10000>;
|
||||
#gpio-cells = <3>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
pmc@d8130000 {
|
||||
|
||||
@ -40,11 +40,13 @@
|
||||
interrupts = <56 57 58 59 60 61 62 63>;
|
||||
};
|
||||
|
||||
gpio: gpio-controller@d8110000 {
|
||||
compatible = "wm,wm8505-gpio";
|
||||
gpio-controller;
|
||||
pinctrl: pinctrl@d8110000 {
|
||||
compatible = "wm,wm8505-pinctrl";
|
||||
reg = <0xd8110000 0x10000>;
|
||||
#gpio-cells = <3>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
pmc@d8130000 {
|
||||
|
||||
@ -34,11 +34,13 @@
|
||||
interrupts = <56 57 58 59 60 61 62 63>;
|
||||
};
|
||||
|
||||
gpio: gpio-controller@d8110000 {
|
||||
compatible = "wm,wm8650-gpio";
|
||||
gpio-controller;
|
||||
pinctrl: pinctrl@d8110000 {
|
||||
compatible = "wm,wm8650-pinctrl";
|
||||
reg = <0xd8110000 0x10000>;
|
||||
#gpio-cells = <3>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
pmc@d8130000 {
|
||||
|
||||
@ -41,11 +41,13 @@
|
||||
interrupts = <56 57 58 59 60 61 62 63>;
|
||||
};
|
||||
|
||||
gpio: gpio-controller@d8110000 {
|
||||
compatible = "wm,wm8650-gpio";
|
||||
gpio-controller;
|
||||
pinctrl: pinctrl@d8110000 {
|
||||
compatible = "wm,wm8850-pinctrl";
|
||||
reg = <0xd8110000 0x10000>;
|
||||
#gpio-cells = <3>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
pmc@d8130000 {
|
||||
|
||||
@ -111,56 +111,23 @@
|
||||
};
|
||||
|
||||
ttc0: ttc0@f8001000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "xlnx,ttc";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = < 0 10 4 0 11 4 0 12 4 >;
|
||||
compatible = "cdns,ttc";
|
||||
reg = <0xF8001000 0x1000>;
|
||||
clocks = <&cpu_clk 3>;
|
||||
clock-names = "cpu_1x";
|
||||
clock-ranges;
|
||||
|
||||
ttc0_0: ttc0.0 {
|
||||
status = "disabled";
|
||||
reg = <0>;
|
||||
interrupts = <0 10 4>;
|
||||
};
|
||||
ttc0_1: ttc0.1 {
|
||||
status = "disabled";
|
||||
reg = <1>;
|
||||
interrupts = <0 11 4>;
|
||||
};
|
||||
ttc0_2: ttc0.2 {
|
||||
status = "disabled";
|
||||
reg = <2>;
|
||||
interrupts = <0 12 4>;
|
||||
};
|
||||
};
|
||||
|
||||
ttc1: ttc1@f8002000 {
|
||||
#interrupt-parent = <&intc>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "xlnx,ttc";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = < 0 37 4 0 38 4 0 39 4 >;
|
||||
compatible = "cdns,ttc";
|
||||
reg = <0xF8002000 0x1000>;
|
||||
clocks = <&cpu_clk 3>;
|
||||
clock-names = "cpu_1x";
|
||||
clock-ranges;
|
||||
|
||||
ttc1_0: ttc1.0 {
|
||||
status = "disabled";
|
||||
reg = <0>;
|
||||
interrupts = <0 37 4>;
|
||||
};
|
||||
ttc1_1: ttc1.1 {
|
||||
status = "disabled";
|
||||
reg = <1>;
|
||||
interrupts = <0 38 4>;
|
||||
};
|
||||
ttc1_2: ttc1.2 {
|
||||
status = "disabled";
|
||||
reg = <2>;
|
||||
interrupts = <0 39 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -32,13 +32,3 @@
|
||||
&ps_clk {
|
||||
clock-frequency = <33333330>;
|
||||
};
|
||||
|
||||
&ttc0_0 {
|
||||
status = "ok";
|
||||
compatible = "xlnx,ttc-counter-clocksource";
|
||||
};
|
||||
|
||||
&ttc0_1 {
|
||||
status = "ok";
|
||||
compatible = "xlnx,ttc-counter-clockevent";
|
||||
};
|
||||
|
||||
@ -4,7 +4,7 @@ CONFIG_KALLSYMS_ALL=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_ARCH_EXYNOS=y
|
||||
CONFIG_ARCH_EXYNOS_SINGLE=y
|
||||
CONFIG_S3C_LOWLEVEL_UART_PORT=1
|
||||
CONFIG_MACH_SMDKC210=y
|
||||
CONFIG_MACH_ARMLEX4210=y
|
||||
|
||||
@ -34,12 +34,4 @@ struct twd_local_timer name __initdata = { \
|
||||
|
||||
int twd_local_timer_register(struct twd_local_timer *);
|
||||
|
||||
#ifdef CONFIG_HAVE_ARM_TWD
|
||||
void twd_local_timer_of_register(void);
|
||||
#else
|
||||
static inline void twd_local_timer_of_register(void)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@ -1,10 +1,7 @@
|
||||
/* linux/arch/arm/mach-exynos4/include/mach/debug-macro.S
|
||||
*
|
||||
/*
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
@ -12,7 +9,10 @@
|
||||
|
||||
/* pull in the relevant register and map files. */
|
||||
|
||||
#include <mach/map.h>
|
||||
#define S3C_ADDR_BASE 0xF6000000
|
||||
#define S3C_VA_UART S3C_ADDR_BASE + 0x01000000
|
||||
#define EXYNOS4_PA_UART 0x13800000
|
||||
#define EXYNOS5_PA_UART 0x12C00000
|
||||
|
||||
/* note, for the boot process to work we have to keep the UART
|
||||
* virtual address aligned to an 1MiB boundary for the L1
|
||||
@ -36,4 +36,4 @@
|
||||
#define fifo_full fifo_full_s5pv210
|
||||
#define fifo_level fifo_level_s5pv210
|
||||
|
||||
#include <plat/debug-macro.S>
|
||||
#include <debug/samsung.S>
|
||||
@ -562,21 +562,21 @@ ENDPROC(__und_usr)
|
||||
@ Fall-through from Thumb-2 __und_usr
|
||||
@
|
||||
#ifdef CONFIG_NEON
|
||||
get_thread_info r10 @ get current thread
|
||||
adr r6, .LCneon_thumb_opcodes
|
||||
b 2f
|
||||
#endif
|
||||
call_fpe:
|
||||
get_thread_info r10 @ get current thread
|
||||
#ifdef CONFIG_NEON
|
||||
adr r6, .LCneon_arm_opcodes
|
||||
2:
|
||||
ldr r7, [r6], #4 @ mask value
|
||||
cmp r7, #0 @ end mask?
|
||||
beq 1f
|
||||
and r8, r0, r7
|
||||
2: ldr r5, [r6], #4 @ mask value
|
||||
ldr r7, [r6], #4 @ opcode bits matching in mask
|
||||
cmp r5, #0 @ end mask?
|
||||
beq 1f
|
||||
and r8, r0, r5
|
||||
cmp r8, r7 @ NEON instruction?
|
||||
bne 2b
|
||||
get_thread_info r10
|
||||
mov r7, #1
|
||||
strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
|
||||
strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
|
||||
@ -586,7 +586,6 @@ call_fpe:
|
||||
tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
|
||||
tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
|
||||
moveq pc, lr
|
||||
get_thread_info r10 @ get current thread
|
||||
and r8, r0, #0x00000f00 @ mask out CP number
|
||||
THUMB( lsr r8, r8, #8 )
|
||||
mov r7, #1
|
||||
|
||||
@ -459,15 +459,16 @@ unsigned long arch_randomize_brk(struct mm_struct *mm)
|
||||
* atomic helpers and the signal restart code. Insert it into the
|
||||
* gate_vma so that it is visible through ptrace and /proc/<pid>/mem.
|
||||
*/
|
||||
static struct vm_area_struct gate_vma;
|
||||
static struct vm_area_struct gate_vma = {
|
||||
.vm_start = 0xffff0000,
|
||||
.vm_end = 0xffff0000 + PAGE_SIZE,
|
||||
.vm_flags = VM_READ | VM_EXEC | VM_MAYREAD | VM_MAYEXEC,
|
||||
.vm_mm = &init_mm,
|
||||
};
|
||||
|
||||
static int __init gate_vma_init(void)
|
||||
{
|
||||
gate_vma.vm_start = 0xffff0000;
|
||||
gate_vma.vm_end = 0xffff0000 + PAGE_SIZE;
|
||||
gate_vma.vm_page_prot = PAGE_READONLY_EXEC;
|
||||
gate_vma.vm_flags = VM_READ | VM_EXEC |
|
||||
VM_MAYREAD | VM_MAYEXEC;
|
||||
gate_vma.vm_page_prot = PAGE_READONLY_EXEC;
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(gate_vma_init);
|
||||
|
||||
@ -362,25 +362,13 @@ int __init twd_local_timer_register(struct twd_local_timer *tlt)
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
const static struct of_device_id twd_of_match[] __initconst = {
|
||||
{ .compatible = "arm,cortex-a9-twd-timer", },
|
||||
{ .compatible = "arm,cortex-a5-twd-timer", },
|
||||
{ .compatible = "arm,arm11mp-twd-timer", },
|
||||
{ },
|
||||
};
|
||||
|
||||
void __init twd_local_timer_of_register(void)
|
||||
static void __init twd_local_timer_of_register(struct device_node *np)
|
||||
{
|
||||
struct device_node *np;
|
||||
int err;
|
||||
|
||||
if (!is_smp() || !setup_max_cpus)
|
||||
return;
|
||||
|
||||
np = of_find_matching_node(NULL, twd_of_match);
|
||||
if (!np)
|
||||
return;
|
||||
|
||||
twd_ppi = irq_of_parse_and_map(np, 0);
|
||||
if (!twd_ppi) {
|
||||
err = -EINVAL;
|
||||
@ -398,4 +386,7 @@ void __init twd_local_timer_of_register(void)
|
||||
out:
|
||||
WARN(err, "twd_local_timer_of_register failed (%d)\n", err);
|
||||
}
|
||||
CLOCKSOURCE_OF_DECLARE(arm_twd_a9, "arm,cortex-a9-twd-timer", twd_local_timer_of_register);
|
||||
CLOCKSOURCE_OF_DECLARE(arm_twd_a5, "arm,cortex-a5-twd-timer", twd_local_timer_of_register);
|
||||
CLOCKSOURCE_OF_DECLARE(arm_twd_11mp, "arm,arm11mp-twd-timer", twd_local_timer_of_register);
|
||||
#endif
|
||||
|
||||
@ -169,6 +169,8 @@ static struct clk *periph_clocks[] __initdata = {
|
||||
};
|
||||
|
||||
static struct clk_lookup periph_clocks_lookups[] = {
|
||||
CLKDEV_CON_DEV_ID("hclk", "at91sam9261-lcdfb.0", &hck1),
|
||||
CLKDEV_CON_DEV_ID("hclk", "at91sam9g10-lcdfb.0", &hck1),
|
||||
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
|
||||
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
|
||||
CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
|
||||
|
||||
@ -488,7 +488,6 @@ static struct resource lcdc_resources[] = {
|
||||
};
|
||||
|
||||
static struct platform_device at91_lcdc_device = {
|
||||
.name = "atmel_lcdfb",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = &lcdc_dmamask,
|
||||
@ -505,6 +504,11 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
|
||||
return;
|
||||
}
|
||||
|
||||
if (cpu_is_at91sam9g10())
|
||||
at91_lcdc_device.name = "at91sam9g10-lcdfb";
|
||||
else
|
||||
at91_lcdc_device.name = "at91sam9261-lcdfb";
|
||||
|
||||
#if defined(CONFIG_FB_ATMEL_STN)
|
||||
at91_set_A_periph(AT91_PIN_PB0, 0); /* LCDVSYNC */
|
||||
at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
|
||||
|
||||
@ -190,6 +190,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
|
||||
CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
|
||||
CLKDEV_CON_DEV_ID("pclk", "fff98000.ssc", &ssc0_clk),
|
||||
CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc1_clk),
|
||||
CLKDEV_CON_DEV_ID("hclk", "at91sam9263-lcdfb.0", &lcdc_clk),
|
||||
CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
|
||||
CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
|
||||
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
|
||||
|
||||
@ -848,7 +848,7 @@ static struct resource lcdc_resources[] = {
|
||||
};
|
||||
|
||||
static struct platform_device at91_lcdc_device = {
|
||||
.name = "atmel_lcdfb",
|
||||
.name = "at91sam9263-lcdfb",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = &lcdc_dmamask,
|
||||
|
||||
@ -228,6 +228,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
|
||||
CLKDEV_CON_ID("hclk", &macb_clk),
|
||||
/* One additional fake clock for ohci */
|
||||
CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
|
||||
CLKDEV_CON_DEV_ID("hclk", "at91sam9g45-lcdfb.0", &lcdc_clk),
|
||||
CLKDEV_CON_DEV_ID("hclk", "at91sam9g45es-lcdfb.0", &lcdc_clk),
|
||||
CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
|
||||
CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
|
||||
CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
|
||||
|
||||
@ -981,7 +981,6 @@ static struct resource lcdc_resources[] = {
|
||||
};
|
||||
|
||||
static struct platform_device at91_lcdc_device = {
|
||||
.name = "atmel_lcdfb",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = &lcdc_dmamask,
|
||||
@ -997,6 +996,11 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
|
||||
if (!data)
|
||||
return;
|
||||
|
||||
if (cpu_is_at91sam9g45es())
|
||||
at91_lcdc_device.name = "at91sam9g45es-lcdfb";
|
||||
else
|
||||
at91_lcdc_device.name = "at91sam9g45-lcdfb";
|
||||
|
||||
at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
|
||||
|
||||
at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
|
||||
|
||||
@ -179,6 +179,7 @@ static struct clk *periph_clocks[] __initdata = {
|
||||
};
|
||||
|
||||
static struct clk_lookup periph_clocks_lookups[] = {
|
||||
CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
|
||||
CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
|
||||
CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
|
||||
CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
|
||||
|
||||
@ -514,7 +514,7 @@ static struct resource lcdc_resources[] = {
|
||||
};
|
||||
|
||||
static struct platform_device at91_lcdc_device = {
|
||||
.name = "atmel_lcdfb",
|
||||
.name = "at91sam9rl-lcdfb",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = &lcdc_dmamask,
|
||||
|
||||
@ -7,6 +7,21 @@
|
||||
|
||||
# Configuration options for the EXYNOS4
|
||||
|
||||
config ARCH_EXYNOS
|
||||
# TODO: make this visible after all drivers are converted
|
||||
bool "Samsung EXYNOS" if ARCH_MULTI_V7 && BROKEN
|
||||
default ARCH_EXYNOS_SINGLE
|
||||
select ARCH_HAS_CPUFREQ
|
||||
select CLKDEV_LOOKUP
|
||||
select COMMON_CLK
|
||||
select CPU_V7
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_CLK
|
||||
select HAVE_S3C2410_I2C if I2C
|
||||
select HAVE_S3C_RTC if RTC_CLASS
|
||||
help
|
||||
Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
|
||||
|
||||
if ARCH_EXYNOS
|
||||
|
||||
menu "SAMSUNG EXYNOS SoCs Support"
|
||||
@ -19,6 +34,9 @@ config ARCH_EXYNOS4
|
||||
help
|
||||
Samsung EXYNOS4 SoCs based systems
|
||||
|
||||
config ARCH_EXYNOS4_SINGLE
|
||||
def_bool ARCH_EXYNOS4 && ARCH_EXYNOS_SINGLE
|
||||
|
||||
config ARCH_EXYNOS5
|
||||
bool "SAMSUNG EXYNOS5"
|
||||
select HAVE_SMP
|
||||
@ -35,7 +53,7 @@ config CPU_EXYNOS4210
|
||||
select PM_GENERIC_DOMAINS
|
||||
select S5P_PM if PM
|
||||
select S5P_SLEEP if PM
|
||||
select SAMSUNG_DMADEV
|
||||
select SAMSUNG_DMADEV if ARCH_EXYNOS_SINGLE
|
||||
help
|
||||
Enable EXYNOS4210 CPU support
|
||||
|
||||
@ -45,7 +63,7 @@ config SOC_EXYNOS4212
|
||||
depends on ARCH_EXYNOS4
|
||||
select S5P_PM if PM
|
||||
select S5P_SLEEP if PM
|
||||
select SAMSUNG_DMADEV
|
||||
select SAMSUNG_DMADEV if ARCH_EXYNOS_SINGLE
|
||||
help
|
||||
Enable EXYNOS4212 SoC support
|
||||
|
||||
@ -53,7 +71,7 @@ config SOC_EXYNOS4412
|
||||
bool "SAMSUNG EXYNOS4412"
|
||||
default y
|
||||
depends on ARCH_EXYNOS4
|
||||
select SAMSUNG_DMADEV
|
||||
select SAMSUNG_DMADEV if ARCH_EXYNOS_SINGLE
|
||||
help
|
||||
Enable EXYNOS4412 SoC support
|
||||
|
||||
@ -61,10 +79,11 @@ config SOC_EXYNOS5250
|
||||
bool "SAMSUNG EXYNOS5250"
|
||||
default y
|
||||
depends on ARCH_EXYNOS5
|
||||
select PM_GENERIC_DOMAINS if PM
|
||||
select S5P_PM if PM
|
||||
select S5P_SLEEP if PM
|
||||
select S5P_DEV_MFC
|
||||
select SAMSUNG_DMADEV
|
||||
select SAMSUNG_DMADEV if ARCH_EXYNOS_SINGLE
|
||||
help
|
||||
Enable EXYNOS5250 SoC support
|
||||
|
||||
@ -79,11 +98,18 @@ config SOC_EXYNOS5440
|
||||
help
|
||||
Enable EXYNOS5440 SoC support
|
||||
|
||||
config EXYNOS4_MCT
|
||||
bool
|
||||
config EXYNOS_ATAGS
|
||||
bool "ATAGS based boot for EXYNOS (deprecated)"
|
||||
depends on !ARCH_MULTIPLATFORM
|
||||
depends on ATAGS
|
||||
default y
|
||||
help
|
||||
Use MCT (Multi Core Timer) as kernel timers
|
||||
The EXYNOS platform is moving towards being completely probed
|
||||
through device tree. This enables support for board files using
|
||||
the traditional ATAGS boot format.
|
||||
Note that this option is not available for multiplatform builds.
|
||||
|
||||
if EXYNOS_ATAGS
|
||||
|
||||
config EXYNOS_DEV_DMA
|
||||
bool
|
||||
@ -276,8 +302,8 @@ config MACH_UNIVERSAL_C210
|
||||
select S5P_DEV_ONENAND
|
||||
select S5P_DEV_TV
|
||||
select S5P_GPIO_INT
|
||||
select S5P_HRT
|
||||
select S5P_SETUP_MIPIPHY
|
||||
select SAMSUNG_HRT
|
||||
help
|
||||
Machine support for Samsung Mobile Universal S5PC210 Reference
|
||||
Board.
|
||||
@ -400,16 +426,20 @@ config MACH_SMDK4412
|
||||
Machine support for Samsung SMDK4412
|
||||
endif
|
||||
|
||||
endif
|
||||
|
||||
comment "Flattened Device Tree based board for EXYNOS SoCs"
|
||||
|
||||
config MACH_EXYNOS4_DT
|
||||
bool "Samsung Exynos4 Machine using device tree"
|
||||
depends on ARCH_EXYNOS4
|
||||
select ARM_AMBA
|
||||
select CLKSRC_OF
|
||||
select CPU_EXYNOS4210
|
||||
select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
|
||||
select PINCTRL
|
||||
select PINCTRL_EXYNOS
|
||||
select S5P_DEV_MFC
|
||||
select USE_OF
|
||||
help
|
||||
Machine support for Samsung Exynos4 machine with device tree enabled.
|
||||
@ -422,6 +452,7 @@ config MACH_EXYNOS5_DT
|
||||
default y
|
||||
depends on ARCH_EXYNOS5
|
||||
select ARM_AMBA
|
||||
select CLKSRC_OF
|
||||
select USE_OF
|
||||
help
|
||||
Machine support for Samsung EXYNOS5 machine with device tree enabled.
|
||||
|
||||
@ -4,6 +4,7 @@
|
||||
# http://www.samsung.com/
|
||||
#
|
||||
# Licensed under GPLv2
|
||||
ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/$(src)/include -I$(srctree)/arch/arm/plat-samsung/include
|
||||
|
||||
obj-y :=
|
||||
obj-m :=
|
||||
@ -13,10 +14,6 @@ obj- :=
|
||||
# Core
|
||||
|
||||
obj-$(CONFIG_ARCH_EXYNOS) += common.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o
|
||||
obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
|
||||
obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
|
||||
obj-$(CONFIG_SOC_EXYNOS5250) += clock-exynos5.o
|
||||
|
||||
obj-$(CONFIG_PM) += pm.o
|
||||
obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
|
||||
@ -26,8 +23,6 @@ obj-$(CONFIG_ARCH_EXYNOS) += pmu.o
|
||||
|
||||
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
|
||||
|
||||
obj-$(CONFIG_EXYNOS4_MCT) += mct.o
|
||||
|
||||
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
|
||||
# machine support
|
||||
@ -48,12 +43,12 @@ obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
|
||||
# device support
|
||||
|
||||
obj-y += dev-uart.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS4_SINGLE) += dev-audio.o
|
||||
obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
|
||||
obj-$(CONFIG_EXYNOS_DEV_DMA) += dma.o
|
||||
obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o
|
||||
|
||||
obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS_SINGLE) += setup-i2c0.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,35 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Header file for exynos4 clock support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_CLOCK_H
|
||||
#define __ASM_ARCH_CLOCK_H __FILE__
|
||||
|
||||
#include <linux/clk.h>
|
||||
|
||||
extern struct clksrc_clk exynos4_clk_aclk_133;
|
||||
extern struct clksrc_clk exynos4_clk_mout_mpll;
|
||||
|
||||
extern struct clksrc_sources exynos4_clkset_mout_corebus;
|
||||
extern struct clksrc_sources exynos4_clkset_group;
|
||||
|
||||
extern struct clk *exynos4_clkset_aclk_top_list[];
|
||||
extern struct clk *exynos4_clkset_group_list[];
|
||||
|
||||
extern struct clksrc_sources exynos4_clkset_mout_g2d0;
|
||||
extern struct clksrc_sources exynos4_clkset_mout_g2d1;
|
||||
|
||||
extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
|
||||
extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
|
||||
extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
|
||||
extern int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable);
|
||||
extern int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable);
|
||||
|
||||
#endif /* __ASM_ARCH_CLOCK_H */
|
||||
@ -1,187 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4210 - Clock support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
|
||||
#include <plat/cpu-freq.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/pll.h>
|
||||
#include <plat/s5p-clock.h>
|
||||
#include <plat/clock-clksrc.h>
|
||||
#include <plat/pm.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-clock.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "clock-exynos4.h"
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct sleep_save exynos4210_clock_save[] = {
|
||||
SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
|
||||
SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
|
||||
SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
|
||||
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
|
||||
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct clksrc_clk *sysclks[] = {
|
||||
/* nothing here yet */
|
||||
};
|
||||
|
||||
static struct clksrc_clk exynos4210_clk_mout_g2d0 = {
|
||||
.clk = {
|
||||
.name = "mout_g2d0",
|
||||
},
|
||||
.sources = &exynos4_clkset_mout_g2d0,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
|
||||
};
|
||||
|
||||
static struct clksrc_clk exynos4210_clk_mout_g2d1 = {
|
||||
.clk = {
|
||||
.name = "mout_g2d1",
|
||||
},
|
||||
.sources = &exynos4_clkset_mout_g2d1,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
|
||||
};
|
||||
|
||||
static struct clk *exynos4210_clkset_mout_g2d_list[] = {
|
||||
[0] = &exynos4210_clk_mout_g2d0.clk,
|
||||
[1] = &exynos4210_clk_mout_g2d1.clk,
|
||||
};
|
||||
|
||||
static struct clksrc_sources exynos4210_clkset_mout_g2d = {
|
||||
.sources = exynos4210_clkset_mout_g2d_list,
|
||||
.nr_sources = ARRAY_SIZE(exynos4210_clkset_mout_g2d_list),
|
||||
};
|
||||
|
||||
static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
|
||||
}
|
||||
|
||||
static struct clksrc_clk clksrcs[] = {
|
||||
{
|
||||
.clk = {
|
||||
.name = "sclk_sata",
|
||||
.id = -1,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 24),
|
||||
},
|
||||
.sources = &exynos4_clkset_mout_corebus,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
|
||||
.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_fimd",
|
||||
.devname = "exynos4-fb.1",
|
||||
.enable = exynos4_clksrc_mask_lcd1_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
},
|
||||
.sources = &exynos4_clkset_group,
|
||||
.reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
|
||||
.reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_fimg2d",
|
||||
},
|
||||
.sources = &exynos4210_clkset_mout_g2d,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
|
||||
.reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk init_clocks_off[] = {
|
||||
{
|
||||
.name = "sataphy",
|
||||
.id = -1,
|
||||
.parent = &exynos4_clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 3),
|
||||
}, {
|
||||
.name = "sata",
|
||||
.id = -1,
|
||||
.parent = &exynos4_clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 10),
|
||||
}, {
|
||||
.name = "fimd",
|
||||
.devname = "exynos4-fb.1",
|
||||
.enable = exynos4_clk_ip_lcd1_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
}, {
|
||||
.name = "sysmmu",
|
||||
.devname = "exynos-sysmmu.9",
|
||||
.enable = exynos4_clk_ip_image_ctrl,
|
||||
.ctrlbit = (1 << 3),
|
||||
}, {
|
||||
.name = "sysmmu",
|
||||
.devname = "exynos-sysmmu.11",
|
||||
.enable = exynos4_clk_ip_lcd1_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
}, {
|
||||
.name = "fimg2d",
|
||||
.enable = exynos4_clk_ip_image_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
},
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int exynos4210_clock_suspend(void)
|
||||
{
|
||||
s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void exynos4210_clock_resume(void)
|
||||
{
|
||||
s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
|
||||
}
|
||||
|
||||
#else
|
||||
#define exynos4210_clock_suspend NULL
|
||||
#define exynos4210_clock_resume NULL
|
||||
#endif
|
||||
|
||||
static struct syscore_ops exynos4210_clock_syscore_ops = {
|
||||
.suspend = exynos4210_clock_suspend,
|
||||
.resume = exynos4210_clock_resume,
|
||||
};
|
||||
|
||||
void __init exynos4210_register_clocks(void)
|
||||
{
|
||||
int ptr;
|
||||
|
||||
exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
|
||||
exynos4_clk_mout_mpll.reg_src.shift = 8;
|
||||
exynos4_clk_mout_mpll.reg_src.size = 1;
|
||||
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
|
||||
s3c_register_clksrc(sysclks[ptr], 1);
|
||||
|
||||
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
|
||||
|
||||
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
||||
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
||||
|
||||
register_syscore_ops(&exynos4210_clock_syscore_ops);
|
||||
}
|
||||
@ -1,201 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4212 - Clock support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
|
||||
#include <plat/cpu-freq.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/pll.h>
|
||||
#include <plat/s5p-clock.h>
|
||||
#include <plat/clock-clksrc.h>
|
||||
#include <plat/pm.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-clock.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "clock-exynos4.h"
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct sleep_save exynos4212_clock_save[] = {
|
||||
SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
|
||||
};
|
||||
#endif
|
||||
|
||||
static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable);
|
||||
}
|
||||
|
||||
static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable);
|
||||
}
|
||||
|
||||
static struct clk *clk_src_mpll_user_list[] = {
|
||||
[0] = &clk_fin_mpll,
|
||||
[1] = &exynos4_clk_mout_mpll.clk,
|
||||
};
|
||||
|
||||
static struct clksrc_sources clk_src_mpll_user = {
|
||||
.sources = clk_src_mpll_user_list,
|
||||
.nr_sources = ARRAY_SIZE(clk_src_mpll_user_list),
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_mout_mpll_user = {
|
||||
.clk = {
|
||||
.name = "mout_mpll_user",
|
||||
},
|
||||
.sources = &clk_src_mpll_user,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
|
||||
};
|
||||
|
||||
static struct clksrc_clk exynos4x12_clk_mout_g2d0 = {
|
||||
.clk = {
|
||||
.name = "mout_g2d0",
|
||||
},
|
||||
.sources = &exynos4_clkset_mout_g2d0,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 20, .size = 1 },
|
||||
};
|
||||
|
||||
static struct clksrc_clk exynos4x12_clk_mout_g2d1 = {
|
||||
.clk = {
|
||||
.name = "mout_g2d1",
|
||||
},
|
||||
.sources = &exynos4_clkset_mout_g2d1,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 24, .size = 1 },
|
||||
};
|
||||
|
||||
static struct clk *exynos4x12_clkset_mout_g2d_list[] = {
|
||||
[0] = &exynos4x12_clk_mout_g2d0.clk,
|
||||
[1] = &exynos4x12_clk_mout_g2d1.clk,
|
||||
};
|
||||
|
||||
static struct clksrc_sources exynos4x12_clkset_mout_g2d = {
|
||||
.sources = exynos4x12_clkset_mout_g2d_list,
|
||||
.nr_sources = ARRAY_SIZE(exynos4x12_clkset_mout_g2d_list),
|
||||
};
|
||||
|
||||
static struct clksrc_clk *sysclks[] = {
|
||||
&clk_mout_mpll_user,
|
||||
};
|
||||
|
||||
static struct clksrc_clk clksrcs[] = {
|
||||
{
|
||||
.clk = {
|
||||
.name = "sclk_fimg2d",
|
||||
},
|
||||
.sources = &exynos4x12_clkset_mout_g2d,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 28, .size = 1 },
|
||||
.reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 0, .size = 4 },
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk init_clocks_off[] = {
|
||||
{
|
||||
.name = "sysmmu",
|
||||
.devname = "exynos-sysmmu.9",
|
||||
.enable = exynos4_clk_ip_dmc_ctrl,
|
||||
.ctrlbit = (1 << 24),
|
||||
}, {
|
||||
.name = "sysmmu",
|
||||
.devname = "exynos-sysmmu.12",
|
||||
.enable = exynos4212_clk_ip_isp0_ctrl,
|
||||
.ctrlbit = (7 << 8),
|
||||
}, {
|
||||
.name = "sysmmu",
|
||||
.devname = "exynos-sysmmu.13",
|
||||
.enable = exynos4212_clk_ip_isp1_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
}, {
|
||||
.name = "sysmmu",
|
||||
.devname = "exynos-sysmmu.14",
|
||||
.enable = exynos4212_clk_ip_isp0_ctrl,
|
||||
.ctrlbit = (1 << 11),
|
||||
}, {
|
||||
.name = "sysmmu",
|
||||
.devname = "exynos-sysmmu.15",
|
||||
.enable = exynos4212_clk_ip_isp0_ctrl,
|
||||
.ctrlbit = (1 << 12),
|
||||
}, {
|
||||
.name = "flite",
|
||||
.devname = "exynos-fimc-lite.0",
|
||||
.enable = exynos4212_clk_ip_isp0_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
}, {
|
||||
.name = "flite",
|
||||
.devname = "exynos-fimc-lite.1",
|
||||
.enable = exynos4212_clk_ip_isp0_ctrl,
|
||||
.ctrlbit = (1 << 3),
|
||||
}, {
|
||||
.name = "fimg2d",
|
||||
.enable = exynos4_clk_ip_dmc_ctrl,
|
||||
.ctrlbit = (1 << 23),
|
||||
},
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int exynos4212_clock_suspend(void)
|
||||
{
|
||||
s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void exynos4212_clock_resume(void)
|
||||
{
|
||||
s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
|
||||
}
|
||||
|
||||
#else
|
||||
#define exynos4212_clock_suspend NULL
|
||||
#define exynos4212_clock_resume NULL
|
||||
#endif
|
||||
|
||||
static struct syscore_ops exynos4212_clock_syscore_ops = {
|
||||
.suspend = exynos4212_clock_suspend,
|
||||
.resume = exynos4212_clock_resume,
|
||||
};
|
||||
|
||||
void __init exynos4212_register_clocks(void)
|
||||
{
|
||||
int ptr;
|
||||
|
||||
/* usbphy1 is removed */
|
||||
exynos4_clkset_group_list[4] = NULL;
|
||||
|
||||
/* mout_mpll_user is used */
|
||||
exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
|
||||
exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
|
||||
|
||||
exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
|
||||
exynos4_clk_mout_mpll.reg_src.shift = 12;
|
||||
exynos4_clk_mout_mpll.reg_src.size = 1;
|
||||
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
|
||||
s3c_register_clksrc(sysclks[ptr], 1);
|
||||
|
||||
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
|
||||
|
||||
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
||||
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
||||
|
||||
register_syscore_ops(&exynos4212_clock_syscore_ops);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@ -25,6 +25,8 @@
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
|
||||
#include <asm/proc-fns.h>
|
||||
@ -37,9 +39,9 @@
|
||||
#include <mach/regs-irq.h>
|
||||
#include <mach/regs-pmu.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/pm.h>
|
||||
#include <plat/sdhci.h>
|
||||
@ -65,17 +67,16 @@ static const char name_exynos5440[] = "EXYNOS5440";
|
||||
static void exynos4_map_io(void);
|
||||
static void exynos5_map_io(void);
|
||||
static void exynos5440_map_io(void);
|
||||
static void exynos4_init_clocks(int xtal);
|
||||
static void exynos5_init_clocks(int xtal);
|
||||
static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
|
||||
static int exynos_init(void);
|
||||
|
||||
unsigned long xxti_f = 0, xusbxti_f = 0;
|
||||
|
||||
static struct cpu_table cpu_ids[] __initdata = {
|
||||
{
|
||||
.idcode = EXYNOS4210_CPU_ID,
|
||||
.idmask = EXYNOS4_CPU_MASK,
|
||||
.map_io = exynos4_map_io,
|
||||
.init_clocks = exynos4_init_clocks,
|
||||
.init_uarts = exynos4_init_uarts,
|
||||
.init = exynos_init,
|
||||
.name = name_exynos4210,
|
||||
@ -83,7 +84,6 @@ static struct cpu_table cpu_ids[] __initdata = {
|
||||
.idcode = EXYNOS4212_CPU_ID,
|
||||
.idmask = EXYNOS4_CPU_MASK,
|
||||
.map_io = exynos4_map_io,
|
||||
.init_clocks = exynos4_init_clocks,
|
||||
.init_uarts = exynos4_init_uarts,
|
||||
.init = exynos_init,
|
||||
.name = name_exynos4212,
|
||||
@ -91,7 +91,6 @@ static struct cpu_table cpu_ids[] __initdata = {
|
||||
.idcode = EXYNOS4412_CPU_ID,
|
||||
.idmask = EXYNOS4_CPU_MASK,
|
||||
.map_io = exynos4_map_io,
|
||||
.init_clocks = exynos4_init_clocks,
|
||||
.init_uarts = exynos4_init_uarts,
|
||||
.init = exynos_init,
|
||||
.name = name_exynos4412,
|
||||
@ -99,7 +98,6 @@ static struct cpu_table cpu_ids[] __initdata = {
|
||||
.idcode = EXYNOS5250_SOC_ID,
|
||||
.idmask = EXYNOS5_SOC_MASK,
|
||||
.map_io = exynos5_map_io,
|
||||
.init_clocks = exynos5_init_clocks,
|
||||
.init = exynos_init,
|
||||
.name = name_exynos5250,
|
||||
}, {
|
||||
@ -256,11 +254,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
|
||||
.pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_SYSTIMER,
|
||||
.pfn = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_SYSRAM,
|
||||
.pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
|
||||
@ -368,6 +361,9 @@ static void __init exynos4_map_io(void)
|
||||
else
|
||||
iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
|
||||
|
||||
if (!IS_ENABLED(CONFIG_EXYNOS_ATAGS))
|
||||
return
|
||||
|
||||
/* initialize device information early */
|
||||
exynos4_default_sdhci0();
|
||||
exynos4_default_sdhci1();
|
||||
@ -402,43 +398,26 @@ static void __init exynos5_map_io(void)
|
||||
iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
|
||||
}
|
||||
|
||||
static void __init exynos4_init_clocks(int xtal)
|
||||
{
|
||||
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
|
||||
|
||||
s3c24xx_register_baseclocks(xtal);
|
||||
s5p_register_clocks(xtal);
|
||||
|
||||
if (soc_is_exynos4210())
|
||||
exynos4210_register_clocks();
|
||||
else if (soc_is_exynos4212() || soc_is_exynos4412())
|
||||
exynos4212_register_clocks();
|
||||
|
||||
exynos4_register_clocks();
|
||||
exynos4_setup_clocks();
|
||||
}
|
||||
|
||||
static void __init exynos5440_map_io(void)
|
||||
{
|
||||
iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
|
||||
}
|
||||
|
||||
static void __init exynos5_init_clocks(int xtal)
|
||||
void __init exynos_init_time(void)
|
||||
{
|
||||
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
|
||||
|
||||
/* EXYNOS5440 can support only common clock framework */
|
||||
|
||||
if (soc_is_exynos5440())
|
||||
return;
|
||||
|
||||
#ifdef CONFIG_SOC_EXYNOS5250
|
||||
s3c24xx_register_baseclocks(xtal);
|
||||
s5p_register_clocks(xtal);
|
||||
|
||||
exynos5_register_clocks();
|
||||
exynos5_setup_clocks();
|
||||
if (of_have_populated_dt()) {
|
||||
#ifdef CONFIG_OF
|
||||
of_clk_init(NULL);
|
||||
clocksource_of_init();
|
||||
#endif
|
||||
} else {
|
||||
/* todo: remove after migrating legacy E4 platforms to dt */
|
||||
#ifdef CONFIG_ARCH_EXYNOS4
|
||||
exynos4_clk_init(NULL);
|
||||
exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
|
||||
#endif
|
||||
mct_init();
|
||||
}
|
||||
}
|
||||
|
||||
void __init exynos4_init_irq(void)
|
||||
@ -570,6 +549,8 @@ static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
|
||||
s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
|
||||
}
|
||||
|
||||
|
||||
#ifdef CONFIG_EXYNOS_ATAGS
|
||||
static void __iomem *exynos_eint_base;
|
||||
|
||||
static DEFINE_SPINLOCK(eint_lock);
|
||||
@ -822,6 +803,7 @@ static int __init exynos_init_irq_eint(void)
|
||||
static const struct of_device_id exynos_pinctrl_ids[] = {
|
||||
{ .compatible = "samsung,exynos4210-pinctrl", },
|
||||
{ .compatible = "samsung,exynos4x12-pinctrl", },
|
||||
{ .compatible = "samsung,exynos5250-pinctrl", },
|
||||
};
|
||||
struct device_node *pctrl_np, *wkup_np;
|
||||
const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
|
||||
@ -875,3 +857,31 @@ static int __init exynos_init_irq_eint(void)
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(exynos_init_irq_eint);
|
||||
#endif
|
||||
|
||||
static struct resource exynos4_pmu_resource[] = {
|
||||
DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
|
||||
DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
|
||||
#if defined(CONFIG_SOC_EXYNOS4412)
|
||||
DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2),
|
||||
DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3),
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct platform_device exynos4_device_pmu = {
|
||||
.name = "arm-pmu",
|
||||
.num_resources = ARRAY_SIZE(exynos4_pmu_resource),
|
||||
.resource = exynos4_pmu_resource,
|
||||
};
|
||||
|
||||
static int __init exynos_armpmu_init(void)
|
||||
{
|
||||
if (!of_have_populated_dt()) {
|
||||
if (soc_is_exynos4210() || soc_is_exynos4212())
|
||||
exynos4_device_pmu.num_resources = 2;
|
||||
platform_device_register(&exynos4_device_pmu);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(exynos_armpmu_init);
|
||||
|
||||
@ -12,7 +12,11 @@
|
||||
#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
|
||||
#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
|
||||
|
||||
extern void exynos4_timer_init(void);
|
||||
#include <linux/of.h>
|
||||
|
||||
extern void mct_init(void);
|
||||
void exynos_init_time(void);
|
||||
extern unsigned long xxti_f, xusbxti_f;
|
||||
|
||||
struct map_desc;
|
||||
void exynos_init_io(struct map_desc *mach_desc, int size);
|
||||
@ -22,6 +26,10 @@ void exynos4_restart(char mode, const char *cmd);
|
||||
void exynos5_restart(char mode, const char *cmd);
|
||||
void exynos_init_late(void);
|
||||
|
||||
/* ToDo: remove these after migrating legacy exynos4 platforms to dt */
|
||||
void exynos4_clk_init(struct device_node *np);
|
||||
void exynos4_clk_register_fixed_ext(unsigned long, unsigned long);
|
||||
|
||||
#ifdef CONFIG_PM_GENERIC_DOMAINS
|
||||
int exynos_pm_late_initcall(void);
|
||||
#else
|
||||
|
||||
@ -20,6 +20,7 @@
|
||||
#include <asm/mach/irq.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#include <plat/devs.h>
|
||||
|
||||
|
||||
@ -30,8 +30,6 @@
|
||||
|
||||
/* For EXYNOS4 and EXYNOS5 */
|
||||
|
||||
#define EXYNOS_IRQ_MCT_LOCALTIMER IRQ_PPI(12)
|
||||
|
||||
#define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32)
|
||||
|
||||
/* For EXYNOS4 SoCs */
|
||||
@ -128,7 +126,7 @@
|
||||
#define EXYNOS4_IRQ_ADC1 IRQ_SPI(107)
|
||||
#define EXYNOS4_IRQ_PEN1 IRQ_SPI(108)
|
||||
#define EXYNOS4_IRQ_KEYPAD IRQ_SPI(109)
|
||||
#define EXYNOS4_IRQ_PMU IRQ_SPI(110)
|
||||
#define EXYNOS4_IRQ_POWER_PMU IRQ_SPI(110)
|
||||
#define EXYNOS4_IRQ_GPS IRQ_SPI(111)
|
||||
#define EXYNOS4_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
|
||||
#define EXYNOS4_IRQ_SLIMBUS IRQ_SPI(113)
|
||||
@ -136,6 +134,11 @@
|
||||
#define EXYNOS4_IRQ_TSI IRQ_SPI(115)
|
||||
#define EXYNOS4_IRQ_SATA IRQ_SPI(116)
|
||||
|
||||
#define EXYNOS4_IRQ_PMU COMBINER_IRQ(2, 2)
|
||||
#define EXYNOS4_IRQ_PMU_CPU1 COMBINER_IRQ(3, 2)
|
||||
#define EXYNOS4_IRQ_PMU_CPU2 COMBINER_IRQ(18, 2)
|
||||
#define EXYNOS4_IRQ_PMU_CPU3 COMBINER_IRQ(19, 2)
|
||||
|
||||
#define EXYNOS4_IRQ_TMU_TRIG0 COMBINER_IRQ(2, 4)
|
||||
#define EXYNOS4_IRQ_TMU_TRIG1 COMBINER_IRQ(3, 4)
|
||||
|
||||
@ -168,7 +171,10 @@
|
||||
#define EXYNOS4_IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1)
|
||||
#define EXYNOS4_IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2)
|
||||
|
||||
#define EXYNOS4_MAX_COMBINER_NR 16
|
||||
#define EXYNOS4210_MAX_COMBINER_NR 16
|
||||
#define EXYNOS4212_MAX_COMBINER_NR 18
|
||||
#define EXYNOS4412_MAX_COMBINER_NR 20
|
||||
#define EXYNOS4_MAX_COMBINER_NR EXYNOS4412_MAX_COMBINER_NR
|
||||
|
||||
#define EXYNOS4_IRQ_GPIO1_NR_GROUPS 16
|
||||
#define EXYNOS4_IRQ_GPIO2_NR_GROUPS 9
|
||||
@ -233,7 +239,6 @@
|
||||
#define IRQ_TC EXYNOS4_IRQ_PEN0
|
||||
|
||||
#define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD
|
||||
#define IRQ_PMU EXYNOS4_IRQ_PMU
|
||||
|
||||
#define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO
|
||||
#define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC
|
||||
@ -323,8 +328,6 @@
|
||||
#define EXYNOS5_IRQ_CEC IRQ_SPI(114)
|
||||
#define EXYNOS5_IRQ_SATA IRQ_SPI(115)
|
||||
|
||||
#define EXYNOS5_IRQ_MCT_L0 IRQ_SPI(120)
|
||||
#define EXYNOS5_IRQ_MCT_L1 IRQ_SPI(121)
|
||||
#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123)
|
||||
#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124)
|
||||
#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125)
|
||||
@ -419,8 +422,6 @@
|
||||
#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0)
|
||||
#define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3)
|
||||
#define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0)
|
||||
#define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1)
|
||||
@ -466,7 +467,10 @@
|
||||
#define IRQ_TIMER_BASE (IRQ_GPIO_END + 64)
|
||||
|
||||
/* Set the default NR_IRQS */
|
||||
#define EXYNOS_NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
|
||||
|
||||
#define NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
|
||||
#ifndef CONFIG_SPARSE_IRQ
|
||||
#define NR_IRQS EXYNOS_NR_IRQS
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_ARCH_IRQS_H */
|
||||
|
||||
@ -65,7 +65,6 @@
|
||||
#define EXYNOS5_PA_CMU 0x10010000
|
||||
|
||||
#define EXYNOS4_PA_SYSTIMER 0x10050000
|
||||
#define EXYNOS5_PA_SYSTIMER 0x101C0000
|
||||
|
||||
#define EXYNOS4_PA_WATCHDOG 0x10060000
|
||||
#define EXYNOS5_PA_WATCHDOG 0x101D0000
|
||||
|
||||
@ -1,53 +0,0 @@
|
||||
/* arch/arm/mach-exynos4/include/mach/regs-mct.h
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4 MCT configutation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_REGS_MCT_H
|
||||
#define __ASM_ARCH_REGS_MCT_H __FILE__
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
#define EXYNOS4_MCTREG(x) (S5P_VA_SYSTIMER + (x))
|
||||
|
||||
#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
|
||||
#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
|
||||
#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
|
||||
|
||||
#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
|
||||
#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
|
||||
#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
|
||||
|
||||
#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
|
||||
|
||||
#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
|
||||
#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
|
||||
#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
|
||||
|
||||
#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
|
||||
#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
|
||||
#define EXYNOS4_MCT_L_MASK (0xffffff00)
|
||||
|
||||
#define MCT_L_TCNTB_OFFSET (0x00)
|
||||
#define MCT_L_ICNTB_OFFSET (0x08)
|
||||
#define MCT_L_TCON_OFFSET (0x20)
|
||||
#define MCT_L_INT_CSTAT_OFFSET (0x30)
|
||||
#define MCT_L_INT_ENB_OFFSET (0x34)
|
||||
#define MCT_L_WSTAT_OFFSET (0x40)
|
||||
|
||||
#define MCT_G_TCON_START (1 << 8)
|
||||
#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
|
||||
#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
|
||||
|
||||
#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
|
||||
#define MCT_L_TCON_INT_START (1 << 1)
|
||||
#define MCT_L_TCON_TIMER_START (1 << 0)
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_MCT_H */
|
||||
@ -25,6 +25,7 @@
|
||||
#include <plat/regs-srom.h>
|
||||
#include <plat/sdhci.h>
|
||||
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include "common.h"
|
||||
@ -177,7 +178,6 @@ static void __init armlex4210_smsc911x_init(void)
|
||||
static void __init armlex4210_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(24000000);
|
||||
s3c24xx_init_uarts(armlex4210_uartcfgs,
|
||||
ARRAY_SIZE(armlex4210_uartcfgs));
|
||||
}
|
||||
@ -202,6 +202,6 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
|
||||
.map_io = armlex4210_map_io,
|
||||
.init_machine = armlex4210_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = exynos_init_time,
|
||||
.restart = exynos4_restart,
|
||||
MACHINE_END
|
||||
|
||||
@ -11,121 +11,26 @@
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/clocksource.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/mfc.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
/*
|
||||
* The following lookup table is used to override device names when devices
|
||||
* are registered from device tree. This is temporarily added to enable
|
||||
* device tree support addition for the Exynos4 architecture.
|
||||
*
|
||||
* For drivers that require platform data to be provided from the machine
|
||||
* file, a platform data pointer can also be supplied along with the
|
||||
* devices names. Usually, the platform data elements that cannot be parsed
|
||||
* from the device tree by the drivers (example: function pointers) are
|
||||
* supplied. But it should be noted that this is a temporary mechanism and
|
||||
* at some point, the drivers should be capable of parsing all the platform
|
||||
* data from the device tree.
|
||||
*/
|
||||
static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART0,
|
||||
"exynos4210-uart.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART1,
|
||||
"exynos4210-uart.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART2,
|
||||
"exynos4210-uart.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART3,
|
||||
"exynos4210-uart.3", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0),
|
||||
"exynos4-sdhci.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(1),
|
||||
"exynos4-sdhci.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(2),
|
||||
"exynos4-sdhci.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(3),
|
||||
"exynos4-sdhci.3", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0),
|
||||
"s3c2440-i2c.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(1),
|
||||
"s3c2440-i2c.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(2),
|
||||
"s3c2440-i2c.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(3),
|
||||
"s3c2440-i2c.3", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(4),
|
||||
"s3c2440-i2c.4", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(5),
|
||||
"s3c2440-i2c.5", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(6),
|
||||
"s3c2440-i2c.6", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(7),
|
||||
"s3c2440-i2c.7", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI0,
|
||||
"exynos4210-spi.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI1,
|
||||
"exynos4210-spi.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI2,
|
||||
"exynos4210-spi.2", NULL),
|
||||
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
|
||||
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
|
||||
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_MDMA1, "dma-pl330.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-tmu", EXYNOS4_PA_TMU,
|
||||
"exynos-tmu", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13620000,
|
||||
"exynos-sysmmu.0", NULL), /* MFC_L */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13630000,
|
||||
"exynos-sysmmu.1", NULL), /* MFC_R */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E20000,
|
||||
"exynos-sysmmu.2", NULL), /* TV */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A60000,
|
||||
"exynos-sysmmu.3", NULL), /* JPEG */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A30000,
|
||||
"exynos-sysmmu.4", NULL), /* ROTATOR */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A20000,
|
||||
"exynos-sysmmu.5", NULL), /* FIMC0 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A30000,
|
||||
"exynos-sysmmu.6", NULL), /* FIMC1 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A40000,
|
||||
"exynos-sysmmu.7", NULL), /* FIMC2 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A50000,
|
||||
"exynos-sysmmu.8", NULL), /* FIMC3 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A20000,
|
||||
"exynos-sysmmu.9", NULL), /* G2D(4210) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A40000,
|
||||
"exynos-sysmmu.9", NULL), /* G2D(4x12) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11E20000,
|
||||
"exynos-sysmmu.10", NULL), /* FIMD0 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12220000,
|
||||
"exynos-sysmmu.11", NULL), /* FIMD1(4210) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12260000,
|
||||
"exynos-sysmmu.12", NULL), /* IS0(4x12) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x122B0000,
|
||||
"exynos-sysmmu.13", NULL), /* IS1(4x12) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123B0000,
|
||||
"exynos-sysmmu.14", NULL), /* FIMC-LITE0(4x12) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123C0000,
|
||||
"exynos-sysmmu.15", NULL), /* FIMC-LITE1(4x12) */
|
||||
{},
|
||||
};
|
||||
|
||||
static void __init exynos4_dt_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(24000000);
|
||||
}
|
||||
|
||||
static void __init exynos4_dt_machine_init(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
exynos4_auxdata_lookup, NULL);
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
static char const *exynos4_dt_compat[] __initdata = {
|
||||
@ -135,6 +40,18 @@ static char const *exynos4_dt_compat[] __initdata = {
|
||||
NULL
|
||||
};
|
||||
|
||||
static void __init exynos4_reserve(void)
|
||||
{
|
||||
#ifdef CONFIG_S5P_DEV_MFC
|
||||
struct s5p_mfc_dt_meminfo mfc_mem;
|
||||
|
||||
/* Reserve memory for MFC only if it's available */
|
||||
mfc_mem.compatible = "samsung,mfc-v5";
|
||||
if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem))
|
||||
s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff,
|
||||
mfc_mem.lsize);
|
||||
#endif
|
||||
}
|
||||
DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
|
||||
/* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
|
||||
.smp = smp_ops(exynos_smp_ops),
|
||||
@ -142,7 +59,8 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
|
||||
.map_io = exynos4_dt_map_io,
|
||||
.init_machine = exynos4_dt_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = exynos_init_time,
|
||||
.dt_compat = exynos4_dt_compat,
|
||||
.restart = exynos4_restart,
|
||||
.reserve = exynos4_reserve,
|
||||
MACHINE_END
|
||||
|
||||
@ -11,151 +11,21 @@
|
||||
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/clocksource.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-pmu.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/mfc.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
/*
|
||||
* The following lookup table is used to override device names when devices
|
||||
* are registered from device tree. This is temporarily added to enable
|
||||
* device tree support addition for the EXYNOS5 architecture.
|
||||
*
|
||||
* For drivers that require platform data to be provided from the machine
|
||||
* file, a platform data pointer can also be supplied along with the
|
||||
* devices names. Usually, the platform data elements that cannot be parsed
|
||||
* from the device tree by the drivers (example: function pointers) are
|
||||
* supplied. But it should be noted that this is a temporary mechanism and
|
||||
* at some point, the drivers should be capable of parsing all the platform
|
||||
* data from the device tree.
|
||||
*/
|
||||
static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
|
||||
"exynos4210-uart.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
|
||||
"exynos4210-uart.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
|
||||
"exynos4210-uart.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
|
||||
"exynos4210-uart.3", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
|
||||
"s3c2440-i2c.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
|
||||
"s3c2440-i2c.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(2),
|
||||
"s3c2440-i2c.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(3),
|
||||
"s3c2440-i2c.3", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(4),
|
||||
"s3c2440-i2c.4", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(5),
|
||||
"s3c2440-i2c.5", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(6),
|
||||
"s3c2440-i2c.6", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(7),
|
||||
"s3c2440-i2c.7", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-hdmiphy-i2c", EXYNOS5_PA_IIC(8),
|
||||
"s3c2440-hdmiphy-i2c", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI0,
|
||||
"dw_mmc.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI1,
|
||||
"dw_mmc.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI2,
|
||||
"dw_mmc.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI3,
|
||||
"dw_mmc.3", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
|
||||
"exynos4210-spi.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
|
||||
"exynos4210-spi.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
|
||||
"exynos4210-spi.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-sata-ahci", 0x122F0000,
|
||||
"exynos5-sata", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-sata-phy", 0x12170000,
|
||||
"exynos5-sata-phy", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-sata-phy-i2c", 0x121D0000,
|
||||
"exynos5-sata-phy-i2c", NULL),
|
||||
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
|
||||
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
|
||||
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC0,
|
||||
"exynos-gsc.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC1,
|
||||
"exynos-gsc.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC2,
|
||||
"exynos-gsc.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3,
|
||||
"exynos-gsc.3", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
|
||||
"exynos5-hdmi", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-mixer", 0x14450000,
|
||||
"exynos5-mixer", NULL),
|
||||
OF_DEV_AUXDATA("samsung,mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5250-tmu", 0x10060000,
|
||||
"exynos-tmu", NULL),
|
||||
OF_DEV_AUXDATA("samsung,i2s-v5", 0x03830000,
|
||||
"samsung-i2s.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D60000,
|
||||
"samsung-i2s.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D70000,
|
||||
"samsung-i2s.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11210000,
|
||||
"exynos-sysmmu.0", "mfc"), /* MFC_L */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11200000,
|
||||
"exynos-sysmmu.1", "mfc"), /* MFC_R */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14650000,
|
||||
"exynos-sysmmu.2", NULL), /* TV */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11F20000,
|
||||
"exynos-sysmmu.3", "jpeg"), /* JPEG */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11D40000,
|
||||
"exynos-sysmmu.4", NULL), /* ROTATOR */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E80000,
|
||||
"exynos-sysmmu.5", "gscl"), /* GSCL0 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E90000,
|
||||
"exynos-sysmmu.6", "gscl"), /* GSCL1 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EA0000,
|
||||
"exynos-sysmmu.7", "gscl"), /* GSCL2 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EB0000,
|
||||
"exynos-sysmmu.8", "gscl"), /* GSCL3 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13260000,
|
||||
"exynos-sysmmu.9", NULL), /* FIMC-IS0 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x132C0000,
|
||||
"exynos-sysmmu.10", NULL), /* FIMC-IS1 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14640000,
|
||||
"exynos-sysmmu.11", NULL), /* FIMD1 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C40000,
|
||||
"exynos-sysmmu.12", NULL), /* FIMC-LITE0 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C50000,
|
||||
"exynos-sysmmu.13", NULL), /* FIMC-LITE1 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A60000,
|
||||
"exynos-sysmmu.14", NULL), /* G2D */
|
||||
{},
|
||||
};
|
||||
|
||||
static const struct of_dev_auxdata exynos5440_auxdata_lookup[] __initconst = {
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5440_PA_UART0,
|
||||
"exynos4210-uart.0", NULL),
|
||||
{},
|
||||
};
|
||||
|
||||
static void __init exynos5_dt_map_io(void)
|
||||
{
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
|
||||
exynos_init_io(NULL, 0);
|
||||
|
||||
if (of_flat_dt_is_compatible(root, "samsung,exynos5250"))
|
||||
s3c24xx_init_clocks(24000000);
|
||||
}
|
||||
|
||||
static void __init exynos5_dt_machine_init(void)
|
||||
@ -182,12 +52,7 @@ static void __init exynos5_dt_machine_init(void)
|
||||
}
|
||||
}
|
||||
|
||||
if (of_machine_is_compatible("samsung,exynos5250"))
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
exynos5250_auxdata_lookup, NULL);
|
||||
else if (of_machine_is_compatible("samsung,exynos5440"))
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
exynos5440_auxdata_lookup, NULL);
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
static char const *exynos5_dt_compat[] __initdata = {
|
||||
@ -216,7 +81,7 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
|
||||
.map_io = exynos5_dt_map_io,
|
||||
.init_machine = exynos5_dt_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = exynos_init_time,
|
||||
.dt_compat = exynos5_dt_compat,
|
||||
.restart = exynos5_restart,
|
||||
.reserve = exynos5_reserve,
|
||||
|
||||
@ -53,6 +53,7 @@
|
||||
#include <plat/fimc-core.h>
|
||||
#include <plat/camport.h>
|
||||
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include "common.h"
|
||||
@ -1330,8 +1331,9 @@ static struct platform_device *nuri_devices[] __initdata = {
|
||||
static void __init nuri_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(clk_xusbxti.rate);
|
||||
s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
|
||||
xxti_f = 0;
|
||||
xusbxti_f = 24000000;
|
||||
}
|
||||
|
||||
static void __init nuri_reserve(void)
|
||||
@ -1380,7 +1382,7 @@ MACHINE_START(NURI, "NURI")
|
||||
.map_io = nuri_map_io,
|
||||
.init_machine = nuri_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = exynos_init_time,
|
||||
.reserve = &nuri_reserve,
|
||||
.restart = exynos4_restart,
|
||||
MACHINE_END
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user