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net: phy: Add mdi(x) support in Microsemi PHYs driver
To connect two ports of the same configuration (MDI to MDI or MDI-X to MDI-X) with a 10/100/1000 Mbit/s connection, an Ethernet crossover cable is needed to cross over the transmit and receive signals in the cable, so that they are matched at the connector level. When connecting an MDI port to an MDI-X port a straight through cable is used while to connect two MDI ports or two MDI-X ports a crossover cable must be used. Conventionally MDI is used on end devices while MDI-X is used on hubs and switches Auto MDI-X automatically detects the required cable connection type and configures the connection appropriately, removing the need for crossover cables to interconnect switches or connecting PCs peer-to-peer. Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microsemi.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Raju Lakkaraju
David S. Miller
parent
1004ee6196
commit
233275ecf3
@ -27,6 +27,11 @@ enum rgmii_rx_clock_delay {
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/* Microsemi VSC85xx PHY registers */
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/* IEEE 802. Std Registers */
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#define MSCC_PHY_BYPASS_CONTROL 18
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#define DISABLE_HP_AUTO_MDIX_MASK 0x0080
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#define DISABLE_PAIR_SWAP_CORR_MASK 0x0020
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#define DISABLE_POLARITY_CORR_MASK 0x0010
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#define MSCC_PHY_EXT_PHY_CNTL_1 23
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#define MAC_IF_SELECTION_MASK 0x1800
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#define MAC_IF_SELECTION_GMII 0
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@ -44,12 +49,20 @@ enum rgmii_rx_clock_delay {
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#define EDGE_RATE_CNTL_POS 5
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#define EDGE_RATE_CNTL_MASK 0x00E0
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#define MSCC_PHY_DEV_AUX_CNTL 28
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#define HP_AUTO_MDIX_X_OVER_IND_MASK 0x2000
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#define MSCC_EXT_PAGE_ACCESS 31
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#define MSCC_PHY_PAGE_STANDARD 0x0000 /* Standard registers */
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#define MSCC_PHY_PAGE_EXTENDED 0x0001 /* Extended registers */
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#define MSCC_PHY_PAGE_EXTENDED_2 0x0002 /* Extended reg - page 2 */
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/* Extended Page 1 Registers */
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#define MSCC_PHY_EXT_MODE_CNTL 19
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#define FORCE_MDI_CROSSOVER_MASK 0x000C
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#define FORCE_MDI_CROSSOVER_MDIX 0x000C
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#define FORCE_MDI_CROSSOVER_MDI 0x0008
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#define MSCC_PHY_ACTIPHY_CNTL 20
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#define DOWNSHIFT_CNTL_MASK 0x001C
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#define DOWNSHIFT_EN 0x0010
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@ -110,6 +123,59 @@ static int vsc85xx_phy_page_set(struct phy_device *phydev, u8 page)
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return rc;
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}
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static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix)
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{
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u16 reg_val;
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reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL);
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if (reg_val & HP_AUTO_MDIX_X_OVER_IND_MASK)
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*mdix = ETH_TP_MDI_X;
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else
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*mdix = ETH_TP_MDI;
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return 0;
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}
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static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix)
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{
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int rc;
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u16 reg_val;
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reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL);
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if ((mdix == ETH_TP_MDI) || (mdix == ETH_TP_MDI_X)) {
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reg_val |= (DISABLE_PAIR_SWAP_CORR_MASK |
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DISABLE_POLARITY_CORR_MASK |
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DISABLE_HP_AUTO_MDIX_MASK);
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} else {
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reg_val &= ~(DISABLE_PAIR_SWAP_CORR_MASK |
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DISABLE_POLARITY_CORR_MASK |
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DISABLE_HP_AUTO_MDIX_MASK);
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}
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rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val);
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if (rc != 0)
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return rc;
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rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED);
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if (rc != 0)
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return rc;
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reg_val = phy_read(phydev, MSCC_PHY_EXT_MODE_CNTL);
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reg_val &= ~(FORCE_MDI_CROSSOVER_MASK);
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if (mdix == ETH_TP_MDI)
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reg_val |= FORCE_MDI_CROSSOVER_MDI;
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else if (mdix == ETH_TP_MDI_X)
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reg_val |= FORCE_MDI_CROSSOVER_MDIX;
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rc = phy_write(phydev, MSCC_PHY_EXT_MODE_CNTL, reg_val);
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if (rc != 0)
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return rc;
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rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
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if (rc != 0)
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return rc;
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return genphy_restart_aneg(phydev);
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}
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static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count)
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{
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int rc;
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@ -375,6 +441,7 @@ static int vsc85xx_default_config(struct phy_device *phydev)
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int rc;
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u16 reg_val;
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phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
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mutex_lock(&phydev->lock);
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rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
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if (rc != 0)
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@ -464,6 +531,28 @@ static int vsc85xx_config_intr(struct phy_device *phydev)
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return rc;
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}
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static int vsc85xx_config_aneg(struct phy_device *phydev)
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{
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int rc;
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rc = vsc85xx_mdix_set(phydev, phydev->mdix_ctrl);
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if (rc < 0)
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return rc;
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return genphy_config_aneg(phydev);
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}
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static int vsc85xx_read_status(struct phy_device *phydev)
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{
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int rc;
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rc = vsc85xx_mdix_get(phydev, &phydev->mdix);
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if (rc < 0)
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return rc;
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return genphy_read_status(phydev);
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}
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static int vsc85xx_probe(struct phy_device *phydev)
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{
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int rate_magic;
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@ -494,9 +583,9 @@ static struct phy_driver vsc85xx_driver[] = {
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.flags = PHY_HAS_INTERRUPT,
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.soft_reset = &genphy_soft_reset,
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.config_init = &vsc85xx_config_init,
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.config_aneg = &genphy_config_aneg,
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.config_aneg = &vsc85xx_config_aneg,
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.aneg_done = &genphy_aneg_done,
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.read_status = &genphy_read_status,
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.read_status = &vsc85xx_read_status,
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.ack_interrupt = &vsc85xx_ack_interrupt,
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.config_intr = &vsc85xx_config_intr,
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.suspend = &genphy_suspend,
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@ -515,9 +604,9 @@ static struct phy_driver vsc85xx_driver[] = {
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.flags = PHY_HAS_INTERRUPT,
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.soft_reset = &genphy_soft_reset,
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.config_init = &vsc85xx_config_init,
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.config_aneg = &genphy_config_aneg,
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.config_aneg = &vsc85xx_config_aneg,
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.aneg_done = &genphy_aneg_done,
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.read_status = &genphy_read_status,
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.read_status = &vsc85xx_read_status,
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.ack_interrupt = &vsc85xx_ack_interrupt,
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.config_intr = &vsc85xx_config_intr,
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.suspend = &genphy_suspend,
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@ -536,9 +625,9 @@ static struct phy_driver vsc85xx_driver[] = {
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.flags = PHY_HAS_INTERRUPT,
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.soft_reset = &genphy_soft_reset,
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.config_init = &vsc85xx_config_init,
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.config_aneg = &genphy_config_aneg,
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.config_aneg = &vsc85xx_config_aneg,
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.aneg_done = &genphy_aneg_done,
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.read_status = &genphy_read_status,
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.read_status = &vsc85xx_read_status,
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.ack_interrupt = &vsc85xx_ack_interrupt,
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.config_intr = &vsc85xx_config_intr,
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.suspend = &genphy_suspend,
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@ -557,9 +646,9 @@ static struct phy_driver vsc85xx_driver[] = {
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.flags = PHY_HAS_INTERRUPT,
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.soft_reset = &genphy_soft_reset,
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.config_init = &vsc85xx_config_init,
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.config_aneg = &genphy_config_aneg,
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.config_aneg = &vsc85xx_config_aneg,
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.aneg_done = &genphy_aneg_done,
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.read_status = &genphy_read_status,
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.read_status = &vsc85xx_read_status,
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.ack_interrupt = &vsc85xx_ack_interrupt,
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.config_intr = &vsc85xx_config_intr,
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.suspend = &genphy_suspend,
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