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clk: mxs: add mxs specific clocks
Add mxs specific clocks, pll, reference clock (PFD), integer divider and fractional divider. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
Shawn Guo
parent
d48b97b403
commit
23b5e15a29
5
drivers/clk/mxs/Makefile
Normal file
5
drivers/clk/mxs/Makefile
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@ -0,0 +1,5 @@
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#
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# Makefile for mxs specific clk
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#
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obj-y += clk.o clk-pll.o clk-ref.o clk-div.o clk-frac.o
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110
drivers/clk/mxs/clk-div.c
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110
drivers/clk/mxs/clk-div.c
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@ -0,0 +1,110 @@
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/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include "clk.h"
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/**
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* struct clk_div - mxs integer divider clock
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* @divider: the parent class
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* @ops: pointer to clk_ops of parent class
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* @reg: register address
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* @busy: busy bit shift
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*
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* The mxs divider clock is a subclass of basic clk_divider with an
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* addtional busy bit.
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*/
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struct clk_div {
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struct clk_divider divider;
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const struct clk_ops *ops;
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void __iomem *reg;
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u8 busy;
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};
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static inline struct clk_div *to_clk_div(struct clk_hw *hw)
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{
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struct clk_divider *divider = container_of(hw, struct clk_divider, hw);
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return container_of(divider, struct clk_div, divider);
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}
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static unsigned long clk_div_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_div *div = to_clk_div(hw);
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return div->ops->recalc_rate(&div->divider.hw, parent_rate);
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}
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static long clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_div *div = to_clk_div(hw);
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return div->ops->round_rate(&div->divider.hw, rate, prate);
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}
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static int clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_div *div = to_clk_div(hw);
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int ret;
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ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate);
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if (!ret)
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ret = mxs_clk_wait(div->reg, div->busy);
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return ret;
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}
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static struct clk_ops clk_div_ops = {
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.recalc_rate = clk_div_recalc_rate,
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.round_rate = clk_div_round_rate,
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.set_rate = clk_div_set_rate,
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};
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struct clk *mxs_clk_div(const char *name, const char *parent_name,
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void __iomem *reg, u8 shift, u8 width, u8 busy)
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{
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struct clk_div *div;
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struct clk *clk;
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struct clk_init_data init;
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div = kzalloc(sizeof(*div), GFP_KERNEL);
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if (!div)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &clk_div_ops;
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init.flags = CLK_SET_RATE_PARENT;
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init.parent_names = (parent_name ? &parent_name: NULL);
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init.num_parents = (parent_name ? 1 : 0);
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div->reg = reg;
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div->busy = busy;
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div->divider.reg = reg;
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div->divider.shift = shift;
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div->divider.width = width;
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div->divider.flags = CLK_DIVIDER_ONE_BASED;
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div->divider.lock = &mxs_lock;
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div->divider.hw.init = &init;
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div->ops = &clk_divider_ops;
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clk = clk_register(NULL, &div->divider.hw);
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if (IS_ERR(clk))
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kfree(div);
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return clk;
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}
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139
drivers/clk/mxs/clk-frac.c
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139
drivers/clk/mxs/clk-frac.c
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@ -0,0 +1,139 @@
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/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include "clk.h"
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/**
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* struct clk_frac - mxs fractional divider clock
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* @hw: clk_hw for the fractional divider clock
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* @reg: register address
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* @shift: the divider bit shift
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* @width: the divider bit width
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* @busy: busy bit shift
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*
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* The clock is an adjustable fractional divider with a busy bit to wait
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* when the divider is adjusted.
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*/
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struct clk_frac {
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struct clk_hw hw;
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void __iomem *reg;
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u8 shift;
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u8 width;
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u8 busy;
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};
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#define to_clk_frac(_hw) container_of(_hw, struct clk_frac, hw)
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static unsigned long clk_frac_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_frac *frac = to_clk_frac(hw);
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u32 div;
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div = readl_relaxed(frac->reg) >> frac->shift;
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div &= (1 << frac->width) - 1;
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return (parent_rate >> frac->width) * div;
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}
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static long clk_frac_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_frac *frac = to_clk_frac(hw);
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unsigned long parent_rate = *prate;
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u32 div;
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u64 tmp;
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if (rate > parent_rate)
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return -EINVAL;
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tmp = rate;
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tmp <<= frac->width;
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do_div(tmp, parent_rate);
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div = tmp;
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if (!div)
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return -EINVAL;
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return (parent_rate >> frac->width) * div;
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}
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static int clk_frac_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_frac *frac = to_clk_frac(hw);
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unsigned long flags;
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u32 div, val;
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u64 tmp;
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if (rate > parent_rate)
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return -EINVAL;
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tmp = rate;
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tmp <<= frac->width;
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do_div(tmp, parent_rate);
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div = tmp;
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if (!div)
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return -EINVAL;
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spin_lock_irqsave(&mxs_lock, flags);
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val = readl_relaxed(frac->reg);
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val &= ~(((1 << frac->width) - 1) << frac->shift);
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val |= div << frac->shift;
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writel_relaxed(val, frac->reg);
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spin_unlock_irqrestore(&mxs_lock, flags);
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return mxs_clk_wait(frac->reg, frac->busy);
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}
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static struct clk_ops clk_frac_ops = {
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.recalc_rate = clk_frac_recalc_rate,
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.round_rate = clk_frac_round_rate,
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.set_rate = clk_frac_set_rate,
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};
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struct clk *mxs_clk_frac(const char *name, const char *parent_name,
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void __iomem *reg, u8 shift, u8 width, u8 busy)
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{
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struct clk_frac *frac;
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struct clk *clk;
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struct clk_init_data init;
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frac = kzalloc(sizeof(*frac), GFP_KERNEL);
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if (!frac)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &clk_frac_ops;
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init.flags = CLK_SET_RATE_PARENT;
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init.parent_names = (parent_name ? &parent_name: NULL);
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init.num_parents = (parent_name ? 1 : 0);
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frac->reg = reg;
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frac->shift = shift;
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frac->width = width;
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frac->busy = busy;
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frac->hw.init = &init;
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clk = clk_register(NULL, &frac->hw);
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if (IS_ERR(clk))
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kfree(frac);
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return clk;
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}
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116
drivers/clk/mxs/clk-pll.c
Normal file
116
drivers/clk/mxs/clk-pll.c
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@ -0,0 +1,116 @@
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/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include "clk.h"
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/**
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* struct clk_pll - mxs pll clock
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* @hw: clk_hw for the pll
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* @base: base address of the pll
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* @power: the shift of power bit
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* @rate: the clock rate of the pll
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*
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* The mxs pll is a fixed rate clock with power and gate control,
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* and the shift of gate bit is always 31.
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*/
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struct clk_pll {
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struct clk_hw hw;
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void __iomem *base;
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u8 power;
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unsigned long rate;
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};
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#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
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static int clk_pll_prepare(struct clk_hw *hw)
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{
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struct clk_pll *pll = to_clk_pll(hw);
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writel_relaxed(1 << pll->power, pll->base + SET);
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udelay(10);
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return 0;
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}
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static void clk_pll_unprepare(struct clk_hw *hw)
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{
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struct clk_pll *pll = to_clk_pll(hw);
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writel_relaxed(1 << pll->power, pll->base + CLR);
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}
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static int clk_pll_enable(struct clk_hw *hw)
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{
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struct clk_pll *pll = to_clk_pll(hw);
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writel_relaxed(1 << 31, pll->base + CLR);
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return 0;
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}
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static void clk_pll_disable(struct clk_hw *hw)
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{
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struct clk_pll *pll = to_clk_pll(hw);
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writel_relaxed(1 << 31, pll->base + SET);
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}
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static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_pll *pll = to_clk_pll(hw);
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return pll->rate;
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}
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static const struct clk_ops clk_pll_ops = {
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.prepare = clk_pll_prepare,
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.unprepare = clk_pll_unprepare,
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.enable = clk_pll_enable,
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.disable = clk_pll_disable,
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.recalc_rate = clk_pll_recalc_rate,
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};
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struct clk *mxs_clk_pll(const char *name, const char *parent_name,
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void __iomem *base, u8 power, unsigned long rate)
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{
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struct clk_pll *pll;
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struct clk *clk;
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struct clk_init_data init;
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &clk_pll_ops;
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init.flags = 0;
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init.parent_names = (parent_name ? &parent_name: NULL);
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init.num_parents = (parent_name ? 1 : 0);
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pll->base = base;
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pll->rate = rate;
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pll->power = power;
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pll->hw.init = &init;
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clk = clk_register(NULL, &pll->hw);
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if (IS_ERR(clk))
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kfree(pll);
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return clk;
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}
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154
drivers/clk/mxs/clk-ref.c
Normal file
154
drivers/clk/mxs/clk-ref.c
Normal file
@ -0,0 +1,154 @@
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/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* The code contained herein is licensed under the GNU General Public
|
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* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include "clk.h"
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/**
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* struct clk_ref - mxs reference clock
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* @hw: clk_hw for the reference clock
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* @reg: register address
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* @idx: the index of the reference clock within the same register
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*
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* The mxs reference clock sources from pll. Every 4 reference clocks share
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* one register space, and @idx is used to identify them. Each reference
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* clock has a gate control and a fractional * divider. The rate is calculated
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* as pll rate * (18 / FRAC), where FRAC = 18 ~ 35.
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*/
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struct clk_ref {
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struct clk_hw hw;
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void __iomem *reg;
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u8 idx;
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};
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#define to_clk_ref(_hw) container_of(_hw, struct clk_ref, hw)
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static int clk_ref_enable(struct clk_hw *hw)
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{
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struct clk_ref *ref = to_clk_ref(hw);
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writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + CLR);
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return 0;
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}
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static void clk_ref_disable(struct clk_hw *hw)
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{
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struct clk_ref *ref = to_clk_ref(hw);
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writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + SET);
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}
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static unsigned long clk_ref_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_ref *ref = to_clk_ref(hw);
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u64 tmp = parent_rate;
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u8 frac = (readl_relaxed(ref->reg) >> (ref->idx * 8)) & 0x3f;
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tmp *= 18;
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do_div(tmp, frac);
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return tmp;
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}
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static long clk_ref_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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unsigned long parent_rate = *prate;
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u64 tmp = parent_rate;
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u8 frac;
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tmp = tmp * 18 + rate / 2;
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do_div(tmp, rate);
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frac = tmp;
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if (frac < 18)
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frac = 18;
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else if (frac > 35)
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frac = 35;
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tmp = parent_rate;
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tmp *= 18;
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do_div(tmp, frac);
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return tmp;
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}
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static int clk_ref_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_ref *ref = to_clk_ref(hw);
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unsigned long flags;
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u64 tmp = parent_rate;
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u32 val;
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u8 frac, shift = ref->idx * 8;
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tmp = tmp * 18 + rate / 2;
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do_div(tmp, rate);
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frac = tmp;
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if (frac < 18)
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frac = 18;
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else if (frac > 35)
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frac = 35;
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spin_lock_irqsave(&mxs_lock, flags);
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val = readl_relaxed(ref->reg);
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val &= ~(0x3f << shift);
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val |= frac << shift;
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writel_relaxed(val, ref->reg);
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spin_unlock_irqrestore(&mxs_lock, flags);
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return 0;
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}
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static const struct clk_ops clk_ref_ops = {
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||||
.enable = clk_ref_enable,
|
||||
.disable = clk_ref_disable,
|
||||
.recalc_rate = clk_ref_recalc_rate,
|
||||
.round_rate = clk_ref_round_rate,
|
||||
.set_rate = clk_ref_set_rate,
|
||||
};
|
||||
|
||||
struct clk *mxs_clk_ref(const char *name, const char *parent_name,
|
||||
void __iomem *reg, u8 idx)
|
||||
{
|
||||
struct clk_ref *ref;
|
||||
struct clk *clk;
|
||||
struct clk_init_data init;
|
||||
|
||||
ref = kzalloc(sizeof(*ref), GFP_KERNEL);
|
||||
if (!ref)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
init.name = name;
|
||||
init.ops = &clk_ref_ops;
|
||||
init.flags = 0;
|
||||
init.parent_names = (parent_name ? &parent_name: NULL);
|
||||
init.num_parents = (parent_name ? 1 : 0);
|
||||
|
||||
ref->reg = reg;
|
||||
ref->idx = idx;
|
||||
ref->hw.init = &init;
|
||||
|
||||
clk = clk_register(NULL, &ref->hw);
|
||||
if (IS_ERR(clk))
|
||||
kfree(ref);
|
||||
|
||||
return clk;
|
||||
}
|
||||
28
drivers/clk/mxs/clk.c
Normal file
28
drivers/clk/mxs/clk.c
Normal file
@ -0,0 +1,28 @@
|
||||
/*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/jiffies.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
DEFINE_SPINLOCK(mxs_lock);
|
||||
|
||||
int mxs_clk_wait(void __iomem *reg, u8 shift)
|
||||
{
|
||||
unsigned long timeout = jiffies + msecs_to_jiffies(10);
|
||||
|
||||
while (readl_relaxed(reg) & (1 << shift))
|
||||
if (time_after(jiffies, timeout))
|
||||
return -ETIMEDOUT;
|
||||
|
||||
return 0;
|
||||
}
|
||||
66
drivers/clk/mxs/clk.h
Normal file
66
drivers/clk/mxs/clk.h
Normal file
@ -0,0 +1,66 @@
|
||||
/*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#ifndef __MXS_CLK_H
|
||||
#define __MXS_CLK_H
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#define SET 0x4
|
||||
#define CLR 0x8
|
||||
|
||||
extern spinlock_t mxs_lock;
|
||||
|
||||
int mxs_clk_wait(void __iomem *reg, u8 shift);
|
||||
|
||||
struct clk *mxs_clk_pll(const char *name, const char *parent_name,
|
||||
void __iomem *base, u8 power, unsigned long rate);
|
||||
|
||||
struct clk *mxs_clk_ref(const char *name, const char *parent_name,
|
||||
void __iomem *reg, u8 idx);
|
||||
|
||||
struct clk *mxs_clk_div(const char *name, const char *parent_name,
|
||||
void __iomem *reg, u8 shift, u8 width, u8 busy);
|
||||
|
||||
struct clk *mxs_clk_frac(const char *name, const char *parent_name,
|
||||
void __iomem *reg, u8 shift, u8 width, u8 busy);
|
||||
|
||||
static inline struct clk *mxs_clk_fixed(const char *name, int rate)
|
||||
{
|
||||
return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
|
||||
}
|
||||
|
||||
static inline struct clk *mxs_clk_gate(const char *name,
|
||||
const char *parent_name, void __iomem *reg, u8 shift)
|
||||
{
|
||||
return clk_register_gate(NULL, name, parent_name, CLK_SET_RATE_PARENT,
|
||||
reg, shift, CLK_GATE_SET_TO_DISABLE,
|
||||
&mxs_lock);
|
||||
}
|
||||
|
||||
static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg,
|
||||
u8 shift, u8 width, const char **parent_names, int num_parents)
|
||||
{
|
||||
return clk_register_mux(NULL, name, parent_names, num_parents,
|
||||
CLK_SET_RATE_PARENT, reg, shift, width,
|
||||
0, &mxs_lock);
|
||||
}
|
||||
|
||||
static inline struct clk *mxs_clk_fixed_factor(const char *name,
|
||||
const char *parent_name, unsigned int mult, unsigned int div)
|
||||
{
|
||||
return clk_register_fixed_factor(NULL, name, parent_name,
|
||||
CLK_SET_RATE_PARENT, mult, div);
|
||||
}
|
||||
|
||||
#endif /* __MXS_CLK_H */
|
||||
Loading…
Reference in New Issue
Block a user