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mtd: mtk-nor: modify functions' name more generally
Since more and more Mediatek's SoC can use this driver to control spi-nor flash, functions' name with "mt8173_" is no longer properly. Replacing "mt8173_" with "mtk_" will be more accurate to describe these functions' usable scope. Signed-off-by: Guochun Mao <guochun.mao@mediatek.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
This commit is contained in:
Guochun Mao
Cyrille Pitchen
parent
a6e4836d69
commit
23bae78e8a
@ -110,7 +110,7 @@
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#define MTK_NOR_PRG_REG(n) (MTK_NOR_PRGDATA0_REG + 4 * (n))
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#define MTK_NOR_SHREG(n) (MTK_NOR_SHREG0_REG + 4 * (n))
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struct mt8173_nor {
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struct mtk_nor {
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struct spi_nor nor;
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struct device *dev;
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void __iomem *base; /* nor flash base address */
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@ -118,47 +118,47 @@ struct mt8173_nor {
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struct clk *nor_clk;
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};
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static void mt8173_nor_set_read_mode(struct mt8173_nor *mt8173_nor)
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static void mtk_nor_set_read_mode(struct mtk_nor *mtk_nor)
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{
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struct spi_nor *nor = &mt8173_nor->nor;
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struct spi_nor *nor = &mtk_nor->nor;
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switch (nor->read_proto) {
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case SNOR_PROTO_1_1_1:
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writeb(nor->read_opcode, mt8173_nor->base +
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writeb(nor->read_opcode, mtk_nor->base +
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MTK_NOR_PRGDATA3_REG);
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writeb(MTK_NOR_FAST_READ, mt8173_nor->base +
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writeb(MTK_NOR_FAST_READ, mtk_nor->base +
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MTK_NOR_CFG1_REG);
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break;
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case SNOR_PROTO_1_1_2:
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writeb(nor->read_opcode, mt8173_nor->base +
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writeb(nor->read_opcode, mtk_nor->base +
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MTK_NOR_PRGDATA3_REG);
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writeb(MTK_NOR_DUAL_READ_EN, mt8173_nor->base +
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writeb(MTK_NOR_DUAL_READ_EN, mtk_nor->base +
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MTK_NOR_DUAL_REG);
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break;
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case SNOR_PROTO_1_1_4:
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writeb(nor->read_opcode, mt8173_nor->base +
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writeb(nor->read_opcode, mtk_nor->base +
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MTK_NOR_PRGDATA4_REG);
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writeb(MTK_NOR_QUAD_READ_EN, mt8173_nor->base +
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writeb(MTK_NOR_QUAD_READ_EN, mtk_nor->base +
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MTK_NOR_DUAL_REG);
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break;
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default:
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writeb(MTK_NOR_DUAL_DISABLE, mt8173_nor->base +
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writeb(MTK_NOR_DUAL_DISABLE, mtk_nor->base +
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MTK_NOR_DUAL_REG);
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break;
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}
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}
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static int mt8173_nor_execute_cmd(struct mt8173_nor *mt8173_nor, u8 cmdval)
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static int mtk_nor_execute_cmd(struct mtk_nor *mtk_nor, u8 cmdval)
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{
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int reg;
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u8 val = cmdval & 0x1f;
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writeb(cmdval, mt8173_nor->base + MTK_NOR_CMD_REG);
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return readl_poll_timeout(mt8173_nor->base + MTK_NOR_CMD_REG, reg,
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writeb(cmdval, mtk_nor->base + MTK_NOR_CMD_REG);
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return readl_poll_timeout(mtk_nor->base + MTK_NOR_CMD_REG, reg,
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!(reg & val), 100, 10000);
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}
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static int mt8173_nor_do_tx_rx(struct mt8173_nor *mt8173_nor, u8 op,
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static int mtk_nor_do_tx_rx(struct mtk_nor *mtk_nor, u8 op,
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u8 *tx, int txlen, u8 *rx, int rxlen)
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{
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int len = 1 + txlen + rxlen;
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@ -167,26 +167,26 @@ static int mt8173_nor_do_tx_rx(struct mt8173_nor *mt8173_nor, u8 op,
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if (len > MTK_NOR_MAX_SHIFT)
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return -EINVAL;
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writeb(len * 8, mt8173_nor->base + MTK_NOR_CNT_REG);
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writeb(len * 8, mtk_nor->base + MTK_NOR_CNT_REG);
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/* start at PRGDATA5, go down to PRGDATA0 */
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idx = MTK_NOR_MAX_RX_TX_SHIFT - 1;
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/* opcode */
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writeb(op, mt8173_nor->base + MTK_NOR_PRG_REG(idx));
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writeb(op, mtk_nor->base + MTK_NOR_PRG_REG(idx));
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idx--;
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/* program TX data */
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for (i = 0; i < txlen; i++, idx--)
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writeb(tx[i], mt8173_nor->base + MTK_NOR_PRG_REG(idx));
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writeb(tx[i], mtk_nor->base + MTK_NOR_PRG_REG(idx));
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/* clear out rest of TX registers */
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while (idx >= 0) {
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writeb(0, mt8173_nor->base + MTK_NOR_PRG_REG(idx));
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writeb(0, mtk_nor->base + MTK_NOR_PRG_REG(idx));
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idx--;
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}
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ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PRG_CMD);
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ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PRG_CMD);
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if (ret)
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return ret;
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@ -195,20 +195,20 @@ static int mt8173_nor_do_tx_rx(struct mt8173_nor *mt8173_nor, u8 op,
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/* read out RX data */
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for (i = 0; i < rxlen; i++, idx--)
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rx[i] = readb(mt8173_nor->base + MTK_NOR_SHREG(idx));
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rx[i] = readb(mtk_nor->base + MTK_NOR_SHREG(idx));
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return 0;
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}
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/* Do a WRSR (Write Status Register) command */
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static int mt8173_nor_wr_sr(struct mt8173_nor *mt8173_nor, u8 sr)
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static int mtk_nor_wr_sr(struct mtk_nor *mtk_nor, u8 sr)
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{
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writeb(sr, mt8173_nor->base + MTK_NOR_PRGDATA5_REG);
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writeb(8, mt8173_nor->base + MTK_NOR_CNT_REG);
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return mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_WRSR_CMD);
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writeb(sr, mtk_nor->base + MTK_NOR_PRGDATA5_REG);
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writeb(8, mtk_nor->base + MTK_NOR_CNT_REG);
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return mtk_nor_execute_cmd(mtk_nor, MTK_NOR_WRSR_CMD);
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}
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static int mt8173_nor_write_buffer_enable(struct mt8173_nor *mt8173_nor)
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static int mtk_nor_write_buffer_enable(struct mtk_nor *mtk_nor)
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{
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u8 reg;
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@ -216,27 +216,27 @@ static int mt8173_nor_write_buffer_enable(struct mt8173_nor *mt8173_nor)
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* 0: pre-fetch buffer use for read
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* 1: pre-fetch buffer use for page program
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*/
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writel(MTK_NOR_WR_BUF_ENABLE, mt8173_nor->base + MTK_NOR_CFG2_REG);
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return readb_poll_timeout(mt8173_nor->base + MTK_NOR_CFG2_REG, reg,
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writel(MTK_NOR_WR_BUF_ENABLE, mtk_nor->base + MTK_NOR_CFG2_REG);
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return readb_poll_timeout(mtk_nor->base + MTK_NOR_CFG2_REG, reg,
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0x01 == (reg & 0x01), 100, 10000);
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}
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static int mt8173_nor_write_buffer_disable(struct mt8173_nor *mt8173_nor)
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static int mtk_nor_write_buffer_disable(struct mtk_nor *mtk_nor)
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{
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u8 reg;
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writel(MTK_NOR_WR_BUF_DISABLE, mt8173_nor->base + MTK_NOR_CFG2_REG);
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return readb_poll_timeout(mt8173_nor->base + MTK_NOR_CFG2_REG, reg,
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writel(MTK_NOR_WR_BUF_DISABLE, mtk_nor->base + MTK_NOR_CFG2_REG);
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return readb_poll_timeout(mtk_nor->base + MTK_NOR_CFG2_REG, reg,
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MTK_NOR_WR_BUF_DISABLE == (reg & 0x1), 100,
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10000);
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}
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static void mt8173_nor_set_addr_width(struct mt8173_nor *mt8173_nor)
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static void mtk_nor_set_addr_width(struct mtk_nor *mtk_nor)
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{
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u8 val;
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struct spi_nor *nor = &mt8173_nor->nor;
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struct spi_nor *nor = &mtk_nor->nor;
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val = readb(mt8173_nor->base + MTK_NOR_DUAL_REG);
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val = readb(mtk_nor->base + MTK_NOR_DUAL_REG);
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switch (nor->addr_width) {
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case 3:
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@ -246,115 +246,115 @@ static void mt8173_nor_set_addr_width(struct mt8173_nor *mt8173_nor)
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val |= MTK_NOR_4B_ADDR_EN;
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break;
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default:
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dev_warn(mt8173_nor->dev, "Unexpected address width %u.\n",
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dev_warn(mtk_nor->dev, "Unexpected address width %u.\n",
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nor->addr_width);
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break;
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}
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writeb(val, mt8173_nor->base + MTK_NOR_DUAL_REG);
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writeb(val, mtk_nor->base + MTK_NOR_DUAL_REG);
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}
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static void mt8173_nor_set_addr(struct mt8173_nor *mt8173_nor, u32 addr)
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static void mtk_nor_set_addr(struct mtk_nor *mtk_nor, u32 addr)
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{
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int i;
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mt8173_nor_set_addr_width(mt8173_nor);
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mtk_nor_set_addr_width(mtk_nor);
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for (i = 0; i < 3; i++) {
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writeb(addr & 0xff, mt8173_nor->base + MTK_NOR_RADR0_REG + i * 4);
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writeb(addr & 0xff, mtk_nor->base + MTK_NOR_RADR0_REG + i * 4);
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addr >>= 8;
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}
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/* Last register is non-contiguous */
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writeb(addr & 0xff, mt8173_nor->base + MTK_NOR_RADR3_REG);
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writeb(addr & 0xff, mtk_nor->base + MTK_NOR_RADR3_REG);
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}
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static ssize_t mt8173_nor_read(struct spi_nor *nor, loff_t from, size_t length,
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static ssize_t mtk_nor_read(struct spi_nor *nor, loff_t from, size_t length,
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u_char *buffer)
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{
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int i, ret;
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int addr = (int)from;
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u8 *buf = (u8 *)buffer;
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struct mt8173_nor *mt8173_nor = nor->priv;
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struct mtk_nor *mtk_nor = nor->priv;
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/* set mode for fast read mode ,dual mode or quad mode */
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mt8173_nor_set_read_mode(mt8173_nor);
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mt8173_nor_set_addr(mt8173_nor, addr);
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mtk_nor_set_read_mode(mtk_nor);
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mtk_nor_set_addr(mtk_nor, addr);
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for (i = 0; i < length; i++) {
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ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PIO_READ_CMD);
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ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PIO_READ_CMD);
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if (ret < 0)
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return ret;
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buf[i] = readb(mt8173_nor->base + MTK_NOR_RDATA_REG);
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buf[i] = readb(mtk_nor->base + MTK_NOR_RDATA_REG);
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}
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return length;
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}
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static int mt8173_nor_write_single_byte(struct mt8173_nor *mt8173_nor,
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static int mtk_nor_write_single_byte(struct mtk_nor *mtk_nor,
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int addr, int length, u8 *data)
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{
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int i, ret;
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mt8173_nor_set_addr(mt8173_nor, addr);
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mtk_nor_set_addr(mtk_nor, addr);
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for (i = 0; i < length; i++) {
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writeb(*data++, mt8173_nor->base + MTK_NOR_WDATA_REG);
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ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PIO_WR_CMD);
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writeb(*data++, mtk_nor->base + MTK_NOR_WDATA_REG);
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ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PIO_WR_CMD);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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static int mt8173_nor_write_buffer(struct mt8173_nor *mt8173_nor, int addr,
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static int mtk_nor_write_buffer(struct mtk_nor *mtk_nor, int addr,
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const u8 *buf)
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{
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int i, bufidx, data;
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mt8173_nor_set_addr(mt8173_nor, addr);
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mtk_nor_set_addr(mtk_nor, addr);
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bufidx = 0;
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for (i = 0; i < SFLASH_WRBUF_SIZE; i += 4) {
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data = buf[bufidx + 3]<<24 | buf[bufidx + 2]<<16 |
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buf[bufidx + 1]<<8 | buf[bufidx];
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bufidx += 4;
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writel(data, mt8173_nor->base + MTK_NOR_PP_DATA_REG);
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writel(data, mtk_nor->base + MTK_NOR_PP_DATA_REG);
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}
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return mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_WR_CMD);
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return mtk_nor_execute_cmd(mtk_nor, MTK_NOR_WR_CMD);
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}
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static ssize_t mt8173_nor_write(struct spi_nor *nor, loff_t to, size_t len,
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static ssize_t mtk_nor_write(struct spi_nor *nor, loff_t to, size_t len,
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const u_char *buf)
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{
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int ret;
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struct mt8173_nor *mt8173_nor = nor->priv;
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struct mtk_nor *mtk_nor = nor->priv;
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size_t i;
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ret = mt8173_nor_write_buffer_enable(mt8173_nor);
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ret = mtk_nor_write_buffer_enable(mtk_nor);
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if (ret < 0) {
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dev_warn(mt8173_nor->dev, "write buffer enable failed!\n");
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dev_warn(mtk_nor->dev, "write buffer enable failed!\n");
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return ret;
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}
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for (i = 0; i + SFLASH_WRBUF_SIZE <= len; i += SFLASH_WRBUF_SIZE) {
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ret = mt8173_nor_write_buffer(mt8173_nor, to, buf);
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ret = mtk_nor_write_buffer(mtk_nor, to, buf);
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if (ret < 0) {
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dev_err(mt8173_nor->dev, "write buffer failed!\n");
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dev_err(mtk_nor->dev, "write buffer failed!\n");
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return ret;
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}
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to += SFLASH_WRBUF_SIZE;
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buf += SFLASH_WRBUF_SIZE;
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}
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ret = mt8173_nor_write_buffer_disable(mt8173_nor);
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ret = mtk_nor_write_buffer_disable(mtk_nor);
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if (ret < 0) {
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dev_warn(mt8173_nor->dev, "write buffer disable failed!\n");
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dev_warn(mtk_nor->dev, "write buffer disable failed!\n");
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return ret;
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}
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if (i < len) {
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ret = mt8173_nor_write_single_byte(mt8173_nor, to,
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ret = mtk_nor_write_single_byte(mtk_nor, to,
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(int)(len - i), (u8 *)buf);
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if (ret < 0) {
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dev_err(mt8173_nor->dev, "write single byte failed!\n");
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dev_err(mtk_nor->dev, "write single byte failed!\n");
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return ret;
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}
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}
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@ -362,72 +362,72 @@ static ssize_t mt8173_nor_write(struct spi_nor *nor, loff_t to, size_t len,
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return len;
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}
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static int mt8173_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
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static int mtk_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
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{
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int ret;
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struct mt8173_nor *mt8173_nor = nor->priv;
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struct mtk_nor *mtk_nor = nor->priv;
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switch (opcode) {
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case SPINOR_OP_RDSR:
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ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_RDSR_CMD);
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ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_RDSR_CMD);
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if (ret < 0)
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return ret;
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if (len == 1)
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*buf = readb(mt8173_nor->base + MTK_NOR_RDSR_REG);
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*buf = readb(mtk_nor->base + MTK_NOR_RDSR_REG);
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else
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dev_err(mt8173_nor->dev, "len should be 1 for read status!\n");
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dev_err(mtk_nor->dev, "len should be 1 for read status!\n");
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break;
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default:
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ret = mt8173_nor_do_tx_rx(mt8173_nor, opcode, NULL, 0, buf, len);
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ret = mtk_nor_do_tx_rx(mtk_nor, opcode, NULL, 0, buf, len);
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break;
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}
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return ret;
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}
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static int mt8173_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
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static int mtk_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
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int len)
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{
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int ret;
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struct mt8173_nor *mt8173_nor = nor->priv;
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struct mtk_nor *mtk_nor = nor->priv;
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switch (opcode) {
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case SPINOR_OP_WRSR:
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/* We only handle 1 byte */
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ret = mt8173_nor_wr_sr(mt8173_nor, *buf);
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ret = mtk_nor_wr_sr(mtk_nor, *buf);
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break;
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default:
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ret = mt8173_nor_do_tx_rx(mt8173_nor, opcode, buf, len, NULL, 0);
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ret = mtk_nor_do_tx_rx(mtk_nor, opcode, buf, len, NULL, 0);
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if (ret)
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dev_warn(mt8173_nor->dev, "write reg failure!\n");
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dev_warn(mtk_nor->dev, "write reg failure!\n");
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break;
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}
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return ret;
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}
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static void mt8173_nor_disable_clk(struct mt8173_nor *mt8173_nor)
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static void mtk_nor_disable_clk(struct mtk_nor *mtk_nor)
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{
|
||||
clk_disable_unprepare(mt8173_nor->spi_clk);
|
||||
clk_disable_unprepare(mt8173_nor->nor_clk);
|
||||
clk_disable_unprepare(mtk_nor->spi_clk);
|
||||
clk_disable_unprepare(mtk_nor->nor_clk);
|
||||
}
|
||||
|
||||
static int mt8173_nor_enable_clk(struct mt8173_nor *mt8173_nor)
|
||||
static int mtk_nor_enable_clk(struct mtk_nor *mtk_nor)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(mt8173_nor->spi_clk);
|
||||
ret = clk_prepare_enable(mtk_nor->spi_clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_prepare_enable(mt8173_nor->nor_clk);
|
||||
ret = clk_prepare_enable(mtk_nor->nor_clk);
|
||||
if (ret) {
|
||||
clk_disable_unprepare(mt8173_nor->spi_clk);
|
||||
clk_disable_unprepare(mtk_nor->spi_clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_nor_init(struct mt8173_nor *mt8173_nor,
|
||||
static int mtk_nor_init(struct mtk_nor *mtk_nor,
|
||||
struct device_node *flash_node)
|
||||
{
|
||||
const struct spi_nor_hwcaps hwcaps = {
|
||||
@ -439,18 +439,18 @@ static int mtk_nor_init(struct mt8173_nor *mt8173_nor,
|
||||
struct spi_nor *nor;
|
||||
|
||||
/* initialize controller to accept commands */
|
||||
writel(MTK_NOR_ENABLE_SF_CMD, mt8173_nor->base + MTK_NOR_WRPROT_REG);
|
||||
writel(MTK_NOR_ENABLE_SF_CMD, mtk_nor->base + MTK_NOR_WRPROT_REG);
|
||||
|
||||
nor = &mt8173_nor->nor;
|
||||
nor->dev = mt8173_nor->dev;
|
||||
nor->priv = mt8173_nor;
|
||||
nor = &mtk_nor->nor;
|
||||
nor->dev = mtk_nor->dev;
|
||||
nor->priv = mtk_nor;
|
||||
spi_nor_set_flash_node(nor, flash_node);
|
||||
|
||||
/* fill the hooks to spi nor */
|
||||
nor->read = mt8173_nor_read;
|
||||
nor->read_reg = mt8173_nor_read_reg;
|
||||
nor->write = mt8173_nor_write;
|
||||
nor->write_reg = mt8173_nor_write_reg;
|
||||
nor->read = mtk_nor_read;
|
||||
nor->read_reg = mtk_nor_read_reg;
|
||||
nor->write = mtk_nor_write;
|
||||
nor->write_reg = mtk_nor_write_reg;
|
||||
nor->mtd.name = "mtk_nor";
|
||||
/* initialized with NULL */
|
||||
ret = spi_nor_scan(nor, NULL, &hwcaps);
|
||||
@ -465,34 +465,34 @@ static int mtk_nor_drv_probe(struct platform_device *pdev)
|
||||
struct device_node *flash_np;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
struct mt8173_nor *mt8173_nor;
|
||||
struct mtk_nor *mtk_nor;
|
||||
|
||||
if (!pdev->dev.of_node) {
|
||||
dev_err(&pdev->dev, "No DT found\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
mt8173_nor = devm_kzalloc(&pdev->dev, sizeof(*mt8173_nor), GFP_KERNEL);
|
||||
if (!mt8173_nor)
|
||||
mtk_nor = devm_kzalloc(&pdev->dev, sizeof(*mtk_nor), GFP_KERNEL);
|
||||
if (!mtk_nor)
|
||||
return -ENOMEM;
|
||||
platform_set_drvdata(pdev, mt8173_nor);
|
||||
platform_set_drvdata(pdev, mtk_nor);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
mt8173_nor->base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(mt8173_nor->base))
|
||||
return PTR_ERR(mt8173_nor->base);
|
||||
mtk_nor->base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(mtk_nor->base))
|
||||
return PTR_ERR(mtk_nor->base);
|
||||
|
||||
mt8173_nor->spi_clk = devm_clk_get(&pdev->dev, "spi");
|
||||
if (IS_ERR(mt8173_nor->spi_clk))
|
||||
return PTR_ERR(mt8173_nor->spi_clk);
|
||||
mtk_nor->spi_clk = devm_clk_get(&pdev->dev, "spi");
|
||||
if (IS_ERR(mtk_nor->spi_clk))
|
||||
return PTR_ERR(mtk_nor->spi_clk);
|
||||
|
||||
mt8173_nor->nor_clk = devm_clk_get(&pdev->dev, "sf");
|
||||
if (IS_ERR(mt8173_nor->nor_clk))
|
||||
return PTR_ERR(mt8173_nor->nor_clk);
|
||||
mtk_nor->nor_clk = devm_clk_get(&pdev->dev, "sf");
|
||||
if (IS_ERR(mtk_nor->nor_clk))
|
||||
return PTR_ERR(mtk_nor->nor_clk);
|
||||
|
||||
mt8173_nor->dev = &pdev->dev;
|
||||
mtk_nor->dev = &pdev->dev;
|
||||
|
||||
ret = mt8173_nor_enable_clk(mt8173_nor);
|
||||
ret = mtk_nor_enable_clk(mtk_nor);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
@ -503,20 +503,20 @@ static int mtk_nor_drv_probe(struct platform_device *pdev)
|
||||
ret = -ENODEV;
|
||||
goto nor_free;
|
||||
}
|
||||
ret = mtk_nor_init(mt8173_nor, flash_np);
|
||||
ret = mtk_nor_init(mtk_nor, flash_np);
|
||||
|
||||
nor_free:
|
||||
if (ret)
|
||||
mt8173_nor_disable_clk(mt8173_nor);
|
||||
mtk_nor_disable_clk(mtk_nor);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mtk_nor_drv_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct mt8173_nor *mt8173_nor = platform_get_drvdata(pdev);
|
||||
struct mtk_nor *mtk_nor = platform_get_drvdata(pdev);
|
||||
|
||||
mt8173_nor_disable_clk(mt8173_nor);
|
||||
mtk_nor_disable_clk(mtk_nor);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -524,18 +524,18 @@ static int mtk_nor_drv_remove(struct platform_device *pdev)
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int mtk_nor_suspend(struct device *dev)
|
||||
{
|
||||
struct mt8173_nor *mt8173_nor = dev_get_drvdata(dev);
|
||||
struct mtk_nor *mtk_nor = dev_get_drvdata(dev);
|
||||
|
||||
mt8173_nor_disable_clk(mt8173_nor);
|
||||
mtk_nor_disable_clk(mtk_nor);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_nor_resume(struct device *dev)
|
||||
{
|
||||
struct mt8173_nor *mt8173_nor = dev_get_drvdata(dev);
|
||||
struct mtk_nor *mtk_nor = dev_get_drvdata(dev);
|
||||
|
||||
return mt8173_nor_enable_clk(mt8173_nor);
|
||||
return mtk_nor_enable_clk(mtk_nor);
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops mtk_nor_dev_pm_ops = {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user