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ARM: mach-msm: hook special idle handlers to arm_pm_idle

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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: David Brown <davidb@codeaurora.org>
This commit is contained in:
Nicolas Pitre 2011-08-03 11:34:59 -04:00 committed by Nicolas Pitre
parent 4a3ea24405
commit 25eb433ab1
3 changed files with 53 additions and 37 deletions
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36
arch/arm/mach-msm/idle.S
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@ -1,36 +0,0 @@
/* arch/arm/mach-msm/include/mach/idle.S
*
* Idle processing for MSM7K - work around bugs with SWFI.
*
* Copyright (c) 2007 QUALCOMM Incorporated.
* Copyright (C) 2007 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
ENTRY(arch_idle)
#ifdef CONFIG_MSM7X00A_IDLE
mrc p15, 0, r1, c1, c0, 0 /* read current CR */
bic r0, r1, #(1 << 2) /* clear dcache bit */
bic r0, r0, #(1 << 12) /* clear icache bit */
mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */
mov r0, #0 /* prepare wfi value */
mcr p15, 0, r0, c7, c10, 0 /* flush the cache */
mcr p15, 0, r0, c7, c10, 4 /* memory barrier */
mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */
mcr p15, 0, r1, c1, c0, 0 /* restore d/i cache */
#endif
mov pc, lr

49
arch/arm/mach-msm/idle.c Normal file
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@ -0,0 +1,49 @@
/* arch/arm/mach-msm/idle.c
*
* Idle processing for MSM7K - work around bugs with SWFI.
*
* Copyright (c) 2007 QUALCOMM Incorporated.
* Copyright (C) 2007 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/init.h>
#include <asm/system.h>
static void msm_idle(void)
{
#ifdef CONFIG_MSM7X00A_IDLE
asm volatile (
"mrc p15, 0, r1, c1, c0, 0 /* read current CR */ \n\t"
"bic r0, r1, #(1 << 2) /* clear dcache bit */ \n\t"
"bic r0, r0, #(1 << 12) /* clear icache bit */ \n\t"
"mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */ \n\t"
"mov r0, #0 /* prepare wfi value */ \n\t"
"mcr p15, 0, r0, c7, c10, 0 /* flush the cache */ \n\t"
"mcr p15, 0, r0, c7, c10, 4 /* memory barrier */ \n\t"
"mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */ \n\t"
"mcr p15, 0, r1, c1, c0, 0 /* restore d/i cache */ \n\t"
: : : "r0","r1" );
#endif
}
static int __init msm_idle_init(void)
{
arm_pm_idle = msm_idle;
return 0;
}
arch_initcall(msm_idle_init);

5
arch/arm/mach-msm/include/mach/system.h
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@ -12,7 +12,10 @@
* GNU General Public License for more details.
*
*/
void arch_idle(void);
static inline void arch_idle(void)
{
cpu_do_idle();
}
/* low level hardware reset hook -- for example, hitting the
* PSHOLD line on the PMIC to hard reset the system