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drm/bridge: dw-hdmi: Add SCDC and TMDS Scrambling support
Add support for SCDC Setup for TMDS Clock > 3.4GHz and enable TMDS Scrambling when supported or mandatory. This patch also adds an helper to setup the control bit to support the high TMDS Bit Period/TMDS Clock-Period Ratio as required with TMDS Clock > 3.4GHz for HDMI2.0 3840x2160@60/50 modes. These changes were based on work done by Huicong Xu <xhc@rock-chips.com> and Nickey Yang <nickey.yang@rock-chips.com> to support HDMI2.0 modes on the Rockchip 4.4 BSP kernel at [1] [1] https://github.com/rockchip-linux/kernel/tree/release-4.4 Cc: Nickey Yang <nickey.yang@rock-chips.com> Cc: Huicong Xu <xhc@rock-chips.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Link: https://patchwork.freedesktop.org/patch/msgid/1549022873-40549-2-git-send-email-narmstrong@baylibre.com
This commit is contained in:
Neil Armstrong
Andrzej Hajda
parent
d60ea31a87
commit
264fce6cc2
@ -27,6 +27,7 @@
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_edid.h>
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#include <drm/drm_encoder_slave.h>
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#include <drm/drm_scdc_helper.h>
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#include <drm/drm_probe_helper.h>
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#include <drm/bridge/dw_hdmi.h>
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@ -43,6 +44,11 @@
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#define HDMI_EDID_LEN 512
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/* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
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#define SCDC_MIN_SOURCE_VERSION 0x1
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#define HDMI14_MAX_TMDSCLK 340000000
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enum hdmi_datamap {
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RGB444_8B = 0x01,
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RGB444_10B = 0x03,
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@ -1015,6 +1021,33 @@ void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
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}
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EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write);
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/*
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* HDMI2.0 Specifies the following procedure for High TMDS Bit Rates:
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* - The Source shall suspend transmission of the TMDS clock and data
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* - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it
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* from a 0 to a 1 or from a 1 to a 0
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* - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from
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* the time the TMDS_Bit_Clock_Ratio bit is written until resuming
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* transmission of TMDS clock and data
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*
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* To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio()
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* helper should called right before enabling the TMDS Clock and Data in
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* the PHY configuration callback.
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*/
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void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi)
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{
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unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mpixelclock;
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/* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
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if (hdmi->connector.display_info.hdmi.scdc.supported) {
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if (mtmdsclock > HDMI14_MAX_TMDSCLK)
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drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1);
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else
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drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0);
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}
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}
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EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio);
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static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
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{
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hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
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@ -1216,6 +1249,8 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi)
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dw_hdmi_phy_power_off(hdmi);
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dw_hdmi_set_high_tmds_clock_ratio(hdmi);
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/* Leave low power consumption mode by asserting SVSRET. */
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if (phy->has_svsret)
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dw_hdmi_phy_enable_svsret(hdmi, 1);
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@ -1237,6 +1272,10 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi)
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return ret;
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}
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/* Wait for resuming transmission of TMDS clock and data */
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if (mpixelclock > HDMI14_MAX_TMDSCLK)
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msleep(100);
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return dw_hdmi_phy_power_on(hdmi);
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}
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@ -1504,7 +1543,8 @@ static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
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static void hdmi_av_composer(struct dw_hdmi *hdmi,
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const struct drm_display_mode *mode)
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{
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u8 inv_val;
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u8 inv_val, bytes;
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struct drm_hdmi_info *hdmi_info = &hdmi->connector.display_info.hdmi;
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struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
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int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
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unsigned int vdisplay;
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@ -1514,7 +1554,9 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi,
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dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
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/* Set up HDMI_FC_INVIDCONF */
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inv_val = (hdmi->hdmi_data.hdcp_enable ?
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inv_val = (hdmi->hdmi_data.hdcp_enable ||
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vmode->mpixelclock > HDMI14_MAX_TMDSCLK ||
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hdmi_info->scdc.scrambling.low_rates ?
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HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
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HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
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@ -1563,6 +1605,45 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi,
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vsync_len /= 2;
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}
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/* Scrambling Control */
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if (hdmi_info->scdc.supported) {
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if (vmode->mpixelclock > HDMI14_MAX_TMDSCLK ||
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hdmi_info->scdc.scrambling.low_rates) {
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/*
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* HDMI2.0 Specifies the following procedure:
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* After the Source Device has determined that
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* SCDC_Present is set (=1), the Source Device should
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* write the accurate Version of the Source Device
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* to the Source Version field in the SCDCS.
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* Source Devices compliant shall set the
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* Source Version = 1.
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*/
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drm_scdc_readb(&hdmi->i2c->adap, SCDC_SINK_VERSION,
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&bytes);
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drm_scdc_writeb(&hdmi->i2c->adap, SCDC_SOURCE_VERSION,
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min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION));
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/* Enabled Scrambling in the Sink */
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drm_scdc_set_scrambling(&hdmi->i2c->adap, 1);
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/*
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* To activate the scrambler feature, you must ensure
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* that the quasi-static configuration bit
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* fc_invidconf.HDCP_keepout is set at configuration
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* time, before the required mc_swrstzreq.tmdsswrst_req
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* reset request is issued.
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*/
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hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
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HDMI_MC_SWRSTZ);
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hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
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} else {
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hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
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hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
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HDMI_MC_SWRSTZ);
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drm_scdc_set_scrambling(&hdmi->i2c->adap, 0);
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}
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}
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/* Set up horizontal active pixel width */
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hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
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hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
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@ -255,6 +255,7 @@
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#define HDMI_FC_MASK2 0x10DA
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#define HDMI_FC_POL2 0x10DB
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#define HDMI_FC_PRCONF 0x10E0
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#define HDMI_FC_SCRAMBLER_CTRL 0x10E1
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#define HDMI_FC_GMD_STAT 0x1100
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#define HDMI_FC_GMD_EN 0x1101
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@ -159,6 +159,7 @@ void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense);
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void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate);
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void dw_hdmi_audio_enable(struct dw_hdmi *hdmi);
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void dw_hdmi_audio_disable(struct dw_hdmi *hdmi);
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void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi);
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/* PHY configuration */
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void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address);
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