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https://github.com/FEX-Emu/linux.git
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Merge remote-tracking branches 'spi/fix/ep93xx', 'spi/fix/rockchip', 'spi/fix/sunxi' and 'spi/fix/ti-qspi' into spi-linus
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commit
2a9b27b326
@ -578,7 +578,7 @@ static int rockchip_spi_transfer_one(
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struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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int ret = 1;
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int ret = 0;
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struct rockchip_spi *rs = spi_master_get_devdata(master);
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WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
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@ -627,6 +627,8 @@ static int rockchip_spi_transfer_one(
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spi_enable_chip(rs, 1);
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ret = rockchip_spi_prepare_dma(rs);
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}
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/* successful DMA prepare means the transfer is in progress */
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ret = ret ? ret : 1;
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} else {
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spi_enable_chip(rs, 1);
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ret = rockchip_spi_pio_transfer(rs);
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@ -173,13 +173,17 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
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{
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struct sun4i_spi *sspi = spi_master_get_devdata(master);
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unsigned int mclk_rate, div, timeout;
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unsigned int start, end, tx_time;
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unsigned int tx_len = 0;
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int ret = 0;
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u32 reg;
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/* We don't support transfer larger than the FIFO */
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if (tfr->len > SUN4I_FIFO_DEPTH)
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return -EINVAL;
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return -EMSGSIZE;
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if (tfr->tx_buf && tfr->len >= SUN4I_FIFO_DEPTH)
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return -EMSGSIZE;
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reinit_completion(&sspi->done);
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sspi->tx_buf = tfr->tx_buf;
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@ -269,8 +273,12 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
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sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len));
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sun4i_spi_write(sspi, SUN4I_XMIT_CNT_REG, SUN4I_XMIT_CNT(tx_len));
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/* Fill the TX FIFO */
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sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);
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/*
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* Fill the TX FIFO
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* Filling the FIFO fully causes timeout for some reason
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* at least on spi2 on A10s
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*/
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sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH - 1);
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/* Enable the interrupts */
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sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, SUN4I_INT_CTL_TC);
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@ -279,9 +287,16 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
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reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
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sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH);
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tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U);
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start = jiffies;
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timeout = wait_for_completion_timeout(&sspi->done,
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msecs_to_jiffies(1000));
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msecs_to_jiffies(tx_time));
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end = jiffies;
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if (!timeout) {
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dev_warn(&master->dev,
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"%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
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dev_name(&spi->dev), tfr->len, tfr->speed_hz,
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jiffies_to_msecs(end - start), tx_time);
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ret = -ETIMEDOUT;
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goto out;
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}
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@ -160,6 +160,7 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
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{
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struct sun6i_spi *sspi = spi_master_get_devdata(master);
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unsigned int mclk_rate, div, timeout;
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unsigned int start, end, tx_time;
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unsigned int tx_len = 0;
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int ret = 0;
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u32 reg;
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@ -269,9 +270,16 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
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reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
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sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
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tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U);
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start = jiffies;
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timeout = wait_for_completion_timeout(&sspi->done,
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msecs_to_jiffies(1000));
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msecs_to_jiffies(tx_time));
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end = jiffies;
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if (!timeout) {
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dev_warn(&master->dev,
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"%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
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dev_name(&spi->dev), tfr->len, tfr->speed_hz,
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jiffies_to_msecs(end - start), tx_time);
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ret = -ETIMEDOUT;
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goto out;
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}
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@ -646,6 +646,13 @@ free_master:
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static int ti_qspi_remove(struct platform_device *pdev)
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{
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struct ti_qspi *qspi = platform_get_drvdata(pdev);
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int rc;
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rc = spi_master_suspend(qspi->master);
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if (rc)
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return rc;
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pm_runtime_put_sync(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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