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https://github.com/FEX-Emu/linux.git
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staging: tidspbridge: Remove unused defined constants
Remove defined constants not being used. Signed-off-by: Armando Uribe <x0095078@ti.com> Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
This commit is contained in:
parent
c378204afa
commit
2c36fac485
drivers/staging/tidspbridge
@ -24,9 +24,7 @@
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#define BRD_IDLE 0x1 /* Monitor Loaded, but suspended. */
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#define BRD_RUNNING 0x2 /* Monitor loaded, and executing. */
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#define BRD_UNKNOWN 0x3 /* Board state is indeterminate. */
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#define BRD_SYNCINIT 0x4
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#define BRD_LOADED 0x5
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#define BRD_LASTSTATE BRD_LOADED /* Set to highest legal board state. */
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#define BRD_SLEEP_TRANSITION 0x6 /* Sleep transition in progress */
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#define BRD_HIBERNATION 0x7 /* MPU initiated hibernation */
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#define BRD_RETENTION 0x8 /* Retention mode */
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@ -19,25 +19,12 @@
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#ifndef CFGDEFS_
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#define CFGDEFS_
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/* Maximum length of module search path. */
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#define CFG_MAXSEARCHPATHLEN 255
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/* Maximum length of general paths. */
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#define CFG_MAXPATH 255
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/* Host Resources: */
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#define CFG_MAXMEMREGISTERS 9
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#define CFG_MAXIOPORTS 20
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#define CFG_MAXIRQS 7
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#define CFG_MAXDMACHANNELS 7
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/* IRQ flag */
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#define CFG_IRQSHARED 0x01 /* IRQ can be shared */
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/* DSP Resources: */
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#define CFG_DSPMAXMEMTYPES 10
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#define CFG_DEFAULT_NUM_WINDOWS 1 /* We support only one window. */
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/* A platform-related device handle: */
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struct cfg_devnode;
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@ -22,9 +22,6 @@
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/* Channel id option. */
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#define CHNL_PICKFREE (~0UL) /* Let manager pick a free channel. */
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/* Channel manager limits: */
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#define CHNL_INITIOREQS 4 /* Default # of I/O requests. */
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/* Channel modes */
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#define CHNL_MODETODSP 0 /* Data streaming to the DSP. */
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#define CHNL_MODEFROMDSP 1 /* Data streaming from the DSP. */
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@ -39,12 +39,6 @@
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*/
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#define CHNL_PCPY 0 /* Proc-copy transport 0 */
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#define CHNL_MAXIRQ 0xff /* Arbitrarily large number. */
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/* The following modes are private: */
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#define CHNL_MODEUSEREVENT 0x1000 /* User provided the channel event. */
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#define CHNL_MODEMASK 0x1001
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/* Higher level channel states: */
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#define CHNL_STATEREADY 0 /* Channel ready for I/O. */
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#define CHNL_STATECANCEL 1 /* I/O was cancelled. */
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@ -56,13 +50,6 @@
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/* Types of channel class libraries: */
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#define CHNL_TYPESM 1 /* Shared memory driver. */
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#define CHNL_TYPEBM 2 /* Bus Mastering driver. */
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/* Max string length of channel I/O completion event name - change if needed */
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#define CHNL_MAXEVTNAMELEN 32
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/* Max memory pages lockable in CHNL_PrepareBuffer() - change if needed */
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#define CHNL_MAXLOCKPAGES 64
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/* Channel info. */
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struct chnl_info {
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@ -27,9 +27,6 @@
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#define COD_TRACEBEG "SYS_PUTCBEG"
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#define COD_TRACEEND "SYS_PUTCEND"
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#define COD_TRACECURPOS "BRIDGE_SYS_PUTC_current"
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#define COD_TRACESECT "trace"
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#define COD_TRACEBEGOLD "PUTCBEG"
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#define COD_TRACEENDOLD "PUTCEND"
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#define COD_NOLOAD DBLL_NOLOAD
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#define COD_SYMB DBLL_SYMB
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@ -31,9 +31,6 @@
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/* API return value and calling convention */
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#define DBAPI int
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/* Infinite time value for the utimeout parameter to DSPStream_Select() */
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#define DSP_FOREVER (-1)
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/* Maximum length of node name, used in dsp_ndbprops */
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#define DSP_MAXNAMELEN 32
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@ -74,16 +71,9 @@
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#define DSP_NODE_MIN_PRIORITY 1
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#define DSP_NODE_MAX_PRIORITY 15
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/* Pre-Defined Message Command Codes available to user: */
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#define DSP_RMSUSERCODESTART RMS_USER /* Start of RMS user cmd codes */
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/* end of user codes */
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#define DSP_RMSUSERCODEEND (RMS_USER + RMS_MAXUSERCODES);
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/* msg_ctrl contains SM buffer description */
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#define DSP_RMSBUFDESC RMS_BUFDESC
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/* Shared memory identifier for MEM segment named "SHMSEG0" */
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#define DSP_SHMSEG0 (u32)(-1)
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/* Processor ID numbers */
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#define DSP_UNIT 0
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#define IVA_UNIT 1
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@ -91,15 +81,6 @@
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#define DSPWORD unsigned char
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#define DSPWORDSIZE sizeof(DSPWORD)
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/* Power control enumerations */
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#define PROC_PWRCONTROL 0x8070
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#define PROC_PWRMGT_ENABLE (PROC_PWRCONTROL + 0x3)
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#define PROC_PWRMGT_DISABLE (PROC_PWRCONTROL + 0x4)
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/* Bridge Code Version */
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#define BRIDGE_VERSION_CODE 333
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#define MAX_PROFILES 16
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/* DSP chip type */
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@ -501,13 +482,6 @@ bit 15 - Output (writeable) buffer
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#define DSPPROCTYPE_C64 6410
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#define IVAPROCTYPE_ARM7 470
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#define REG_MGR_OBJECT 1
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#define REG_DRV_OBJECT 2
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/* registry */
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#define DRVOBJECT "DrvObject"
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#define MGROBJECT "MgrObject"
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/* Max registry path length. Also the max registry value length. */
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#define MAXREGPATHLENGTH 255
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@ -17,17 +17,6 @@
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#ifndef DBLDEFS_
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#define DBLDEFS_
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/*
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* Bit masks for dbl_flags.
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*/
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#define DBL_NOLOAD 0x0 /* Don't load symbols, code, or data */
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#define DBL_SYMB 0x1 /* load symbols */
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#define DBL_CODE 0x2 /* load code */
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#define DBL_DATA 0x4 /* load data */
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#define DBL_DYNAMIC 0x8 /* dynamic load */
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#define DBL_BSS 0x20 /* Unitialized section */
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#define DBL_MAXPATHLENGTH 255
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/*
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* ======== dbl_flags ========
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@ -26,7 +26,6 @@ struct deh_mgr;
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/* Magic code used to determine if DSP signaled exception. */
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#define DEH_BASE MBX_DEH_BASE
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#define DEH_USERS_BASE MBX_DEH_USERS_BASE
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#define DEH_LIMIT MBX_DEH_LIMIT
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#endif /* _DEHDEFS_H */
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@ -26,9 +26,6 @@
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#include <dspbridge/drvdefs.h>
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#include <linux/idr.h>
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#define DRV_ASSIGN 1
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#define DRV_RELEASE 0
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/* Provide the DSP Internal memory windows that can be accessed from L3 address
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* space */
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@ -38,23 +35,14 @@
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/* MEM1 is L2 RAM + L2 Cache space */
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#define OMAP_DSP_MEM1_BASE 0x5C7F8000
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#define OMAP_DSP_MEM1_SIZE 0x18000
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#define OMAP_DSP_GEM1_BASE 0x107F8000
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/* MEM2 is L1P RAM/CACHE space */
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#define OMAP_DSP_MEM2_BASE 0x5CE00000
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#define OMAP_DSP_MEM2_SIZE 0x8000
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#define OMAP_DSP_GEM2_BASE 0x10E00000
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/* MEM3 is L1D RAM/CACHE space */
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#define OMAP_DSP_MEM3_BASE 0x5CF04000
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#define OMAP_DSP_MEM3_SIZE 0x14000
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#define OMAP_DSP_GEM3_BASE 0x10F04000
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#define OMAP_IVA2_PRM_BASE 0x48306000
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#define OMAP_IVA2_PRM_SIZE 0x1000
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#define OMAP_IVA2_CM_BASE 0x48004000
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#define OMAP_IVA2_CM_SIZE 0x1000
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#define OMAP_PER_CM_BASE 0x48005000
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#define OMAP_PER_CM_SIZE 0x1000
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@ -68,9 +56,6 @@
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#define OMAP_DMMU_BASE 0x5D000000
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#define OMAP_DMMU_SIZE 0x1000
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#define OMAP_PRCM_VDD1_DOMAIN 1
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#define OMAP_PRCM_VDD2_DOMAIN 2
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/* GPP PROCESS CLEANUP Data structures */
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/* New structure (member of process context) abstracts NODE resource info */
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@ -37,12 +37,6 @@
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#include <dspbridge/iodefs.h>
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#include <dspbridge/msgdefs.h>
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/*
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* Any IOCTLS at or above this value are reserved for standard Bridge driver
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* interfaces.
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*/
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#define BRD_RESERVEDIOCTLBASE 0x8000
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/* Handle to Bridge driver's private device context. */
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struct bridge_dev_context;
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@ -20,8 +20,6 @@
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#if !defined _DSPDRV_H_
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#define _DSPDRV_H_
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#define MAX_DEV 10 /* Max support of 10 devices */
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/*
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* ======== dsp_deinit ========
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* Purpose:
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@ -31,9 +31,6 @@
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#define BRDIOCTL_CHNLREAD (BRDIOCTL_RESERVEDBASE + 0x10)
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#define BRDIOCTL_CHNLWRITE (BRDIOCTL_RESERVEDBASE + 0x20)
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#define BRDIOCTL_GETINTRCOUNT (BRDIOCTL_RESERVEDBASE + 0x30)
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#define BRDIOCTL_RESETINTRCOUNT (BRDIOCTL_RESERVEDBASE + 0x40)
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#define BRDIOCTL_INTERRUPTDSP (BRDIOCTL_RESERVEDBASE + 0x50)
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/* DMMU */
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#define BRDIOCTL_SETMMUCONFIG (BRDIOCTL_RESERVEDBASE + 0x60)
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/* PWR */
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@ -47,8 +44,6 @@
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#define BRDIOCTL_DEEPSLEEP (BRDIOCTL_PWRCONTROL + 0x0)
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#define BRDIOCTL_EMERGENCYSLEEP (BRDIOCTL_PWRCONTROL + 0x1)
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#define BRDIOCTL_WAKEUP (BRDIOCTL_PWRCONTROL + 0x2)
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#define BRDIOCTL_PWRENABLE (BRDIOCTL_PWRCONTROL + 0x3)
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#define BRDIOCTL_PWRDISABLE (BRDIOCTL_PWRCONTROL + 0x4)
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#define BRDIOCTL_CLK_CTRL (BRDIOCTL_PWRCONTROL + 0x7)
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/* DSP Initiated Hibernate */
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#define BRDIOCTL_PWR_HIBERNATE (BRDIOCTL_PWRCONTROL + 0x8)
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@ -46,8 +46,6 @@ struct dynamic_loader_initialize;
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* Option flags to modify the behavior of module loading
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*/
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#define DLOAD_INITBSS 0x1 /* initialize BSS sections to zero */
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#define DLOAD_BIGEND 0x2 /* require big-endian load module */
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#define DLOAD_LITTLE 0x4 /* require little-endian load module */
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/*****************************************************************************
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* Procedure dynamic_load_module
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@ -28,7 +28,6 @@
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#define IO_INPUT 0
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#define IO_OUTPUT 1
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#define IO_SERVICE 2
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#define IO_MAXSERVICE IO_SERVICE
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#ifdef CONFIG_TIDSPBRIDGE_DVFS
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/* The maximum number of OPPs that are supported */
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#ifndef IODEFS_
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#define IODEFS_
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#define IO_MAXIRQ 0xff /* Arbitrarily large number. */
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/* IO Objects: */
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struct io_mgr;
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@ -110,13 +110,7 @@
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#ifndef _MBX_SH_H
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#define _MBX_SH_H
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#define MBX_CLASS_MSK 0xFC00 /* Class bits are 10 thru 15 */
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#define MBX_VALUE_MSK 0x03FF /* Value is 0 thru 9 */
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#define MBX_DEH_CLASS 0x0000 /* DEH owns Mbx INTR */
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#define MBX_DDMA_CLASS 0x0400 /* DSP-DMA link drvr chnls owns INTR */
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#define MBX_PCPY_CLASS 0x0800 /* PROC-COPY " */
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#define MBX_ZCPY_CLASS 0x1000 /* ZERO-COPY " */
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#define MBX_PM_CLASS 0x2000 /* Power Management */
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#define MBX_DBG_CLASS 0x4000 /* For debugging purpose */
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@ -128,55 +122,21 @@
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#define MBX_DEH_USERS_BASE 0x100 /* 256 */
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#define MBX_DEH_LIMIT 0x3FF /* 1023 */
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#define MBX_DEH_RESET 0x101 /* DSP RESET (DEH) */
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#define MBX_DEH_EMMU 0X103 /*DSP MMU FAULT RECOVERY */
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/*
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* Link driver command/status codes.
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*/
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/* DSP-DMA */
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#define MBX_DDMA_NUMCHNLBITS 5 /* # chnl Id: # bits available */
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#define MBX_DDMA_CHNLSHIFT 0 /* # of bits to shift */
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#define MBX_DDMA_CHNLMSK 0x01F /* bits 0 thru 4 */
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#define MBX_DDMA_NUMBUFBITS 5 /* buffer index: # of bits avail */
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#define MBX_DDMA_BUFSHIFT (MBX_DDMA_NUMCHNLBITS + MBX_DDMA_CHNLSHIFT)
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#define MBX_DDMA_BUFMSK 0x3E0 /* bits 5 thru 9 */
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/* Zero-Copy */
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#define MBX_ZCPY_NUMCHNLBITS 5 /* # chnl Id: # bits available */
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#define MBX_ZCPY_CHNLSHIFT 0 /* # of bits to shift */
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#define MBX_ZCPY_CHNLMSK 0x01F /* bits 0 thru 4 */
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/* Power Management Commands */
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#define MBX_PM_DSPIDLE (MBX_PM_CLASS + 0x0)
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#define MBX_PM_DSPWAKEUP (MBX_PM_CLASS + 0x1)
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#define MBX_PM_EMERGENCYSLEEP (MBX_PM_CLASS + 0x2)
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#define MBX_PM_SLEEPUNTILRESTART (MBX_PM_CLASS + 0x3)
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#define MBX_PM_DSPGLOBALIDLE_OFF (MBX_PM_CLASS + 0x4)
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#define MBX_PM_DSPGLOBALIDLE_ON (MBX_PM_CLASS + 0x5)
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#define MBX_PM_SETPOINT_PRENOTIFY (MBX_PM_CLASS + 0x6)
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#define MBX_PM_SETPOINT_POSTNOTIFY (MBX_PM_CLASS + 0x7)
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#define MBX_PM_DSPRETN (MBX_PM_CLASS + 0x8)
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#define MBX_PM_DSPRETENTION (MBX_PM_CLASS + 0x8)
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#define MBX_PM_DSPHIBERNATE (MBX_PM_CLASS + 0x9)
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#define MBX_PM_HIBERNATE_EN (MBX_PM_CLASS + 0xA)
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#define MBX_PM_OPP_REQ (MBX_PM_CLASS + 0xB)
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#define MBX_PM_OPP_CHG (MBX_PM_CLASS + 0xC)
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#define MBX_PM_TYPE_MASK 0x0300
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#define MBX_PM_TYPE_PWR_CHNG 0x0100
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#define MBX_PM_TYPE_OPP_PRECHNG 0x0200
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#define MBX_PM_TYPE_OPP_POSTCHNG 0x0300
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#define MBX_PM_TYPE_OPP_MASK 0x0300
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#define MBX_PM_OPP_PRECHNG (MBX_PM_CLASS | MBX_PM_TYPE_OPP_PRECHNG)
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/* DSP to MPU */
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#define MBX_PM_OPP_CHNG(OPP) (MBX_PM_CLASS | MBX_PM_TYPE_OPP_PRECHNG | (OPP))
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#define MBX_PM_RET (MBX_PM_CLASS | MBX_PM_TYPE_PWR_CHNG | 0x0006)
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#define MBX_PM_HIB (MBX_PM_CLASS | MBX_PM_TYPE_PWR_CHNG | 0x0002)
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#define MBX_PM_OPP1 0
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#define MBX_PM_OPP2 1
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#define MBX_PM_OPP3 2
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#define MBX_PM_OPP4 3
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/* Bridge Debug Commands */
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#define MBX_DBG_SYSPRINTF (MBX_DBG_CLASS + 0x0)
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/* valid sleep command codes that can be sent by GPP via mailbox: */
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#define PWR_DEEPSLEEP MBX_PM_DSPIDLE
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#define PWR_EMERGENCYDEEPSLEEP MBX_PM_EMERGENCYSLEEP
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#define PWR_SLEEPUNTILRESTART MBX_PM_SLEEPUNTILRESTART
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#define PWR_WAKEUP MBX_PM_DSPWAKEUP
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#define PWR_AUTOENABLE MBX_PM_PWRENABLE
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#define PWR_AUTODISABLE MBX_PM_PWRDISABLE
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#define PWR_RETENTION MBX_PM_DSPRETN
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#endif /* PWR_SH_ */
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#include <dspbridge/rmstypes.h>
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/* Node Types: */
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#define RMS_TASK 1 /* Task node */
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#define RMS_DAIS 2 /* xDAIS socket node */
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#define RMS_MSG 3 /* Message node */
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/* Memory Types: */
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#define RMS_CODE 0 /* Program space */
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#define RMS_DATA 1 /* Data space */
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#define RMS_IO 2 /* I/O space */
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/* RM Server Command and Response Buffer Sizes: */
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#define RMS_COMMANDBUFSIZE 256 /* Size of command buffer */
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#define RMS_RESPONSEBUFSIZE 16 /* Size of response buffer */
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/* Pre-Defined Command/Response Codes: */
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#define RMS_EXIT 0x80000000 /* GPP->Node: shutdown */
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#define RMS_EXITACK 0x40000000 /* Node->GPP: ack shutdown */
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#define RMS_BUFDESC 0x20000000 /* Arg1 SM buf, Arg2 SM size */
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#define RMS_KILLTASK 0x10000000 /* GPP->Node: Kill Task */
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#define RMS_USER 0x0 /* Start of user-defined msg codes */
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#define RMS_MAXUSERCODES 0xfff /* Maximum user defined C/R Codes */
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/* RM Server RPC Command Structure: */
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struct rms_command {
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#ifndef STRMDEFS_
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#define STRMDEFS_
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#define STRM_MAXEVTNAMELEN 32
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struct strm_mgr;
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struct strm_object;
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@ -880,7 +880,7 @@ int dev_start_device(struct cfg_devnode *dev_node_obj)
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{
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struct dev_object *hdev_obj = NULL; /* handle to 'Bridge Device */
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/* Bridge driver filename */
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char bridge_file_name[CFG_MAXSEARCHPATHLEN] = "UMA";
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char *bridge_file_name = "UMA";
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int status;
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struct mgr_object *hmgr_obj = NULL;
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struct drv_data *drv_datap = dev_get_drvdata(bridge);
|
||||
|
Loading…
Reference in New Issue
Block a user