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clocksource: sh_cmt: Split static information from sh_cmt_device
Create a new sh_cmt_info structure to hold static information about the device model and reference that structure from the sh_cmt_device structure. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
This commit is contained in:
Laurent Pinchart
parent
f5ec9b194a
commit
2cda3ac49d
@ -37,6 +37,52 @@
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struct sh_cmt_device;
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/*
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* The CMT comes in 5 different identified flavours, depending not only on the
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* SoC but also on the particular instance. The following table lists the main
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* characteristics of those flavours.
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*
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* 16B 32B 32B-F 48B 48B-2
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* -----------------------------------------------------------------------------
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* Channels 2 1/4 1 6 2/8
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* Control Width 16 16 16 16 32
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* Counter Width 16 32 32 32/48 32/48
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* Shared Start/Stop Y Y Y Y N
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*
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* The 48-bit gen2 version has a per-channel start/stop register located in the
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* channel registers block. All other versions have a shared start/stop register
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* located in the global space.
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*
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* Note that CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
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* channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
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*/
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enum sh_cmt_model {
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SH_CMT_16BIT,
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SH_CMT_32BIT,
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SH_CMT_32BIT_FAST,
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SH_CMT_48BIT,
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SH_CMT_48BIT_GEN2,
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};
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struct sh_cmt_info {
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enum sh_cmt_model model;
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unsigned long width; /* 16 or 32 bit version of hardware block */
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unsigned long overflow_bit;
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unsigned long clear_bits;
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/* callbacks for CMSTR and CMCSR access */
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unsigned long (*read_control)(void __iomem *base, unsigned long offs);
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void (*write_control)(void __iomem *base, unsigned long offs,
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unsigned long value);
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/* callbacks for CMCNT and CMCOR access */
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unsigned long (*read_count)(void __iomem *base, unsigned long offs);
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void (*write_count)(void __iomem *base, unsigned long offs,
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unsigned long value);
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};
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struct sh_cmt_channel {
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struct sh_cmt_device *cmt;
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unsigned int index;
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@ -58,49 +104,16 @@ struct sh_cmt_channel {
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struct sh_cmt_device {
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struct platform_device *pdev;
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const struct sh_cmt_info *info;
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void __iomem *mapbase_ch;
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void __iomem *mapbase;
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struct clk *clk;
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struct sh_cmt_channel *channels;
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unsigned int num_channels;
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unsigned long width; /* 16 or 32 bit version of hardware block */
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unsigned long overflow_bit;
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unsigned long clear_bits;
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/* callbacks for CMSTR and CMCSR access */
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unsigned long (*read_control)(void __iomem *base, unsigned long offs);
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void (*write_control)(void __iomem *base, unsigned long offs,
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unsigned long value);
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/* callbacks for CMCNT and CMCOR access */
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unsigned long (*read_count)(void __iomem *base, unsigned long offs);
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void (*write_count)(void __iomem *base, unsigned long offs,
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unsigned long value);
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};
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/* Examples of supported CMT timer register layouts and I/O access widths:
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*
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* "16-bit counter and 16-bit control" as found on sh7263:
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* CMSTR 0xfffec000 16-bit
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* CMCSR 0xfffec002 16-bit
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* CMCNT 0xfffec004 16-bit
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* CMCOR 0xfffec006 16-bit
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*
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* "32-bit counter and 16-bit control" as found on sh7372, sh73a0, r8a7740:
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* CMSTR 0xffca0000 16-bit
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* CMCSR 0xffca0060 16-bit
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* CMCNT 0xffca0064 32-bit
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* CMCOR 0xffca0068 32-bit
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*
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* "32-bit counter and 32-bit control" as found on r8a73a4 and r8a7790:
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* CMSTR 0xffca0500 32-bit
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* CMCSR 0xffca0510 32-bit
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* CMCNT 0xffca0514 32-bit
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* CMCOR 0xffca0518 32-bit
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*/
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static unsigned long sh_cmt_read16(void __iomem *base, unsigned long offs)
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{
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return ioread16(base + (offs << 1));
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@ -123,47 +136,100 @@ static void sh_cmt_write32(void __iomem *base, unsigned long offs,
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iowrite32(value, base + (offs << 2));
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}
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static const struct sh_cmt_info sh_cmt_info[] = {
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[SH_CMT_16BIT] = {
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.model = SH_CMT_16BIT,
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.width = 16,
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.overflow_bit = 0x80,
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.clear_bits = ~0x80,
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.read_control = sh_cmt_read16,
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.write_control = sh_cmt_write16,
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.read_count = sh_cmt_read16,
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.write_count = sh_cmt_write16,
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},
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[SH_CMT_32BIT] = {
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.model = SH_CMT_32BIT,
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.width = 32,
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.overflow_bit = 0x8000,
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.clear_bits = ~0xc000,
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.read_control = sh_cmt_read16,
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.write_control = sh_cmt_write16,
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.read_count = sh_cmt_read32,
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.write_count = sh_cmt_write32,
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},
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[SH_CMT_32BIT_FAST] = {
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.model = SH_CMT_32BIT_FAST,
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.width = 32,
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.overflow_bit = 0x8000,
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.clear_bits = ~0xc000,
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.read_control = sh_cmt_read16,
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.write_control = sh_cmt_write16,
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.read_count = sh_cmt_read32,
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.write_count = sh_cmt_write32,
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},
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[SH_CMT_48BIT] = {
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.model = SH_CMT_48BIT,
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.width = 32,
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.overflow_bit = 0x8000,
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.clear_bits = ~0xc000,
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.read_control = sh_cmt_read32,
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.write_control = sh_cmt_write32,
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.read_count = sh_cmt_read32,
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.write_count = sh_cmt_write32,
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},
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[SH_CMT_48BIT_GEN2] = {
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.model = SH_CMT_48BIT_GEN2,
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.width = 32,
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.overflow_bit = 0x8000,
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.clear_bits = ~0xc000,
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.read_control = sh_cmt_read32,
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.write_control = sh_cmt_write32,
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.read_count = sh_cmt_read32,
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.write_count = sh_cmt_write32,
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},
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};
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#define CMCSR 0 /* channel register */
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#define CMCNT 1 /* channel register */
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#define CMCOR 2 /* channel register */
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static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_channel *ch)
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{
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return ch->cmt->read_control(ch->cmt->mapbase, 0);
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return ch->cmt->info->read_control(ch->cmt->mapbase, 0);
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}
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static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_channel *ch)
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{
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return ch->cmt->read_control(ch->base, CMCSR);
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return ch->cmt->info->read_control(ch->base, CMCSR);
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}
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static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_channel *ch)
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{
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return ch->cmt->read_count(ch->base, CMCNT);
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return ch->cmt->info->read_count(ch->base, CMCNT);
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}
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static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch,
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unsigned long value)
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{
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ch->cmt->write_control(ch->cmt->mapbase, 0, value);
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ch->cmt->info->write_control(ch->cmt->mapbase, 0, value);
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}
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static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch,
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unsigned long value)
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{
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ch->cmt->write_control(ch->base, CMCSR, value);
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ch->cmt->info->write_control(ch->base, CMCSR, value);
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}
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static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch,
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unsigned long value)
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{
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ch->cmt->write_count(ch->base, CMCNT, value);
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ch->cmt->info->write_count(ch->base, CMCNT, value);
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}
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static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch,
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unsigned long value)
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{
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ch->cmt->write_count(ch->base, CMCOR, value);
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ch->cmt->info->write_count(ch->base, CMCOR, value);
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}
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static unsigned long sh_cmt_get_counter(struct sh_cmt_channel *ch,
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@ -172,7 +238,7 @@ static unsigned long sh_cmt_get_counter(struct sh_cmt_channel *ch,
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unsigned long v1, v2, v3;
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int o1, o2;
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o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->overflow_bit;
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o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
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/* Make sure the timer value is stable. Stolen from acpi_pm.c */
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do {
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@ -180,7 +246,7 @@ static unsigned long sh_cmt_get_counter(struct sh_cmt_channel *ch,
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v1 = sh_cmt_read_cmcnt(ch);
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v2 = sh_cmt_read_cmcnt(ch);
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v3 = sh_cmt_read_cmcnt(ch);
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o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->overflow_bit;
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o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
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} while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
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|| (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
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@ -227,7 +293,7 @@ static int sh_cmt_enable(struct sh_cmt_channel *ch, unsigned long *rate)
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sh_cmt_start_stop_ch(ch, 0);
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/* configure channel, periodic mode and maximum timeout */
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if (ch->cmt->width == 16) {
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if (ch->cmt->info->width == 16) {
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*rate = clk_get_rate(ch->cmt->clk) / 512;
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sh_cmt_write_cmcsr(ch, 0x43);
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} else {
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@ -405,7 +471,8 @@ static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
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struct sh_cmt_channel *ch = dev_id;
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/* clear flags */
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sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) & ch->cmt->clear_bits);
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sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) &
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ch->cmt->info->clear_bits);
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/* update clock source counter to begin with if enabled
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* the wrap flag should be cleared by the timer specific
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@ -719,10 +786,10 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
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return irq;
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}
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if (cmt->width == (sizeof(ch->max_match_value) * 8))
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if (cmt->info->width == (sizeof(ch->max_match_value) * 8))
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ch->max_match_value = ~0;
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else
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ch->max_match_value = (1 << cmt->width) - 1;
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ch->max_match_value = (1 << cmt->info->width) - 1;
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ch->match_value = ch->max_match_value;
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raw_spin_lock_init(&ch->lock);
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@ -800,28 +867,13 @@ static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
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if (ret < 0)
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goto err3;
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if (res2 && (resource_size(res2) == 4)) {
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/* assume both CMSTR and CMCSR to be 32-bit */
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cmt->read_control = sh_cmt_read32;
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cmt->write_control = sh_cmt_write32;
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} else {
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cmt->read_control = sh_cmt_read16;
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cmt->write_control = sh_cmt_write16;
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}
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if (resource_size(res) == 6) {
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cmt->width = 16;
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cmt->read_count = sh_cmt_read16;
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cmt->write_count = sh_cmt_write16;
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cmt->overflow_bit = 0x80;
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cmt->clear_bits = ~0x80;
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} else {
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cmt->width = 32;
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cmt->read_count = sh_cmt_read32;
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cmt->write_count = sh_cmt_write32;
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cmt->overflow_bit = 0x8000;
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cmt->clear_bits = ~0xc000;
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}
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/* identify the model based on the resources */
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if (resource_size(res) == 6)
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cmt->info = &sh_cmt_info[SH_CMT_16BIT];
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else if (res2 && (resource_size(res2) == 4))
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cmt->info = &sh_cmt_info[SH_CMT_48BIT_GEN2];
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else
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cmt->info = &sh_cmt_info[SH_CMT_32BIT];
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cmt->channels = kzalloc(sizeof(*cmt->channels), GFP_KERNEL);
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if (cmt->channels == NULL) {
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