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net: hns3: Fix initialization when cmd is not supported

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When ae_dev doesn't support DCB, rx_priv_wl_config,
common_thrd_config and tm_qs_bp_cfg can't be called, otherwise
cmd return fail, which causes the hclge module initialization
process to fail.
This patch fix it by adding a DCB capability flag to check if
the ae_dev support DCB.

Fixes: 46a3df9f9718 ("net: hns3: Add HNS3 Acceleration Engine & Compatibility Layer Support")
Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Yunsheng Lin 2017-09-20 18:52:51 +08:00 committed by David S. Miller
parent e92a084379
commit 2daf4a6536
4 changed files with 31 additions and 16 deletions
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7
drivers/net/ethernet/hisilicon/hns3/hnae3.h
View File

@ -50,10 +50,17 @@
#define HNAE3_DEV_INITED_B 0x0
#define HNAE3_DEV_SUPPORT_ROCE_B 0x1
#define HNAE3_DEV_SUPPORT_DCB_B 0x2
#define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) |\
BIT(HNAE3_DEV_SUPPORT_ROCE_B))
#define hnae3_dev_roce_supported(hdev) \
hnae_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)
#define hnae3_dev_dcb_supported(hdev) \
hnae_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_DCB_B)
#define ring_ptr_move_fw(ring, p) \
((ring)->p = ((ring)->p + 1) % (ring)->desc_num)
#define ring_ptr_move_bw(ring, p) \

26
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
View File

@ -1772,18 +1772,22 @@ int hclge_buffer_alloc(struct hclge_dev *hdev)
return ret;
}
ret = hclge_rx_priv_wl_config(hdev);
if (ret) {
dev_err(&hdev->pdev->dev,
"could not configure rx private waterline %d\n", ret);
return ret;
}
if (hnae3_dev_dcb_supported(hdev)) {
ret = hclge_rx_priv_wl_config(hdev);
if (ret) {
dev_err(&hdev->pdev->dev,
"could not configure rx private waterline %d\n",
ret);
return ret;
}
ret = hclge_common_thrd_config(hdev);
if (ret) {
dev_err(&hdev->pdev->dev,
"could not configure common threshold %d\n", ret);
return ret;
ret = hclge_common_thrd_config(hdev);
if (ret) {
dev_err(&hdev->pdev->dev,
"could not configure common threshold %d\n",
ret);
return ret;
}
}
ret = hclge_common_wl_config(hdev);

4
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
View File

@ -976,6 +976,10 @@ int hclge_pause_setup_hw(struct hclge_dev *hdev)
if (ret)
return ret;
/* Only DCB-supported dev supports qset back pressure setting */
if (!hnae3_dev_dcb_supported(hdev))
return 0;
for (i = 0; i < hdev->tm_info.num_tc; i++) {
ret = hclge_tm_qs_bp_cfg(hdev, i);
if (ret)

10
drivers/net/ethernet/hisilicon/hns3/hns3pf/hns3_enet.c
View File

@ -42,15 +42,15 @@ static const struct pci_device_id hns3_pci_tbl[] = {
{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
BIT(HNAE3_DEV_SUPPORT_ROCE_B)},
HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
BIT(HNAE3_DEV_SUPPORT_ROCE_B)},
HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
BIT(HNAE3_DEV_SUPPORT_ROCE_B)},
HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
BIT(HNAE3_DEV_SUPPORT_ROCE_B)},
HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
BIT(HNAE3_DEV_SUPPORT_ROCE_B)},
HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
/* required last entry */
{0, }
};