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KVM: arm/arm64: vgic: Implement support for userspace access
Read and write of some registers like ISPENDR and ICPENDR from userspace requires special handling when compared to guest access for these registers. Refer to Documentation/virtual/kvm/devices/arm-vgic-v3.txt for handling of ISPENDR, ICPENDR registers handling. Add infrastructure to support guest and userspace read and write for the required registers Also moved vgic_uaccess from vgic-mmio-v2.c to vgic-mmio.c Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Vijaya Kumar K
Marc Zyngier
parent
10f92c4c53
commit
2df903a89a
@ -407,31 +407,6 @@ int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr)
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return -ENXIO;
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}
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/*
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* When userland tries to access the VGIC register handlers, we need to
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* create a usable struct vgic_io_device to be passed to the handlers and we
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* have to set up a buffer similar to what would have happened if a guest MMIO
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* access occurred, including doing endian conversions on BE systems.
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*/
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static int vgic_uaccess(struct kvm_vcpu *vcpu, struct vgic_io_device *dev,
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bool is_write, int offset, u32 *val)
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{
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unsigned int len = 4;
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u8 buf[4];
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int ret;
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if (is_write) {
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vgic_data_host_to_mmio_bus(buf, len, *val);
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ret = kvm_io_gic_ops.write(vcpu, &dev->dev, offset, len, buf);
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} else {
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ret = kvm_io_gic_ops.read(vcpu, &dev->dev, offset, len, buf);
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if (!ret)
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*val = vgic_data_mmio_bus_to_host(buf, len);
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}
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return ret;
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}
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int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
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int offset, u32 *val)
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{
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@ -207,6 +207,60 @@ static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu,
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return 0;
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}
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static unsigned long vgic_v3_uaccess_read_pending(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
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u32 value = 0;
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int i;
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/*
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* pending state of interrupt is latched in pending_latch variable.
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* Userspace will save and restore pending state and line_level
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* separately.
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* Refer to Documentation/virtual/kvm/devices/arm-vgic-v3.txt
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* for handling of ISPENDR and ICPENDR.
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*/
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for (i = 0; i < len * 8; i++) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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if (irq->pending_latch)
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value |= (1U << i);
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vgic_put_irq(vcpu->kvm, irq);
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}
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return value;
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}
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static void vgic_v3_uaccess_write_pending(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
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int i;
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for (i = 0; i < len * 8; i++) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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spin_lock(&irq->irq_lock);
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if (test_bit(i, &val)) {
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/*
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* pending_latch is set irrespective of irq type
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* (level or edge) to avoid dependency that VM should
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* restore irq config before pending info.
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*/
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irq->pending_latch = true;
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vgic_queue_irq_unlock(vcpu->kvm, irq);
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} else {
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irq->pending_latch = false;
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spin_unlock(&irq->irq_lock);
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}
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vgic_put_irq(vcpu->kvm, irq);
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}
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}
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/* We want to avoid outer shareable. */
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u64 vgic_sanitise_shareability(u64 field)
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{
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@ -356,7 +410,7 @@ static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu,
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* We take some special care here to fix the calculation of the register
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* offset.
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*/
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#define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, bpi, acc) \
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#define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, ur, uw, bpi, acc) \
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{ \
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.reg_offset = off, \
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.bits_per_irq = bpi, \
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@ -371,6 +425,8 @@ static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu,
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.access_flags = acc, \
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.read = rd, \
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.write = wr, \
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.uaccess_read = ur, \
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.uaccess_write = uw, \
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}
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static const struct vgic_register_region vgic_v3_dist_registers[] = {
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@ -378,40 +434,42 @@ static const struct vgic_register_region vgic_v3_dist_registers[] = {
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vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc, 16,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
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vgic_mmio_read_rao, vgic_mmio_write_wi, 1,
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vgic_mmio_read_rao, vgic_mmio_write_wi, NULL, NULL, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,
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vgic_mmio_read_enable, vgic_mmio_write_senable, 1,
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vgic_mmio_read_enable, vgic_mmio_write_senable, NULL, NULL, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,
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vgic_mmio_read_enable, vgic_mmio_write_cenable, 1,
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vgic_mmio_read_enable, vgic_mmio_write_cenable, NULL, NULL, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
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vgic_mmio_read_pending, vgic_mmio_write_spending, 1,
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vgic_mmio_read_pending, vgic_mmio_write_spending,
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vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
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vgic_mmio_read_pending, vgic_mmio_write_cpending, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
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vgic_mmio_read_active, vgic_mmio_write_sactive, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
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vgic_mmio_read_active, vgic_mmio_write_cactive, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
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vgic_mmio_read_priority, vgic_mmio_write_priority, 8,
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VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
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VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
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vgic_mmio_read_config, vgic_mmio_write_config, 2,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
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vgic_mmio_read_pending, vgic_mmio_write_cpending,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
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vgic_mmio_read_active, vgic_mmio_write_sactive, NULL, NULL, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
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vgic_mmio_read_active, vgic_mmio_write_cactive, NULL, NULL, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
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vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL,
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8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
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vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8,
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VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
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vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
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vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,
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vgic_mmio_read_irouter, vgic_mmio_write_irouter, 64,
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vgic_mmio_read_irouter, vgic_mmio_write_irouter, NULL, NULL, 64,
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VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
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vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
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@ -449,11 +507,13 @@ static const struct vgic_register_region vgic_v3_sgibase_registers[] = {
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REGISTER_DESC_WITH_LENGTH(GICR_ICENABLER0,
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vgic_mmio_read_enable, vgic_mmio_write_cenable, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_ISPENDR0,
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vgic_mmio_read_pending, vgic_mmio_write_spending, 4,
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REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ISPENDR0,
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vgic_mmio_read_pending, vgic_mmio_write_spending,
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vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_ICPENDR0,
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vgic_mmio_read_pending, vgic_mmio_write_cpending, 4,
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REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ICPENDR0,
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vgic_mmio_read_pending, vgic_mmio_write_cpending,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_ISACTIVER0,
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vgic_mmio_read_active, vgic_mmio_write_sactive, 4,
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@ -475,6 +475,74 @@ static bool check_region(const struct kvm *kvm,
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return false;
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}
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static const struct vgic_register_region *
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vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
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gpa_t addr, int len)
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{
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const struct vgic_register_region *region;
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region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
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addr - iodev->base_addr);
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if (!region || !check_region(vcpu->kvm, region, addr, len))
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return NULL;
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return region;
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}
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static int vgic_uaccess_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
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gpa_t addr, u32 *val)
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{
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struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
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const struct vgic_register_region *region;
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struct kvm_vcpu *r_vcpu;
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region = vgic_get_mmio_region(vcpu, iodev, addr, sizeof(u32));
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if (!region) {
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*val = 0;
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return 0;
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}
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r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
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if (region->uaccess_read)
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*val = region->uaccess_read(r_vcpu, addr, sizeof(u32));
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else
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*val = region->read(r_vcpu, addr, sizeof(u32));
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return 0;
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}
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static int vgic_uaccess_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
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gpa_t addr, const u32 *val)
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{
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struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
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const struct vgic_register_region *region;
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struct kvm_vcpu *r_vcpu;
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region = vgic_get_mmio_region(vcpu, iodev, addr, sizeof(u32));
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if (!region)
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return 0;
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r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
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if (region->uaccess_write)
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region->uaccess_write(r_vcpu, addr, sizeof(u32), *val);
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else
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region->write(r_vcpu, addr, sizeof(u32), *val);
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return 0;
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}
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/*
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* Userland access to VGIC registers.
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*/
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int vgic_uaccess(struct kvm_vcpu *vcpu, struct vgic_io_device *dev,
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bool is_write, int offset, u32 *val)
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{
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if (is_write)
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return vgic_uaccess_write(vcpu, &dev->dev, offset, val);
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else
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return vgic_uaccess_read(vcpu, &dev->dev, offset, val);
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}
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static int dispatch_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
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gpa_t addr, int len, void *val)
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{
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@ -482,9 +550,8 @@ static int dispatch_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
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const struct vgic_register_region *region;
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unsigned long data = 0;
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region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
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addr - iodev->base_addr);
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if (!region || !check_region(vcpu->kvm, region, addr, len)) {
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region = vgic_get_mmio_region(vcpu, iodev, addr, len);
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if (!region) {
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memset(val, 0, len);
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return 0;
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}
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@ -515,9 +582,8 @@ static int dispatch_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
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const struct vgic_register_region *region;
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unsigned long data = vgic_data_mmio_bus_to_host(val, len);
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region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
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addr - iodev->base_addr);
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if (!region || !check_region(vcpu->kvm, region, addr, len))
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region = vgic_get_mmio_region(vcpu, iodev, addr, len);
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if (!region)
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return 0;
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switch (iodev->iodev_type) {
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@ -34,6 +34,10 @@ struct vgic_register_region {
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gpa_t addr, unsigned int len,
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unsigned long val);
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};
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unsigned long (*uaccess_read)(struct kvm_vcpu *vcpu, gpa_t addr,
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unsigned int len);
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void (*uaccess_write)(struct kvm_vcpu *vcpu, gpa_t addr,
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unsigned int len, unsigned long val);
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};
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extern struct kvm_io_device_ops kvm_io_gic_ops;
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@ -86,6 +90,18 @@ extern struct kvm_io_device_ops kvm_io_gic_ops;
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.write = wr, \
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}
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#define REGISTER_DESC_WITH_LENGTH_UACCESS(off, rd, wr, urd, uwr, length, acc) \
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{ \
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.reg_offset = off, \
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.bits_per_irq = 0, \
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.len = length, \
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.access_flags = acc, \
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.read = rd, \
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.write = wr, \
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.uaccess_read = urd, \
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.uaccess_write = uwr, \
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}
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int kvm_vgic_register_mmio_region(struct kvm *kvm, struct kvm_vcpu *vcpu,
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struct vgic_register_region *reg_desc,
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struct vgic_io_device *region,
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@ -158,6 +174,9 @@ void vgic_mmio_write_config(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val);
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int vgic_uaccess(struct kvm_vcpu *vcpu, struct vgic_io_device *dev,
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bool is_write, int offset, u32 *val);
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unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev);
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unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev);
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